iommu/riscv: Enable IOMMU DMA mapping support
Subsystems (7)
A message that is not in the archive (sent off-list or not yet received): [email protected]
PATCH v5 1/8 iommu/riscv: Enable IOMMU DMA mapping support
From: Jingyu Li <[email protected]>
Enable IOMMU DMA mapping support for RISC-V, so that DMACs can be tested with translation enabled.
Known Possible Issue:
1. When CONFIG_IOMMU_DMA is enabled, on the tested Linux, RISC-V IOMMU is lack of PCIe support, causing riscv_iommu_fault:522 in dealing with NVMe PCIe devices.
--- drivers/iommu/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/iommu/Kconfig +1 -1
@@ -151,7 +151,7 @@ config OF_IOMMU # IOMMU-agnostic DMA-mapping layer config IOMMU_DMA - def_bool ARM64 || X86 || S390 + def_bool ARM64 || X86 || S390 || RISCV select DMA_OPS_HELPERS select IOMMU_API select IOMMU_IOVA
Signature · 7 lines
2.43.0 _______________________________________________ linux-riscv mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-riscv
PATCH v5 2/8 iommu/riscv: Add auxiliary bus framework and HPM device support
In reply to a message not in the archiveFrom: Jingyu Li <[email protected]>
Introduces auxiliary bus support for RISC-V IOMMU to enable modular extension of IOMMU capabilities. The framework allows creating auxiliary devices that can be bound to separate drivers.
The IOMMU HPM featured PMU device ("iommu.riscv_iommu_hpm.0") is created and registered as RISC-V IOMMU auxiliary device.
--- drivers/iommu/riscv/Kconfig | 1 + drivers/iommu/riscv/iommu-pci.c | 8 +- drivers/iommu/riscv/iommu-platform.c | 3 + drivers/iommu/riscv/iommu.c | 169 +++++++++++++++++++++++++++ drivers/iommu/riscv/iommu.h | 21 ++++ include/linux/riscv_iommu.h | 75 ++++++++++++ 6 files changed, 276 insertions(+), 1 deletion(-) create mode 100644 include/linux/riscv_iommu.h
drivers/iommu/riscv/Kconfig +1 -0
@@ -6,6 +6,7 @@ config RISCV_IOMMU depends on RISCV && 64BIT default y select IOMMU_API + select AUXILIARY_BUS help Support for implementations of the RISC-V IOMMU architecture that complements the RISC-V MMU capabilities, providing similar address
drivers/iommu/riscv/iommu-pci.c +7 -1
@@ -34,6 +34,8 @@ static int riscv_iommu_pci_probe(struct pci_dev *pdev, const struct pci_device_i {struct device *dev = &pdev->dev;struct riscv_iommu_device *iommu; +phys_addr_t reg_phys; +resource_size_t reg_size;int rc, vec; rc =pcim_enable_device (pdev);
@@ -43,7 +45,9 @@ static int riscv_iommu_pci_probe(struct pci_dev *pdev, const struct pci_device_iif (!(pci_resource_flags (pdev,0 ) &IORESOURCE_MEM ))return -ENODEV ; -if (pci_resource_len (pdev,0 ) <RISCV_IOMMU_REG_SIZE ) + reg_phys =pci_resource_start (pdev,0 ); + reg_size =pci_resource_len (pdev,0 ); +if (reg_size <RISCV_IOMMU_REG_SIZE )return -ENODEV ; rc =pcim_iomap_regions (pdev,BIT (0 ),pci_name (pdev));
@@ -56,6 +60,8 @@ static int riscv_iommu_pci_probe(struct pci_dev *pdev, const struct pci_device_i iommu->dev = dev; iommu->reg =pcim_iomap_table (pdev)[0 ]; + iommu->reg_phys = reg_phys; + iommu->reg_size = reg_size;pci_set_master (pdev);dev_set_drvdata (dev, iommu);
drivers/iommu/riscv/iommu-platform.c +3 -0
@@ -62,6 +62,9 @@ static int riscv_iommu_platform_probe(struct platform_device *pdev)return dev_err_probe (dev,PTR_ERR (iommu->reg),"could not map register region\n" ); + iommu->reg_phys = res->start; + iommu->reg_size =resource_size (res); +dev_set_drvdata (dev, iommu);/* Check device reported capabilities / features. */
drivers/iommu/riscv/iommu.c +169 -0
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drivers/iommu/riscv/iommu.h +21 -0
@@ -14,6 +14,7 @@#include <linux/iommu.h> #include <linux/types.h> #include <linux/iopoll.h> +#include <linux/riscv_iommu.h> #include "iommu-bits.h"
@@ -42,6 +43,8 @@ struct riscv_iommu_device {/* hardware control register space */ void __iomem *reg; +phys_addr_t reg_phys; +resource_size_t reg_size;/* supported and enabled hardware capabilities */ u64 caps;
@@ -60,11 +63,29 @@ struct riscv_iommu_device {unsigned int ddt_mode;dma_addr_t ddt_phys;u64 *ddt_root; + +/* auxiliary subdevices */ +spinlock_t subdev_lock; +struct list_head subdev_list; +}; + +/** +* struct riscv_iommu_subdev_params - params for adding auxiliary subdevice +* @name: auxiliary device name +* @info: device-specific info, freed in release +* @base: PMU register base +*/ +struct riscv_iommu_subdev_params { +const char *name; +void *info; +void __iomem *base; };int riscv_iommu_init (struct riscv_iommu_device *iommu);void riscv_iommu_remove (struct riscv_iommu_device *iommu);void riscv_iommu_disable (struct riscv_iommu_device *iommu); +void riscv_iommu_subdev_setup (struct riscv_iommu_device *iommu); +void riscv_iommu_subdev_cleanup (struct riscv_iommu_device *iommu);#define riscv_iommu_readl (iommu, addr) \ readl_relaxed((iommu)->reg + (addr))
include/linux/riscv_iommu.h new file +75 -0
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Signature · 1 line
2.43.0
PATCH v5 3/8 iommu/riscv: Add HPM support for performance monitoring
In reply to a message not in the archiveFrom: Jingyu Li <[email protected]>
Introduces perf-based HPM driver for RISC-V IOMMU, enabling performance monitoring capabilities.
Note that the RISC-V IOMMU HPM module uses COUNTER_MAX-1 as a static counter index of HPMCYCLES, and 0~COUNTER_MAX-2 as the dynamic counter indexes of other HPMEVENTS in order to correctly index into IOHPMEVT and IOHPMCTR registers that have already been defined in the iommu-bits.h. However the users treat 0 as the index of HPMCYCLES and 1~COUNTER_MAX-1 as the indexes of other HPMEVENTS, thus care should be taken in dealing with counter indexes between userspace and kernel space.
--- drivers/perf/Kconfig | 9 + drivers/perf/Makefile | 1 + drivers/perf/riscv_iommu_hpm.c | 864 +++++++++++++++++++++++++++++++++ 3 files changed, 874 insertions(+) create mode 100644 drivers/perf/riscv_iommu_hpm.c
drivers/perf/Kconfig +9 -0
@@ -311,4 +311,13 @@ config MARVELL_PEM_PMU Enable support for PCIe Interface performance monitoring on Marvell platform. +config RISCV_IOMMU_HPM + tristate "RISC-V IOMMU HPM support" + depends on RISCV_IOMMU && PERF_EVENTS + help + Support for the Hardware Performance Monitor (HPM) in RISC-V IOMMU, + which provides monitoring of transactions passing through the + IOMMU and allows the resulting information to be filtered based + on the device/process ID of the corresponding master. + endmenu
drivers/perf/Makefile +1 -0
@@ -35,3 +35,4 @@ obj-$(CONFIG_DWC_PCIE_PMU) += dwc_pcie_pmu.o obj-$(CONFIG_ARM_CORESIGHT_PMU_ARCH_SYSTEM_PMU) += arm_cspmu/ obj-$(CONFIG_MESON_DDR_PMU) += amlogic/ obj-$(CONFIG_CXL_PMU) += cxl_pmu.o +obj-$(CONFIG_RISCV_IOMMU_HPM) += riscv_iommu_hpm.o
drivers/perf/riscv_iommu_hpm.c new file +864 -0
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Signature · 1 line
2.43.0
PATCH v5 4/8 dt-bindings: iommu: Add spacemit/t100 features
In reply to a message not in the archiveAdds device tree bindings for SpacemiT T100 specific features by introducing spacemit,t100 compatible. T100 contains distributed IOATCs, each of which exposes pmiv interrupt.
--- .../bindings/iommu/riscv,iommu.yaml | 58 ++++++++++++++++++- 1 file changed, 56 insertions(+), 2 deletions(-)
Documentation/devicetree/bindings/iommu/riscv,iommu.yaml +56 -2
@@ -30,8 +30,19 @@ properties: # Since PCI provides built-in identification methods, compatible is not # actually required. For non-PCIe hardware implementations 'riscv,iommu' # should be specified along with 'reg' property providing MMIO location. + # SpacemiT T100 (distributed IOMMU with split IOATCs placed in adjacent + # to the DMA masters) can be seen in SpacemiT SoCs. It is integerated in + # V100 (server SoC) with coherent page table walk supported and in K3 + # (client SoC) without coherent page table walk supported. compatible: oneOf: + - description: SpacemiT distributed IOMMUs + items: + - enum: + - spacemit,k3-t100 + - spacemit,v100-t100 + - const: spacemit,t100 + - const: riscv,iommu - items: - enum: - qemu,riscv-iommu
@@ -57,11 +68,21 @@ properties: interrupts: minItems: 1 - maxItems: 4 + maxItems: 68 description: Wired interrupt vectors available for RISC-V IOMMU to notify the RISC-V HARTS. The cause to interrupt vector is software defined - using IVEC IOMMU register. + using ICVEC IOMMU register. For WSI only mode, the number of the + interrupt vectors should be 1 while for MSI possible mode, the + maximum of the interrupt vectors should be 4 with the cause indexed + as "CIV=0, FIV=1, PIV=2, PMIV=3". + SpacemiT distributed IOMMU includes additional interrupts for + IOATCs. Each IOATC exposes PMIV wired vector as standalone + interrupt and the maximum number of IOATCs can be up to 64. Thus for + WSI only mode, the maximum number of the interrupt vectors should be + 65 while for MSI possible mode, the maximum number of the interrupt + vectors should be 68 with the cause indexed as "IOATS CIV=0, + IOATS FIV=1, IOATS PIV=2, IOATS PMIV=3, IOATC0..n PMIV=4..4+n". msi-parent: true
@@ -75,6 +96,18 @@ required: additionalProperties: false +allOf: + - if: + properties: + compatible: + not: + contains: + const: spacemit,t100 + then: + properties: + interrupts: + maxItems: 4 + examples: - |+ /* Example 1 (IOMMU device with wired interrupts) */
@@ -145,3 +178,24 @@ examples: }; }; }; + + - |+ + /* Example 5 (SpacemiT distributed IOMMU) */ + #include <dt-bindings/interrupt-controller/irq.h> + + iommu4: iommu@1bccd000 { + compatible = "spacemit,k3-t100", "spacemit,t100", "riscv,iommu"; + reg = <0x1bccd000 0x1000>; + interrupts = <58 IRQ_TYPE_LEVEL_HIGH>, + <62 IRQ_TYPE_LEVEL_HIGH>, <63 IRQ_TYPE_LEVEL_HIGH>, + <62 IRQ_TYPE_LEVEL_HIGH>, <63 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&saplic>; + #iommu-cells = <0x01>; + }; + + /* Device with four IOMMU device IDs */ + master2 { + #iommu-cells = <1>; + iommus = <&iommu4 0xc0010>, <&iommu4 0xc0011>, + <&iommu4 0xc0012>, <&iommu4 0xc0013>; + };
Signature · 7 lines
2.43.0 _______________________________________________ linux-riscv mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-riscv
Re: [PATCH v5 4/8] dt-bindings: iommu: Add spacemit/t100 features
Quoted 6 lines · Lv Zheng
Adds device tree bindings for SpacemiT T100 specific features by introducing spacemit,t100 compatible. T100 contains distributed IOATCs, each of which exposes pmiv interrupt.
Signed-off-by Lv Zheng <[email protected]>Signed-off-by Jingyu Li <[email protected]>
Patch content here is fine, but the signoff chain on this patch is not right. What did Jingyu do? You're author and submitter so either Jingyu did nothing and should be removed, or is a co-developer which requires attribution via the co-developed-by tag. If the latter, their signoff should be before yours (the submitter is always last).
pw-bot: changes-requested
Cheers,
Conor.
Signature · 1 line
Conor Dooley <[email protected]>
Re: [PATCH v5 4/8] dt-bindings: iommu: Add spacemit/t100 features
Quoted 8 lines · Conor Dooley
Quoted 6 lines · Lv Zheng
Adds device tree bindings for SpacemiT T100 specific features by introducing spacemit,t100 compatible. T100 contains distributed IOATCs, each of which exposes pmiv interrupt.
Signed-off-by Lv Zheng <[email protected]>Signed-off-by Jingyu Li <[email protected]>
Quoted 7 lines
Patch content here is fine, but the signoff chain on this patch is not right. What did Jingyu do? You're author and submitter so either Jingyu did nothing and should be removed, or is a co-developer which requires attribution via the co-developed-by tag. If the latter, their signoff should be before yours (the submitter is always last).
pw-bot: changes-requested
She is responsible for the common HPM part, and I just gave my comments to help to improve the quality of that implementation. I was just focusing on enabling and maintaining the T100 specific features.
Our patches will go each other's local repository, leaving such tracks. That means the patch from me is Reviewed-and-tested-by her. And I'm responsible for sending the whole patchset for upstreaming.
Cheers,
Lv
Quoted 4 lines
Cheers,
Conor.
Re: [PATCH v5 4/8] dt-bindings: iommu: Add spacemit/t100 features
Quoted 17 lines · Lv Zheng
Quoted 8 lines · Conor Dooley
Quoted 6 lines · Lv Zheng
Adds device tree bindings for SpacemiT T100 specific features by introducing spacemit,t100 compatible. T100 contains distributed IOATCs, each of which exposes pmiv interrupt.
Signed-off-by Lv Zheng <[email protected]>Signed-off-by Jingyu Li <[email protected]>Quoted 7 lines
Patch content here is fine, but the signoff chain on this patch is not right. What did Jingyu do? You're author and submitter so either Jingyu did nothing and should be removed, or is a co-developer which requires attribution via the co-developed-by tag. If the latter, their signoff should be before yours (the submitter is always last).
pw-bot: changes-requested
Quoted 7 lines
She is responsible for the common HPM part, and I just gave my comments to help to improve the quality of that implementation.
I was just focusing on enabling and maintaining the T100 specific features.Our patches will go each other's local repository, leaving such tracks. That means the patch from me is Reviewed-and-tested-by her.
And I'm responsible for sending the whole patchset for upstreaming.
Then you need to either fix your email setup (because it's not inserting
From: Jingyu Li <[email protected]>) so that she is marked as the author or actually set her to the author in git if you haven't. Currently it looks like this when applied:
commit 872978c875731be43e84bec38798cb8ecd42b7a0
Author: Lv Zheng <[email protected]> Date: Sat Feb 28 22:44:49 2026 +0800
dt-bindings: iommu: Add spacemit/t100 features
Adds device tree bindings for SpacemiT T100 specific features by introducing spacemit,t100 compatible. T100 contains distributed IOATCs, each of which exposes pmiv interrupt.
In both cases, you need to change the order of signoffs so that yours is last as the submitter.
Re: [PATCH v5 4/8] dt-bindings: iommu: Add spacemit/t100 features
Quoted 40 lines · Conor Dooley
Quoted 17 lines · Lv Zheng
Quoted 8 lines · Conor Dooley
Quoted 6 lines · Lv Zheng
Adds device tree bindings for SpacemiT T100 specific features by introducing spacemit,t100 compatible. T100 contains distributed IOATCs, each of which exposes pmiv interrupt.
Signed-off-by Lv Zheng <[email protected]>Signed-off-by Jingyu Li <[email protected]>Quoted 7 lines
Patch content here is fine, but the signoff chain on this patch is not right. What did Jingyu do? You're author and submitter so either Jingyu did nothing and should be removed, or is a co-developer which requires attribution via the co-developed-by tag. If the latter, their signoff should be before yours (the submitter is always last).
pw-bot: changes-requested
Quoted 7 lines
She is responsible for the common HPM part, and I just gave my comments to help to improve the quality of that implementation.
I was just focusing on enabling and maintaining the T100 specific features.Our patches will go each other's local repository, leaving such tracks. That means the patch from me is Reviewed-and-tested-by her.
And I'm responsible for sending the whole patchset for upstreaming.Then you need to either fix your email setup (because it's not inserting
From: Jingyu Li <[email protected]>) so that she is marked as the author or actually set her to the author in git if you haven't. Currently it looks like this when applied:
commit872978c875731be43e84bec38798cb8ecd42b7a0Author: Lv Zheng <[email protected]> Date: Sat Feb 28 22:44:49 2026 +0800dt-bindings: iommu: Add spacemit/t100 features
Adds device tree bindings for SpacemiT T100 specific features by introducing spacemit,t100 compatible. T100 contains distributed IOATCs, each of which exposes pmiv interrupt.
Quoted 5 lines
Signed-off-by Lv Zheng <[email protected]>Signed-off-by Jingyu Li <[email protected]>In both cases, you need to change the order of signoffs so that yours is last as the submitter.
OK.
BTW, since this version of this patch has been worked out all due your constructive feedback and suggestions. Now that it has functionally converged to what the community requested, can I add "Reviewed-by: Conor Dooley <[email protected]>" for its next version?
Best regards,
Lv
Re: [PATCH v5 4/8] dt-bindings: iommu: Add spacemit/t100 features
Quoted 42 lines · Lv Zheng
Quoted 41 lines · Conor Dooley
Quoted 17 lines · Lv Zheng
Quoted 8 lines · Conor Dooley
Quoted 6 lines · Lv Zheng
Adds device tree bindings for SpacemiT T100 specific features by introducing spacemit,t100 compatible. T100 contains distributed IOATCs, each of which exposes pmiv interrupt.
Signed-off-by Lv Zheng <[email protected]>Signed-off-by Jingyu Li <[email protected]>Quoted 7 lines
Patch content here is fine, but the signoff chain on this patch is not right. What did Jingyu do? You're author and submitter so either Jingyu did nothing and should be removed, or is a co-developer which requires attribution via the co-developed-by tag. If the latter, their signoff should be before yours (the submitter is always last).
pw-bot: changes-requested
Quoted 7 lines
She is responsible for the common HPM part, and I just gave my comments to help to improve the quality of that implementation.
I was just focusing on enabling and maintaining the T100 specific features.Our patches will go each other's local repository, leaving such tracks. That means the patch from me is Reviewed-and-tested-by her.
And I'm responsible for sending the whole patchset for upstreaming.Then you need to either fix your email setup (because it's not inserting
From: Jingyu Li <[email protected]>) so that she is marked as the author or actually set her to the author in git if you haven't. Currently it looks like this when applied:
commit872978c875731be43e84bec38798cb8ecd42b7a0Author: Lv Zheng <[email protected]> Date: Sat Feb 28 22:44:49 2026 +0800dt-bindings: iommu: Add spacemit/t100 features
Adds device tree bindings for SpacemiT T100 specific features by introducing spacemit,t100 compatible. T100 contains distributed IOATCs, each of which exposes pmiv interrupt.Signed-off-by Lv Zheng <[email protected]>Signed-off-by Jingyu Li <[email protected]>
Quoted 7 lines
Quoted 2 lines
In both cases, you need to change the order of signoffs so that yours is last as the submitter.
BTW, since this version of this patch has been worked out all due your constructive feedback and suggestions. Now that it has functionally converged to what the community requested, can I add "Reviewed-by: Conor Dooley <[email protected]>" for its next version?
No, as I said the previous time you asked, I will provide one when I am happy with the patch. I have not yet reached a point with you were I am comfortable providing tags with the assumption that you will make the correct changes. There's no need to hassle me for one at this point anyway, because you have to send a v6 anyway. If v6 is satisfactory to the maintainers, they'll grab my tag when they apply the series.
Cheers,
Conor.
PATCH v5 5/8 spacemit/t100: Add global filter awareness for RISC-V IOMMU HPM
In reply to a message not in the archiveAdds global filter support for RISC-V IOMMU HPM. The global filter can be seen in SpacemiT T100 which only supports single filter to be applied to all event counters.
Drivers can program filters in each iohpmevt registers as normal in such a silicon design, however the underlying hardware filters are wired together as a global filter applying to all iohpmevt(s). Since the mechanism is compatible with standard iohpmevt in programming interface, only adds sanity checks to allow it to be configured with "global" awareness to inform users a filter incompatiblity.
--- drivers/iommu/riscv/iommu.c | 5 ++ drivers/perf/riscv_iommu_hpm.c | 94 ++++++++++++++++++++++++++++++++-- include/linux/riscv_iommu.h | 2 + 3 files changed, 96 insertions(+), 5 deletions(-)
drivers/iommu/riscv/iommu.c +5 -0
@@ -1717,6 +1717,11 @@ static void riscv_iommu_enumerate_hpm(struct riscv_iommu_device *iommu) .base = iommu->reg + RISCV_IOMMU_REG_IOCOUNTOVF, }; +if (of_device_is_compatible (iommu->dev->of_node,"spacemit,t100" )) { + hpm_info->global_filter = true; + params.name ="spacemit_ioats_hpm" ; + } + ret =riscv_iommu_subdev_add (iommu, ¶ms);if (ret) {kfree (hpm_info);
drivers/perf/riscv_iommu_hpm.c +89 -5
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include/linux/riscv_iommu.h +2 -0
@@ -36,9 +36,11 @@ struct riscv_iommu_subdev {/** * struct riscv_iommu_hpm_info - HPM info for IOATS (main IOMMU HPM) * @irq: interrupt number +* @global_filter: true if single global filter */ struct riscv_iommu_hpm_info {unsigned int irq; +bool global_filter; };/**
Signature · 1 line
2.43.0
PATCH v5 6/8 iommu/riscv: Add SpacemiT T100 IOATC HPM support
In reply to a message not in the archiveAdd IOATC discovery and HPM support for SpacemiT T100.
SpacemiT T100 supports distributed architecture which allows IOTLBs to be cached in adjacent to the DMA masters. Such IOTLB controllers are called as IOATCs. Adds distributed HPM support for IOATCs.
--- drivers/iommu/riscv/iommu-bits.h | 12 +++ drivers/iommu/riscv/iommu-platform.c | 4 +- drivers/iommu/riscv/iommu.c | 107 ++++++++++++++++++++++++++- drivers/iommu/riscv/iommu.h | 2 +- drivers/perf/riscv_iommu_hpm.c | 48 +++++++++++- include/linux/riscv_iommu.h | 6 +- 6 files changed, 171 insertions(+), 8 deletions(-)
drivers/iommu/riscv/iommu-bits.h +12 -0
@@ -278,6 +278,14 @@ enum riscv_iommu_hpmevent_id {#define RISCV_IOMMU_ICVEC_PMIV GENMASK_ULL(11, 8)#define RISCV_IOMMU_ICVEC_PIV GENMASK_ULL(15, 12) +/* 5.28 Distributed translation interface status register (dtisr0-3) (4 * 32-bits) */ +#define RISCV_IOMMU_REG_DTISR_BASE 0x02B0 +#define RISCV_IOMMU_REG_DTISR (_n) (RISCV_IOMMU_REG_DTISR_BASE + ((_n) * 0x04)) +#define RISCV_IOMMU_DTI_STS_SHIFT (_n) (((_n) % 16) * 2) +#define RISCV_IOMMU_DTI_STS_MASK (_n) (0x3 << RISCV_IOMMU_DTI_STS_SHIFT(_n)) +#define RISCV_IOMMU_DTI_STS_NONE 0x0 +#define RISCV_IOMMU_DTI_STS_IOATC 0x1 +/* 5.28 MSI Configuration table (32 * 64bits) */ #define RISCV_IOMMU_REG_MSI_CFG_TBL 0x0300#define RISCV_IOMMU_REG_MSI_CFG_TBL_ADDR (_n) \
@@ -292,6 +300,10 @@ enum riscv_iommu_hpmevent_id {#define RISCV_IOMMU_REG_SIZE 0x1000 +/* SpacemiT IOMMU IOATC registers */ +#define MAX_RISCV_IOMMU_IOATC 64 +#define RISCV_IOMMU_IOATC_BASE (_idx) (((_idx) + 1) * RISCV_IOMMU_REG_SIZE) +/* * Chapter 2: Data structures */
drivers/iommu/riscv/iommu-platform.c +2 -2
@@ -75,8 +75,8 @@ static int riscv_iommu_platform_probe(struct platform_device *pdev)if (iommu->irqs_count <=0 )return dev_err_probe (dev, -ENODEV ,"no IRQ resources provided\n" ); -if (iommu->irqs_count >RISCV_IOMMU_INTR_COUNT ) - iommu->irqs_count =RISCV_IOMMU_INTR_COUNT ; +if (iommu->irqs_count >RISCV_IOMMU_INTR_COUNT +MAX_RISCV_IOMMU_IOATC ) + iommu->irqs_count =RISCV_IOMMU_INTR_COUNT +MAX_RISCV_IOMMU_IOATC ; igs =FIELD_GET (RISCV_IOMMU_CAPABILITIES_IGS , iommu->caps);switch (igs) {
drivers/iommu/riscv/iommu.c +105 -2
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drivers/iommu/riscv/iommu.h +1 -1
@@ -51,7 +51,7 @@ struct riscv_iommu_device {u32 fctl;/* available interrupt numbers, MSI or WSI */ -unsigned int irqs[RISCV_IOMMU_INTR_COUNT ]; +unsigned int irqs[RISCV_IOMMU_INTR_COUNT +MAX_RISCV_IOMMU_IOATC ];unsigned int irqs_count;unsigned int icvec;
drivers/perf/riscv_iommu_hpm.c +46 -2
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include/linux/riscv_iommu.h +5 -1
@@ -34,13 +34,17 @@ struct riscv_iommu_subdev { };/** -* struct riscv_iommu_hpm_info - HPM info for IOATS (main IOMMU HPM) +* struct riscv_iommu_hpm_info - HPM info for IOATS and IOATC * @irq: interrupt number * @global_filter: true if single global filter +* @is_ioatc: false for IOATS, true for IOATC +* @index: DTISR index for IOATC (0-63), 0 for IOATS */ struct riscv_iommu_hpm_info {unsigned int irq;bool global_filter; +bool is_ioatc; +u8 index; };/**
Signature · 1 line
2.43.0
PATCH v5 7/8 iommu/riscv: Add vendor event support for RISC-V IOMMU HPM
In reply to a message not in the archiveAdd a mechanism to allow vendor events to be registered via userspace jevents. The PMU exposes an "identifier" sysfs attribute derived from the device tree compatible string (e.g. "spacemit,t100" or "riscv,iommu"), which perf's jevents uses to match JSON event definitions to the PMU.
--- drivers/iommu/riscv/iommu.c | 29 +++++++++++++++++++++++++++++ drivers/iommu/riscv/iommu.h | 2 ++ drivers/perf/riscv_iommu_hpm.c | 22 +++++++++++++++++++++- include/linux/riscv_iommu.h | 2 ++ 4 files changed, 54 insertions(+), 1 deletion(-)
drivers/iommu/riscv/iommu.c +29 -0
@@ -1664,6 +1664,7 @@ static int riscv_iommu_subdev_add(struct riscv_iommu_device *iommu, subdev->base = params->base; subdev->iommu = iommu; subdev->info = params->info; + subdev->identifier = params->identifier; auxdev = &subdev->auxdev; auxdev->name = params->name;
@@ -1701,6 +1702,32 @@ static int riscv_iommu_subdev_add(struct riscv_iommu_device *iommu,return ret; } +/* Compatible strings that serve as PMU identifier for userspace jevents */ +static const char *const riscv_iommu_hpm_identifiers[] = { +"spacemit,t100" , +"riscv,iommu" , +}; + +static const char *riscv_iommu_get_hpm_identifier (struct device *dev) +{ +struct device_node *np = dev->of_node; +int i, ret; + +if (!np) +return NULL ; + +for (i =0 ; i <ARRAY_SIZE (riscv_iommu_hpm_identifiers); i++) { + ret =of_property_match_string (np,"compatible" , + riscv_iommu_hpm_identifiers[i]); +if (ret >=0 ) +return devm_kstrdup (dev, + riscv_iommu_hpm_identifiers[i], +GFP_KERNEL ); + } + +return NULL ; +} +static void riscv_iommu_enumerate_hpm (struct riscv_iommu_device *iommu) {struct riscv_iommu_hpm_info *hpm_info;
@@ -1728,6 +1755,7 @@ static void riscv_iommu_enumerate_hpm(struct riscv_iommu_device *iommu) .name = "riscv_iommu_hpm", .info = hpm_info, .base = iommu->reg + RISCV_IOMMU_REG_IOCOUNTOVF, + .identifier = riscv_iommu_get_hpm_identifier(iommu->dev), };if (of_device_is_compatible (iommu->dev->of_node,"spacemit,t100" )) {
@@ -1822,6 +1850,7 @@ static void riscv_iommu_enumerate_ioatc(struct riscv_iommu_device *iommu) .name = "spacemit_ioatc_hpm", .info = ioatc_info, .base = base + RISCV_IOMMU_REG_IOCOUNTOVF, + .identifier = riscv_iommu_get_hpm_identifier(iommu->dev), }; ret =riscv_iommu_subdev_add (iommu, ¶ms);
drivers/iommu/riscv/iommu.h +2 -0
@@ -74,11 +74,13 @@ struct riscv_iommu_device {* @name: auxiliary device name * @info: device-specific info, freed in release * @base: PMU register base +* @identifier: perf PMU identifier for JSON Compat matching */ struct riscv_iommu_subdev_params {const char *name;void *info;void __iomem *base; +const char *identifier; };int riscv_iommu_init (struct riscv_iommu_device *iommu);
drivers/perf/riscv_iommu_hpm.c +21 -1
@@ -88,6 +88,7 @@ struct riscv_iommu_hpm {unsigned int irq;unsigned int on_cpu;bool global_filter; +const char *identifier;struct hlist_node node;/* * Layout of events:
@@ -664,8 +665,24 @@ static ssize_t riscv_iommu_hpm_global_filter_show(struct device *dev,static struct device_attribute riscv_iommu_hpm_global_filter_attr =__ATTR (global_filter,0444 , riscv_iommu_hpm_global_filter_show,NULL ); +static ssize_t riscv_iommu_hpm_identifier_show (struct device *dev, +struct device_attribute *attr, +char *buf) +{ +struct riscv_iommu_hpm *hpm =dev_get_drvdata (dev); + +if (!hpm->identifier) +return 0 ; + +return sysfs_emit (buf,"%s\n" , hpm->identifier); +} + +static struct device_attribute riscv_iommu_hpm_identifier_attr = +__ATTR (identifier,0444 , riscv_iommu_hpm_identifier_show,NULL ); +static struct attribute *riscv_iommu_hpm_vendor_attrs[] = { &riscv_iommu_hpm_global_filter_attr.attr, + &riscv_iommu_hpm_identifier_attr.attr,NULL };
@@ -891,6 +908,7 @@ static int riscv_iommu_hpm_probe(struct auxiliary_device *auxdev, hpm->subdev = subdev; hpm->base = subdev->base; + hpm->identifier = subdev->identifier; hpm->on_cpu =raw_smp_processor_id (); hpm->irq = info->irq; hpm->global_filter = info->global_filter;
@@ -914,7 +932,9 @@ static int riscv_iommu_hpm_probe(struct auxiliary_device *auxdev, attr_grps = is_ioatc ? riscv_iommu_hpm_ioatc_attr_grps : riscv_iommu_hpm_attr_grps; - hpm_name =devm_kstrdup (dev,dev_name (dev),GFP_KERNEL ); +/* jevents name: auxdev->name + "_" + auxdev->id */ + hpm_name =devm_kasprintf (dev,GFP_KERNEL ,"%s_%u" , auxdev->name, + auxdev->id);if (!hpm_name)return -ENOMEM ;
include/linux/riscv_iommu.h +2 -0
@@ -24,6 +24,7 @@ struct riscv_iommu_device;* @base: PMU register base * @iommu: parent IOMMU (opaque) * @info: subdevice-specific info, freed in release +* @identifier: Vendor identifier for userspace jevent */ struct riscv_iommu_subdev {struct list_head link;
@@ -31,6 +32,7 @@ struct riscv_iommu_subdev {void __iomem *base;struct riscv_iommu_device *iommu;void *info; +const char *identifier; };/**
Signature · 1 line
2.43.0
PATCH v5 8/8 perf vendor events riscv: Add SpacemiT T100 HPM event aliases
In reply to a message not in the archiveAdd JSON HPM event aliases for SpacemiT distributed IOMMU (T100) which is general and compatible for all SpacemiT RISC-V SoCs.
--- MAINTAINERS | 5 + .../arch/riscv/spacemit/iommu/sys/ioatc.json | 30 ++++ .../arch/riscv/spacemit/iommu/sys/ioats.json | 163 ++++++++++++++++++ 3 files changed, 198 insertions(+) create mode 100644 tools/perf/pmu-events/arch/riscv/spacemit/iommu/sys/ioatc.json create mode 100644 tools/perf/pmu-events/arch/riscv/spacemit/iommu/sys/ioats.json
MAINTAINERS +5 -0
@@ -22459,12 +22459,17 @@ K: riscv RISC-V IOMMU M: Tomasz Jeznach <[email protected]> +M: Lv Zheng <[email protected]> +M: Jingyu Li <[email protected]> L: [email protected] L: [email protected] S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux.git F: Documentation/devicetree/bindings/iommu/riscv,iommu.yaml F: drivers/iommu/riscv/ +F: drivers/perf/riscv_iommu_hpm.c +F: include/linux/riscv_iommu.h +F: tools/perf/pmu-events/arch/riscv/spacemit/iommu/ RISC-V MICROCHIP SUPPORT M: Conor Dooley <[email protected]>
tools/perf/pmu-events/arch/riscv/spacemit/iommu/sys/ioatc.json new file +30 -0
@@ -0,0 +1,30 @@ +[ + { + "EventName": "mtlb_lkp", + "EventCode": "0x38", + "BriefDescription": "IOATC main TLB (MTLB) lookups", + "Unit": "spacemit_ioatc_hpm", + "Compat": "spacemit,t100" + }, + { + "EventName": "mtlb_mis", + "EventCode": "0x39", + "BriefDescription": "IOATC main TLB (MTLB) misses", + "Unit": "spacemit_ioatc_hpm", + "Compat": "spacemit,t100" + }, + { + "EventName": "utlb_lkp", + "EventCode": "0x3A", + "BriefDescription": "IOATC micro TLB (uTLB) lookups", + "Unit": "spacemit_ioatc_hpm", + "Compat": "spacemit,t100" + }, + { + "EventName": "utlb_mis", + "EventCode": "0x3B", + "BriefDescription": "IOATC micro TLB (uTLB) misses", + "Unit": "spacemit_ioatc_hpm", + "Compat": "spacemit,t100" + } +]
tools/perf/pmu-events/arch/riscv/spacemit/iommu/sys/ioats.json new file +163 -0
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Signature · 1 line
2.43.0