ARM: dts: aspeed-g6: add AST2600 I3C nodes and bindings
v4 cover ARM: dts: aspeed-g6: add AST2600 I3C nodes and bindings
This series reworks and resubmits AST2600 I3C DTS updates that were originally posted in 2024, but stalled without further upstream progress.[1] The series was rebased onto the current tree and merge conflicts were resolved.
The patches first move I2C controller nodes under the APB simple-bus for layout consistency, then document aspeed,ast2600-i3c-global in the syscon binding, and finally add AST2600 I3C controller nodes in aspeed-g6.dtsi.
Jeremy agreed in a separate email thread that I can continue this series under my authorship.
Dawid Glazik (3):
ARM: dts: aspeed-g6: move i2c controllers directly into apb node
dt-bindings: mfd: syscon: add aspeed,ast2600-i3c-global compatible
ARM: dts: aspeed-g6: Add nodes for i3c controllers
.../devicetree/bindings/mfd/syscon.yaml | 2 + arch/arm/boot/dts/aspeed/aspeed-g6.dtsi | 543 ++++++++++-------- 2 files changed, 318 insertions(+), 227 deletions(-)
base-commit: 6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f
Signature · 1 line
2.43.0
PATCH v4 1/3 ARM: dts: aspeed-g6: move i2c controllers directly into apb node
We currently have the apb's mapping of the i2c controller space as a labelled mostly-empty node:
apb {
i2c: bus@1e78a000 {
ranges = <...>;
};
}... and then define the contents of the i2c block later:
i2c: {
i2c0: i2c-bus@80 {
reg = <0x80 0x80>;
};
i2c1: i2c-bus@100 {
reg = <0x100 0x80>;
};
}Krzysztof mentions[1] that isn't convention though, with the top-level simple-bus being empty and linked via the label. So, drop the label usage and move the i2c bus definition into the simple-bus node directly under the apb:
apb {
bus@1e78a000 {
ranges = <...>; i2c0: i2c-bus@80 {
reg = <0x80 0x80>;
};
i2c1: i2c-bus@100 {
reg = <0x100 0x80>;
};
};}
This will allow us to be consistent when we add new definitions for the i3c nodes, which would require the latter format.
---
v3:
- pick up series after two years
- rebase on top of latest tree and solve conflicts
- as agreed with Jeremy off-list, he said I can take authorship of this going forward
v2:
- new patch: reorganise i2c nodes before adding new-format i3c nodes
--- arch/arm/boot/dts/aspeed/aspeed-g6.dtsi | 452 ++++++++++++------------ 1 file changed, 225 insertions(+), 227 deletions(-)
arch/arm/boot/dts/aspeed/aspeed-g6.dtsi +225 -227
@@ -835,11 +835,235 @@ uart9: serial@1e790300 { status = "disabled"; }; - i2c: bus@1e78a000 { + bus@1e78a000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x1e78a000 0x1000>; + + i2c0: i2c@80 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x80 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_default>; + status = "disabled"; + }; + + i2c1: i2c@100 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x100 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_default>; + status = "disabled"; + }; + + i2c2: i2c@180 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x180 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_default>; + status = "disabled"; + }; + + i2c3: i2c@200 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x200 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4_default>; + status = "disabled"; + }; + + i2c4: i2c@280 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x280 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c5_default>; + status = "disabled"; + }; + + i2c5: i2c@300 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x300 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c6_default>; + status = "disabled"; + }; + + i2c6: i2c@380 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x380 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c7_default>; + status = "disabled"; + }; + + i2c7: i2c@400 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x400 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c8_default>; + status = "disabled"; + }; + + i2c8: i2c@480 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x480 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c9_default>; + status = "disabled"; + }; + + i2c9: i2c@500 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x500 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c10_default>; + status = "disabled"; + }; + + i2c10: i2c@580 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x580 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c11_default>; + status = "disabled"; + }; + + i2c11: i2c@600 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x600 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c12_default>; + status = "disabled"; + }; + + i2c12: i2c@680 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x680 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c13_default>; + status = "disabled"; + }; + + i2c13: i2c@700 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x700 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c14_default>; + status = "disabled"; + }; + + i2c14: i2c@780 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x780 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c15_default>; + status = "disabled"; + }; + + i2c15: i2c@800 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x800 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c16_default>; + status = "disabled"; + }; }; fsim0: fsi@1e79b000 {
@@ -870,229 +1094,3 @@ fsim1: fsi@1e79b100 { }; #include "aspeed-g6-pinctrl.dtsi" - -&i2c { - i2c0: i2c@80 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x80 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1_default>; - status = "disabled"; - }; - - i2c1: i2c@100 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x100 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2_default>; - status = "disabled"; - }; - - i2c2: i2c@180 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x180 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3_default>; - status = "disabled"; - }; - - i2c3: i2c@200 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x200 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4_default>; - status = "disabled"; - }; - - i2c4: i2c@280 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x280 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c5_default>; - status = "disabled"; - }; - - i2c5: i2c@300 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x300 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c6_default>; - status = "disabled"; - }; - - i2c6: i2c@380 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x380 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c7_default>; - status = "disabled"; - }; - - i2c7: i2c@400 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x400 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c8_default>; - status = "disabled"; - }; - - i2c8: i2c@480 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x480 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c9_default>; - status = "disabled"; - }; - - i2c9: i2c@500 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x500 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c10_default>; - status = "disabled"; - }; - - i2c10: i2c@580 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x580 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c11_default>; - status = "disabled"; - }; - - i2c11: i2c@600 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x600 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c12_default>; - status = "disabled"; - }; - - i2c12: i2c@680 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x680 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c13_default>; - status = "disabled"; - }; - - i2c13: i2c@700 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x700 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c14_default>; - status = "disabled"; - }; - - i2c14: i2c@780 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x780 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c15_default>; - status = "disabled"; - }; - - i2c15: i2c@800 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x800 0x80>; - compatible = "aspeed,ast2600-i2c-bus"; - clocks = <&syscon ASPEED_CLK_APB2>; - resets = <&syscon ASPEED_RESET_I2C>; - interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; - bus-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c16_default>; - status = "disabled"; - }; -};
Signature · 1 line
2.43.0
PATCH v4 2/3 dt-bindings: mfd: syscon: add aspeed,ast2600-i3c-global compatible
In reply to Dawid GlazikAdd aspeed,ast2600-i3c-global to the syscon binding compatible lists to document the AST2600 I3C global register syscon node.
--- Documentation/devicetree/bindings/mfd/syscon.yaml | 2 ++ 1 file changed, 2 insertions(+)
Documentation/devicetree/bindings/mfd/syscon.yaml +2 -0
@@ -49,6 +49,7 @@ select: - apm,xgene-mcb - apm,xgene-rb - apm,xgene-scu + - aspeed,ast2600-i3c-global - atmel,sama5d2-sfrbu - atmel,sama5d3-nfc-io - atmel,sama5d3-sfrbu
@@ -161,6 +162,7 @@ properties: - apm,xgene-mcb - apm,xgene-rb - apm,xgene-scu + - aspeed,ast2600-i3c-global - atmel,sama5d2-sfrbu - atmel,sama5d3-nfc-io - atmel,sama5d3-sfrbu
Signature · 1 line
2.43.0
Re: [PATCH v4 2/3] dt-bindings: mfd: syscon: add aspeed,ast2600-i3c-global compatible
Quoted 7 lines · Dawid Glazik
Add aspeed,ast2600-i3c-global to the syscon binding compatible lists to document the AST2600 I3C global register syscon node.
Signed-off-by Dawid Glazik <[email protected]>--- Documentation/devicetree/bindings/mfd/syscon.yaml | 2 ++ 1 file changed, 2 insertions(+)
Best regards,
Krzysztof
Andrew Jeffery
maintainerRe: [PATCH v4 2/3] dt-bindings: mfd: syscon: add aspeed,ast2600-i3c-global compatible
Hi Lee,
Quoted 10 lines · Krzysztof Kozlowski
Quoted 7 lines · Dawid Glazik
Add aspeed,ast2600-i3c-global to the syscon binding compatible lists to document the AST2600 I3C global register syscon node.
Signed-off-by Dawid Glazik <[email protected]>---
Documentation/devicetree/bindings/mfd/syscon.yaml | 2 ++1 file changed, 2 insertions(+)Reviewed-by Krzysztof Kozlowski <[email protected]>
Thanks for applying the AST2700 SoC1 pinctrl binding[1].
Can you pick this one up too? I've applied the corresponding dts patch to the BMC tree, it'd be great to address the warning that's currently produced.
Cheers,
Andrew
PATCH v4 3/3 ARM: dts: aspeed-g6: Add nodes for i3c controllers
In reply to Dawid GlazikAdd the i3c controller devices to the ast2600 g6 common dts. We add all 6 busses to the common g6 definition, but leave disabled through the status property, to be enabled per-platform.
---
v4:
- removed i3c aliases
- renamed i3c-global node name to generic: syscon
v3:
- add i3c aliases
- rebase on top of latest tree and solve conflicts
- as agreed with Jeremy off-list, he said I can take authorship of this going forward
v2:
- use inline bus representation, without the i3c: label
--- arch/arm/boot/dts/aspeed/aspeed-g6.dtsi | 91 +++++++++++++++++++++++++ 1 file changed, 91 insertions(+)
arch/arm/boot/dts/aspeed/aspeed-g6.dtsi +91 -0
@@ -1066,6 +1066,97 @@ i2c15: i2c@800 { }; }; + bus@1e7a0000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1e7a0000 0x8000>; + + i3c_global: syscon@0 { + compatible = "aspeed,ast2600-i3c-global", "syscon"; + reg = <0x0 0x1000>; + resets = <&syscon ASPEED_RESET_I3C_DMA>; + }; + + i3c0: i3c@2000 { + compatible = "aspeed,ast2600-i3c"; + reg = <0x2000 0x1000>; + #address-cells = <3>; + #size-cells = <0>; + clocks = <&syscon ASPEED_CLK_GATE_I3C0CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i3c1_default>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + aspeed,global-regs = <&i3c_global 0>; + status = "disabled"; + }; + + i3c1: i3c@3000 { + compatible = "aspeed,ast2600-i3c"; + reg = <0x3000 0x1000>; + #address-cells = <3>; + #size-cells = <0>; + clocks = <&syscon ASPEED_CLK_GATE_I3C1CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i3c2_default>; + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + aspeed,global-regs = <&i3c_global 1>; + status = "disabled"; + }; + + i3c2: i3c@4000 { + compatible = "aspeed,ast2600-i3c"; + reg = <0x4000 0x1000>; + #address-cells = <3>; + #size-cells = <0>; + clocks = <&syscon ASPEED_CLK_GATE_I3C2CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i3c3_default>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; + aspeed,global-regs = <&i3c_global 2>; + status = "disabled"; + }; + + i3c3: i3c@5000 { + compatible = "aspeed,ast2600-i3c"; + reg = <0x5000 0x1000>; + #address-cells = <3>; + #size-cells = <0>; + clocks = <&syscon ASPEED_CLK_GATE_I3C3CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i3c4_default>; + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + aspeed,global-regs = <&i3c_global 3>; + status = "disabled"; + }; + + i3c4: i3c@6000 { + compatible = "aspeed,ast2600-i3c"; + reg = <0x6000 0x1000>; + #address-cells = <3>; + #size-cells = <0>; + clocks = <&syscon ASPEED_CLK_GATE_I3C4CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i3c5_default>; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; + aspeed,global-regs = <&i3c_global 4>; + status = "disabled"; + }; + + i3c5: i3c@7000 { + compatible = "aspeed,ast2600-i3c"; + reg = <0x7000 0x1000>; + #address-cells = <3>; + #size-cells = <0>; + clocks = <&syscon ASPEED_CLK_GATE_I3C5CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i3c6_default>; + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + aspeed,global-regs = <&i3c_global 5>; + status = "disabled"; + }; + }; + fsim0: fsi@1e79b000 { #interrupt-cells = <1>; compatible = "aspeed,ast2600-fsi-master";
Signature · 1 line
2.43.0
Quoted 20 lines · Dawid Glazik
This series reworks and resubmits AST2600 I3C DTS updates that were originally posted in 2024, but stalled without further upstream progress.[1] The series was rebased onto the current tree and merge conflicts were resolved.
The patches first move I2C controller nodes under the APB simple-bus for layout consistency, then document aspeed,ast2600-i3c-global in the syscon binding, and finally add AST2600 I3C controller nodes in
aspeed-g6.dtsi.Jeremy agreed in a separate email thread that I can continue this series under my authorship.
Dawid Glazik (3):
ARM: dts: aspeed-g6: move i2c controllers directly into apb node
dt-bindings: mfd: syscon: add aspeed,ast2600-i3c-global compatible
ARM: dts: aspeed-g6: Add nodes for i3c controllers
Quoted 6 lines
.../devicetree/bindings/mfd/syscon.yaml | 2 + arch/arm/boot/dts/aspeed/aspeed-g6.dtsi | 543 ++++++++++-------- 2 files changed, 318 insertions(+), 227 deletions(-)base-commit:
6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f
Hi all,
Gentle ping for this series:
https://lore.kernel.org/all/[email protected]/#t
I received Reviewed-by from Krzysztof Kozlowski (thank you). Could I please get feedback/ack from maintainers on the remaining parts, especially ASPEED DTS?
If preferred, I can respin/rebase the series.
Thanks,
Dawid Glazik
Andrew Jeffery
maintainerHi Dawid,
Quoted 30 lines · Dawid Glazik
Quoted 20 lines · Dawid Glazik
This series reworks and resubmits AST2600 I3C DTS updates that were originally posted in 2024, but stalled without further upstream progress.[1] The series was rebased onto the current tree and merge conflicts were resolved.
The patches first move I2C controller nodes under the APB simple-bus for layout consistency, then document aspeed,ast2600-i3c-global in the syscon binding, and finally add AST2600 I3C controller nodes in
aspeed-g6.dtsi.Jeremy agreed in a separate email thread that I can continue this series under my authorship.
Dawid Glazik (3):
ARM: dts: aspeed-g6: move i2c controllers directly into apb node
dt-bindings: mfd: syscon: add aspeed,ast2600-i3c-global compatible
ARM: dts: aspeed-g6: Add nodes for i3c controllersQuoted 6 lines
.../devicetree/bindings/mfd/syscon.yaml | 2 + arch/arm/boot/dts/aspeed/aspeed-g6.dtsi | 543 ++++++++++--------
2 files changed, 318 insertions(+), 227 deletions(-)base-commit:
6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27fHi all,
Quoted 9 lines
Gentle ping for this series:
https://lore.kernel.org/all/[email protected]/#tI received Reviewed-by from Krzysztof Kozlowski (thank you). Could I please get feedback/ack from maintainers on the remaining parts, especially ASPEED DTS?
If preferred, I can respin/rebase the series.
Sorry for the delay.
Given Krzysztof's R-b tag for patch 2 I've applied 3 (along with 1) to the BMC tree. Patch 2 should be picked up by Lee through the MFD tree.
Cheers,
Andrew
Quoted 9 lines · Andrew Jeffery
Sorry for the delay.
Given Krzysztof's R-b tag for patch 2 I've applied 3 (along with 1) to the BMC tree. Patch 2 should be picked up by Lee through the MFD tree.
Cheers,
Andrew
Hi Andrew,
Great news! Thank you.
Dawid