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arm64: dts: imx8mp-var-som-symphony: align DTS with hardware revision

PATCH Superseded Stefano Radaelli 2 participants 17 messages Jun 3

Subsystems (2)
Device tree bindings Arm i.MX and Layerscape

v1 of 5 Superseded Latest is v5 →

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Stefano Radaelli

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#0 lore raw

cover arm64: dts: imx8mp-var-som-symphony: align DTS with hardware revision

This series updates the i.MX8MP VAR-SOM and Symphony device trees to better align them with the current hardware configuration.

It adds the missing board peripherals and completes the related pinctrl, GPIO and bus configuration.

Stefano Radaelli (12):
arm64: dts: imx8mp-var-som-symphony: add input keys
arm64: dts: imx8mp-var-som-symphony: enable USB support
arm64: dts: imx8mp-var-som-symphony: add TPM support
arm64: dts: imx8mp-var-som-symphony: add external RTC
arm64: dts: imx8mp-var-som-symphony: enable header UARTs
arm64: dts: imx8mp-var-som-symphony: enable PCIe
arm64: dts: imx8mp-var-som-symphony: add HDMI support
arm64: dts: imx8mp-var-som-symphony: add capacitive touchscreen
arm64: dts: imx8mp-var-som-symphony: enable ECSPI2
arm64: dts: imx8mp-var-som-symphony: keep RGB_SEL low
arm64: dts: imx8mp-var-som-symphony: enable PWM1
arm64: dts: freescale: imx8mp-var-som: add I2C1 bus recovery GPIOs

 .../dts/freescale/imx8mp-var-som-symphony.dts | 307 +++++++++++++++++-
 .../boot/dts/freescale/imx8mp-var-som.dtsi    |  12 +-
 2 files changed, 317 insertions(+), 2 deletions(-)

base-commit: b3c1d1631f097619f8091f0293e027c4301285d6

Signature · 1 line
2.47.3
author
#1 lore raw

PATCH 1/12 arm64: dts: imx8mp-var-som-symphony: add input keys

Add the Back, Home and Menu keys connected through the GPIO expander on the Symphony carrier board.

Also enable the SNVS power key.

Signed-off-by Stefano Radaelli <[email protected]>
---
 .../dts/freescale/imx8mp-var-som-symphony.dts | 29 +++++++++++++++++++
 1 file changed, 29 insertions(+)
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +29 -0
index 291f65e36865..25f707012f62 100644
@@ -13,6 +13,31 @@ chosen {
 		stdout-path = &uart2;
 	};
 
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		button-back {
+			label = "Back";
+			linux,code = <KEY_BACK>;
+			gpios = <&pca9534 1 GPIO_ACTIVE_LOW>;
+			wakeup-source;
+		};
+
+		button-home {
+			label = "Home";
+			linux,code = <KEY_HOME>;
+			gpios = <&pca9534 2 GPIO_ACTIVE_LOW>;
+			wakeup-source;
+		};
+
+		button-menu {
+			label = "Menu";
+			linux,code = <KEY_MENU>;
+			gpios = <&pca9534 3 GPIO_ACTIVE_LOW>;
+			wakeup-source;
+		};
+	};
+
 	gpio-leds {
 		compatible = "gpio-leds";
 

@@ -72,6 +97,10 @@ usb3-sata-sel-hog {
 	};
 };
 
+&snvs_pwrkey {
+	status = "okay";
+};
+
 /* Console */
 &uart2 {
 	pinctrl-names = "default";
Signature · 1 line
2.47.3
author
#2 lore raw

PATCH 2/12 arm64: dts: imx8mp-var-som-symphony: enable USB support

In reply to Stefano Radaelli

From: Stefano Radaelli <[email protected]>

Enable the USB controllers on the Symphony carrier board.

Add the PTN5150 Type-C controller for USB role switching, enable the USB3 PHYs and controllers, configure the I2C bus used by the Type-C controller, and set the first USB port in OTG mode and the second port in host mode.

Signed-off-by Stefano Radaelli <[email protected]>
---
 .../dts/freescale/imx8mp-var-som-symphony.dts | 80 ++++++++++++++++++-
 1 file changed, 79 insertions(+), 1 deletion(-)
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +79 -1
index 25f707012f62..de1b8b842848 100644
@@ -72,8 +72,11 @@ reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc {
 
 &i2c3 {
 	clock-frequency = <400000>;
-	pinctrl-names = "default";
+	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c3>;
+	pinctrl-1 = <&pinctrl_i2c3_gpio>;
+	scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 	status = "okay";
 
 	/* GPIO expander */

@@ -95,6 +98,22 @@ usb3-sata-sel-hog {
 			line-name = "usb3_sata_sel";
 		};
 	};
+
+	/* USB Type-C Controller */
+	typec@3d {
+		compatible = "nxp,ptn5150";
+		reg = <0x3d>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_ptn5150>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
+
+		port {
+			typec_dr_sw: endpoint {
+				remote-endpoint = <&usb3_drd_sw>;
+			};
+		};
+	};
 };
 
 &snvs_pwrkey {

@@ -108,6 +127,52 @@ &uart2 {
 	status = "okay";
 };
 
+&usb3_0 {
+	status = "okay";
+};
+
+&usb3_1 {
+	status = "okay";
+};
+
+&usb_dwc3_0 {
+	adp-disable;
+	dr_mode = "otg";
+	hnp-disable;
+	snps,dis-u1-entry-quirk;
+	snps,dis-u2-entry-quirk;
+	srp-disable;
+	usb-role-switch;
+	status = "okay";
+
+	port {
+		usb3_drd_sw: endpoint {
+			remote-endpoint = <&typec_dr_sw>;
+		};
+	};
+};
+
+&usb_dwc3_1 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usb3_phy0 {
+	fsl,phy-comp-dis-tune-percent = <115>;
+	fsl,phy-pcs-tx-deemph-3p5db-attenuation-db = <33>;
+	fsl,phy-pcs-tx-swing-full-percent = <100>;
+	fsl,phy-tx-preemp-amp-tune-microamp = <1800>;
+	fsl,phy-tx-vboost-level-microvolt = <1156>;
+	fsl,phy-tx-vref-tune-percent = <122>;
+	status = "okay";
+};
+
+&usb3_phy1 {
+	fsl,phy-tx-preemp-amp-tune-microamp = <1800>;
+	fsl,phy-tx-vref-tune-percent = <116>;
+	status = "okay";
+};
+
 /* SD-card */
 &usdhc2 {
 	pinctrl-names = "default", "state_100mhz", "state_200mhz";

@@ -129,12 +194,25 @@ MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA                                 0x400001c2
 		>;
 	};
 
+	pinctrl_i2c3_gpio: i2c3gpiogrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18				0x1c2
+			MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19				0x1c2
+		>;
+	};
+
 	pinctrl_pca9534: pca9534grp {
 		fsl,pins = <
 			MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15                             0xc0
 		>;
 	};
 
+	pinctrl_ptn5150: ptn5150grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05				0x10
+		>;
+	};
+
 	pinctrl_uart2: uart2grp {
 		fsl,pins = <
 			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX                            0x40
Signature · 1 line
2.47.3
AI review
#3 lore raw

Re: [PATCH v1 02/12] arm64: dts: imx8mp-var-som-symphony: enable USB support

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [Low] Incorrect interrupt polarity configured for the PTN5150 Type-C controller's INTB pin. --

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] Incorrect interrupt polarity configured for the PTN5150 Type-C controller's INTB pin. --

commit 29e658d004cef4b6d7125b61dc6adb4519ddc922
Author: Stefano Radaelli <[email protected]>

arm64: dts: imx8mp-var-som-symphony: enable USB support

This commit enables the USB controllers on the Symphony carrier board. It adds the PTN5150 Type-C controller, configures the I2C bus, and enables the USB3 PHYs and controllers with their respective roles.

Quoted 4 lines
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +0 -0
index 25f707012f62c..de1b8b8428481 100644

[ ... ]

arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts usb3-sata-sel-hog { · line 109

Quoted 13 lines
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +9 -0
@@ -95,6 +98,22 @@ usb3-sata-sel-hog {
 			line-name = "usb3_sata_sel";
 		};
 	};
+
+	/* USB Type-C Controller */
+	typec@3d {
+		compatible = "nxp,ptn5150";
+		reg = <0x3d>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_ptn5150>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;

[Severity: Low]
Does this incorrectly describe the interrupt polarity for the PTN5150?

The PTN5150 INTB interrupt pin is an active-low, open-drain output, which would typically use IRQ_TYPE_LEVEL_LOW or IRQ_TYPE_EDGE_FALLING.

While the extcon-ptn5150 driver currently hardcodes IRQF_TRIGGER_FALLING when requesting the IRQ (masking the issue functionally by overriding the devicetree), specifying IRQ_TYPE_LEVEL_HIGH violates hardware description standards. This mismatch could lead to trigger mismatch warnings during boot or future bugs if the driver is ever updated to use the devicetree specified trigger type.

Quoted 8 lines
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +7 -0
+
+		port {
+			typec_dr_sw: endpoint {
+				remote-endpoint = <&usb3_drd_sw>;
+			};
+		};
+	};
 };

[ ... ]

Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=2
author
#4 lore raw

PATCH 3/12 arm64: dts: imx8mp-var-som-symphony: add TPM support

In reply to Stefano Radaelli

From: Stefano Radaelli <[email protected]>

Add the ST33KTPM2XI2C TPM device on the Symphony carrier board.

Enable the I2C4 bus, add the PCAL6408 GPIO expander used by the TPM and describe the TPM reset line.

Signed-off-by Stefano Radaelli <[email protected]>
---
 .../dts/freescale/imx8mp-var-som-symphony.dts | 39 +++++++++++++++++++
 1 file changed, 39 insertions(+)
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +39 -0
index de1b8b842848..935bc71b6ee1 100644
@@ -116,6 +116,31 @@ typec_dr_sw: endpoint {
 	};
 };
 
+&i2c4 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default", "gpio", "sleep";
+	pinctrl-0 = <&pinctrl_i2c4>;
+	pinctrl-1 = <&pinctrl_i2c4_gpio>;
+	pinctrl-2 = <&pinctrl_i2c4_gpio>;
+	scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	status = "okay";
+
+	pcal6408: gpio@21 {
+		compatible = "nxp,pcal6408";
+		reg = <0x21>;
+		#gpio-cells = <2>;
+		gpio-controller;
+	};
+
+	st33ktpm2xi2c: tpm@2e {
+		compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c";
+		reg = <0x2e>;
+		label = "tpm";
+		reset-gpios = <&pcal6408 4 GPIO_ACTIVE_LOW>;
+	};
+};
+
 &snvs_pwrkey {
 	status = "okay";
 };

@@ -201,6 +226,20 @@ MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19				0x1c2
 		>;
 	};
 
+	pinctrl_i2c4: i2c4grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL					0x400001c2
+			MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA					0x400001c2
+		>;
+	};
+
+	pinctrl_i2c4_gpio: i2c4gpiogrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20				0x1c2
+			MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21				0x1c2
+		>;
+	};
+
 	pinctrl_pca9534: pca9534grp {
 		fsl,pins = <
 			MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15                             0xc0
Signature · 1 line
2.47.3
author
#5 lore raw

PATCH 4/12 arm64: dts: imx8mp-var-som-symphony: add external RTC

In reply to Stefano Radaelli

From: Stefano Radaelli <[email protected]>

Add the DS1337 RTC on the Symphony carrier board and disable the internal SNVS RTC.

Signed-off-by Stefano Radaelli <[email protected]>
---
 .../arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts | 9 +++++++++
 1 file changed, 9 insertions(+)
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +9 -0
index 935bc71b6ee1..8f8c76993fb5 100644
@@ -139,12 +139,21 @@ st33ktpm2xi2c: tpm@2e {
 		label = "tpm";
 		reset-gpios = <&pcal6408 4 GPIO_ACTIVE_LOW>;
 	};
+
+	rtc@68 {
+		compatible = "dallas,ds1337";
+		reg = <0x68>;
+	};
 };
 
 &snvs_pwrkey {
 	status = "okay";
 };
 
+&snvs_rtc {
+	status = "disabled";
+};
+
 /* Console */
 &uart2 {
 	pinctrl-names = "default";
Signature · 1 line
2.47.3
author
#6 lore raw

PATCH 5/12 arm64: dts: imx8mp-var-som-symphony: enable header UARTs

In reply to Stefano Radaelli

From: Stefano Radaelli <[email protected]>

Enable UART1 and UART4 on the Symphony carrier board and add the corresponding pinctrl configurations.

Signed-off-by Stefano Radaelli <[email protected]>
---
 .../dts/freescale/imx8mp-var-som-symphony.dts | 28 +++++++++++++++++++
 1 file changed, 28 insertions(+)
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +28 -0
index 8f8c76993fb5..3dda28be92f8 100644
@@ -154,6 +154,13 @@ &snvs_rtc {
 	status = "disabled";
 };
 
+/* Header UART */
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	status = "okay";
+};
+
 /* Console */
 &uart2 {
 	pinctrl-names = "default";

@@ -161,6 +168,13 @@ &uart2 {
 	status = "okay";
 };
 
+/* Header UART */
+&uart4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart4>;
+	status = "okay";
+};
+
 &usb3_0 {
 	status = "okay";
 };

@@ -261,6 +275,13 @@ MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05				0x10
 		>;
 	};
 
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX				0x40
+			MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX				0x40
+		>;
+	};
+
 	pinctrl_uart2: uart2grp {
 		fsl,pins = <
 			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX                            0x40

@@ -268,6 +289,13 @@ MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX                            0x40
 		>;
 	};
 
+	pinctrl_uart4: uart4grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX				0x40
+			MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX				0x40
+		>;
+	};
+
 	pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
 		fsl,pins = <
 			MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14                             0x1c4
Signature · 1 line
2.47.3
author
#7 lore raw

PATCH 6/12 arm64: dts: imx8mp-var-som-symphony: enable PCIe

In reply to Stefano Radaelli

From: Stefano Radaelli <[email protected]>

Add the PCIe reference clock and enable the PCIe controller and PHY on the Symphony carrier board.

Describe the reset GPIO and configure the PHY to use an external reference clock input.

Signed-off-by Stefano Radaelli <[email protected]>
---
 .../dts/freescale/imx8mp-var-som-symphony.dts  | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +18 -0
index 3dda28be92f8..fe1699649414 100644
@@ -48,6 +48,12 @@ led-0 {
 		};
 	};
 
+	pcie0_refclk: pcie0-refclk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+	};
+
 	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
 		compatible = "regulator-fixed";
 		regulator-name = "VSD_3V3";

@@ -146,6 +152,18 @@ rtc@68 {
 	};
 };
 
+&pcie {
+	reset-gpio = <&pcal6408 1 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+&pcie_phy {
+	clocks = <&pcie0_refclk>;
+	clock-names = "ref";
+	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
+	status = "okay";
+};
+
 &snvs_pwrkey {
 	status = "okay";
 };
Signature · 1 line
2.47.3
AI review
#8 lore raw

Re: [PATCH v1 06/12] arm64: dts: imx8mp-var-som-symphony: enable PCIe

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [High] Timeout and PCIe initialization failure during system resume due to I2C-based PCIe reset GPIO in…

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Timeout and PCIe initialization failure during system resume due to I2C-based PCIe reset GPIO in NOIRQ phase. --

commit 1813e394a2d156f58d0fa0b95aed827b4d4e4bc4
Author: Stefano Radaelli <[email protected]>

arm64: dts: imx8mp-var-som-symphony: enable PCIe

Add the PCIe reference clock and enable the PCIe controller and PHY on the Symphony carrier board.

Quoted 3 lines
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +0 -0

[ ... ]

arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts rtc@68 { · line 156

Quoted 6 lines
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +2 -0
@@ -146,6 +152,18 @@ rtc@68 {
 	};
 };
 
+&pcie {
+	reset-gpio = <&pcal6408 1 GPIO_ACTIVE_LOW>;

[Severity: High]
Does this configuration cause a timeout and PCIe initialization failure during system resume?

The PCIe controller specifies an I2C-based GPIO expander (pcal6408) for its reset-gpio. During system resume, the i.MX PCIe driver executes its hardware initialization in the noirq phase (imx_pcie_resume_noirq() -> dw_pcie_resume_noirq() -> imx_pcie_host_init()), which asserts and deasserts the reset GPIO using gpiod_set_value_cansleep().

During the dpm_resume_noirq phase, local CPU interrupts are enabled but device interrupts remain masked at the interrupt controller (because resume_device_irqs() is called after noirq callbacks). As a result, the I2C controller cannot receive device interrupts.

Furthermore, i2c_in_atomic_xfer_mode() evaluates to false because system_state is SYSTEM_RUNNING and local IRQs are enabled, meaning the I2C core will not fall back to atomic polling mode. The I2C transaction required to toggle the GPIO will therefore wait for an interrupt that is masked, resulting in a prolonged timeout and a failed transfer. This causes the PCIe resume to fail and significantly delays the overall system resume process.

Quoted 2 lines
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +2 -0
+	status = "okay";
+};
Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=6
author
#9 lore raw

PATCH 7/12 arm64: dts: imx8mp-var-som-symphony: add HDMI support

In reply to Stefano Radaelli

From: Stefano Radaelli <[email protected]>

Enable HDMI output on Symphony iMX8MP Carrier Board along with audio support.

Signed-off-by Stefano Radaelli <[email protected]>
---
 .../dts/freescale/imx8mp-var-som-symphony.dts | 47 +++++++++++++++++++
 1 file changed, 47 insertions(+)
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +47 -0
index fe1699649414..6878b89c4db8 100644
@@ -48,6 +48,18 @@ led-0 {
 		};
 	};
 
+	native-hdmi-connector {
+		compatible = "hdmi-connector";
+		label = "HDMI OUT";
+		type = "a";
+
+		port {
+			hdmi_in: endpoint {
+				remote-endpoint = <&hdmi_tx_out>;
+			};
+		};
+	};
+
 	pcie0_refclk: pcie0-refclk {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;

@@ -74,6 +86,41 @@ reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc {
 		states = <3300000 0x0 1800000 0x1>;
 		vin-supply = <&ldo5>;
 	};
+
+	sound-hdmi {
+		compatible = "fsl,imx-audio-hdmi";
+		model = "audio-hdmi";
+		audio-cpu = <&aud2htx>;
+		hdmi-out;
+	};
+};
+
+&aud2htx {
+	status = "okay";
+};
+
+&hdmi_pai {
+	status = "okay";
+};
+
+&hdmi_pvi {
+	status = "okay";
+};
+
+&hdmi_tx {
+	status = "okay";
+
+	ports {
+		port@1 {
+			hdmi_tx_out: endpoint {
+				remote-endpoint = <&hdmi_in>;
+			};
+		};
+	};
+};
+
+&hdmi_tx_phy {
+	status = "okay";
 };
 
 &i2c3 {
Signature · 1 line
2.47.3
AI review
#10 lore raw

Re: [PATCH v1 07/12] arm64: dts: imx8mp-var-som-symphony: add HDMI support

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider: - [High] The `lcdif3` display controller is not enabled, breaking the HDMI video pipeline because it is the…

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] The lcdif3 display controller is not enabled, breaking the HDMI video pipeline because it is the sole video source for the HDMI interface on the i.MX8MP.
- [High] The hdmi_tx node lacks pin multiplexing configuration for the DDC and HPD pins, which breaks EDID reading and Hot Plug Detect. --

commit aea2bfe7fe7a358c3badcef46d4148e23cb37818
Author: Stefano Radaelli <[email protected]>

arm64: dts: imx8mp-var-som-symphony: add HDMI support

Enable HDMI output on Symphony iMX8MP Carrier Board along with audio support.

Quoted 4 lines
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +0 -0
index fe16996494141..6878b89c4db8e 100644

[ ... ]

Quoted 15 lines
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +11 -0
@@ -74,6 +86,41 @@ reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc {
 		states = <3300000 0x0 1800000 0x1>;
 		vin-supply = <&ldo5>;
 	};
+
+	sound-hdmi {
+		compatible = "fsl,imx-audio-hdmi";
+		model = "audio-hdmi";
+		audio-cpu = <&aud2htx>;
+		hdmi-out;
+	};
+};
+
+&aud2htx {
+	status = "okay";

arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { · line 109

Quoted 10 lines
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +10 -0
+};
+
+&hdmi_pai {
+	status = "okay";
+};
+
+&hdmi_pvi {
+	status = "okay";
+};
+

[Severity: High]
Does the lcdif3 display controller also need to be enabled here?

On the i.MX8MP architecture, the HDMI transmitter receives its video stream from the Parallel Video Interface (hdmi_pvi), which is driven exclusively by the lcdif3 display controller.

Since lcdif3 is disabled in the base imx8mp.dtsi, omitting its enablement means the DRM framework will lack a CRTC for the HDMI pipeline, causing video output initialization to fail.

arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { · line 112

Quoted 3 lines
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +3 -0
+&hdmi_tx {
+	status = "okay";
+

[Severity: High]
Does this node need explicit pin multiplexing configuration for the DDC and HPD pins?

Without pinctrl-names and pinctrl-0 properties here, the configuration relies on the bootloader. If the kernel does not configure the internal pull-ups for the I2C DDC bus and route the pins correctly, Hot Plug Detect and EDID reads will fail, preventing the driver from detecting display capabilities.

Quoted 14 lines
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +11 -0
+	ports {
+		port@1 {
+			hdmi_tx_out: endpoint {
+				remote-endpoint = <&hdmi_in>;
+			};
+		};
+	};
+};
+
+&hdmi_tx_phy {
+	status = "okay";
 };
 
 &i2c3 {
Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=7
author
#11 lore raw

PATCH 8/12 arm64: dts: imx8mp-var-som-symphony: add capacitive touchscreen

In reply to Stefano Radaelli

From: Stefano Radaelli <[email protected]>

Add the FT5206 capacitive touchscreen controller on the Symphony carrier board.
Describe the interrupt pin and touchscreen geometry.

Signed-off-by Stefano Radaelli <[email protected]>
---
 .../dts/freescale/imx8mp-var-som-symphony.dts | 21 +++++++++++++++++++
 1 file changed, 21 insertions(+)
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +21 -0
index 6878b89c4db8..9622f77f8f13 100644
@@ -193,6 +193,21 @@ st33ktpm2xi2c: tpm@2e {
 		reset-gpios = <&pcal6408 4 GPIO_ACTIVE_LOW>;
 	};
 
+	/* Capacitive touch controller */
+	ft5x06_ts: touchscreen@38 {
+		compatible = "edt,edt-ft5206";
+		reg = <0x38>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_captouch>;
+		interrupt-parent = <&gpio5>;
+		interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
+		touchscreen-size-x = <800>;
+		touchscreen-size-y = <480>;
+		touchscreen-inverted-x;
+		touchscreen-inverted-y;
+		wakeup-source;
+	};
+
 	rtc@68 {
 		compatible = "dallas,ds1337";
 		reg = <0x68>;

@@ -300,6 +315,12 @@ &usdhc2 {
 };
 
 &iomuxc {
+	pinctrl_captouch: captouchgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03				0x16
+		>;
+	};
+
 	pinctrl_i2c3: i2c3grp {
 		fsl,pins = <
 			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL                                 0x400001c2
Signature · 1 line
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author
#12 lore raw

PATCH 9/12 arm64: dts: imx8mp-var-som-symphony: enable ECSPI2

In reply to Stefano Radaelli

From: Stefano Radaelli <[email protected]>

Enable the ECSPI2 bus on the Symphony carrier board and add the pinctrl configuration for the SPI signals and chip select GPIO.

Signed-off-by Stefano Radaelli <[email protected]>
---
 .../dts/freescale/imx8mp-var-som-symphony.dts    | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +16 -0
index 9622f77f8f13..df4409af26a2 100644
@@ -99,6 +99,13 @@ &aud2htx {
 	status = "okay";
 };
 
+&ecspi2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi2>;
+	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
 &hdmi_pai {
 	status = "okay";
 };

@@ -321,6 +328,15 @@ MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03				0x16
 		>;
 	};
 
+	pinctrl_ecspi2: ecspi2grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK				0x12
+			MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI				0x12
+			MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO				0x12
+			MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13				0x12
+		>;
+	};
+
 	pinctrl_i2c3: i2c3grp {
 		fsl,pins = <
 			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL                                 0x400001c2
Signature · 1 line
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author
#13 lore raw

PATCH 10/12 arm64: dts: imx8mp-var-som-symphony: keep RGB_SEL low

In reply to Stefano Radaelli

From: Stefano Radaelli <[email protected]>

Keep the RGB_SEL line driven low on the Symphony carrier board.

This avoids leaving the line floating and ensures the board remains in the expected display configuration.

Signed-off-by Stefano Radaelli <[email protected]>
---
 arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts | 8 ++++++++
 1 file changed, 8 insertions(+)
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +8 -0
index df4409af26a2..d796c32f50cc 100644
@@ -191,6 +191,14 @@ pcal6408: gpio@21 {
 		reg = <0x21>;
 		#gpio-cells = <2>;
 		gpio-controller;
+
+		/* RGB_SEL */
+		lvds-brg-enable-hog {
+			gpio-hog;
+			gpios = <7 GPIO_ACTIVE_HIGH>;
+			output-low;
+			line-name = "rgb_sel";
+		};
 	};
 
 	st33ktpm2xi2c: tpm@2e {
Signature · 1 line
2.47.3
AI review
#14 lore raw

Re: [PATCH v1 10/12] arm64: dts: imx8mp-var-som-symphony: keep RGB_SEL low

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [Low] The gpio-hog DT node is named 'lvds-brg-enable-hog' while the line-name and comments refer to…

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The gpio-hog DT node is named 'lvds-brg-enable-hog' while the line-name and comments refer to 'rgb_sel'. This mismatch creates confusion regarding the hardware's actual configuration and may be a copy-paste error. --

commit 1f0ff0206f69fa2f47bd286b774f7b26db9168ed
Author: Stefano Radaelli <[email protected]>

arm64: dts: imx8mp-var-som-symphony: keep RGB_SEL low

This commit drives the RGB_SEL line low on the Symphony carrier board. It ensures the board remains in the expected display configuration rather than leaving the line floating.

arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts pcal6408: gpio@21 { · line 196

Quoted 11 lines
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +3 -0
index df4409af26a26..d796c32f50cc6 100644
@@ -191,6 +191,14 @@ pcal6408: gpio@21 {
 		reg = <0x21>;
 		#gpio-cells = <2>;
 		gpio-controller;
+
+		/* RGB_SEL */
+		lvds-brg-enable-hog {

[Severity: Low]
This isn't a bug, but is the node name lvds-brg-enable-hog intentional here?

The comment and line-name both refer to rgb_sel. Naming the node lvds-brg-enable-hog creates a mismatch that looks like it might be a leftover from a copy-paste.

Quoted 6 lines
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +5 -0
+			gpio-hog;
+			gpios = <7 GPIO_ACTIVE_HIGH>;
+			output-low;
+			line-name = "rgb_sel";
+		};
 	};
Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=10
author
#15 lore raw

PATCH 11/12 arm64: dts: imx8mp-var-som-symphony: enable PWM1

In reply to Stefano Radaelli

From: Stefano Radaelli <[email protected]>

Enable PWM1 on the Symphony carrier board and add the corresponding pinctrl configuration.

Signed-off-by Stefano Radaelli <[email protected]>
---
 .../boot/dts/freescale/imx8mp-var-som-symphony.dts   | 12 ++++++++++++
 1 file changed, 12 insertions(+)
arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +12 -0
index d796c32f50cc..06baa19d79c8 100644
@@ -241,6 +241,12 @@ &pcie_phy {
 	status = "okay";
 };
 
+&pwm1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm1>;
+	status = "okay";
+};
+
 &snvs_pwrkey {
 	status = "okay";
 };

@@ -385,6 +391,12 @@ MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05				0x10
 		>;
 	};
 
+	pinctrl_pwm1: pwm1grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT				0x116
+		>;
+	};
+
 	pinctrl_uart1: uart1grp {
 		fsl,pins = <
 			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX				0x40
Signature · 1 line
2.47.3
author
#16 lore raw

PATCH 12/12 arm64: dts: freescale: imx8mp-var-som: add I2C1 bus recovery GPIOs

In reply to Stefano Radaelli

From: Stefano Radaelli <[email protected]>

Add the GPIO pinctrl state and GPIO descriptors required for I2C1 bus recovery on the VAR-SOM-MX8M-PLUS.

This allows the I2C controller to recover the bus if SDA or SCL are held low by a device.

Signed-off-by Stefano Radaelli <[email protected]>
---
 arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)
arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi +11 -1
index 49467b48d0b0..61786eee0e82 100644
@@ -180,8 +180,11 @@ led@1 {
 
 &i2c1 {
 	clock-frequency = <400000>;
-	pinctrl-names = "default";
+	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c1>;
+	pinctrl-1 = <&pinctrl_i2c1_gpio>;
+	scl-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio2 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 	status = "okay";
 
 	pmic@25 {

@@ -415,6 +418,13 @@ MX8MP_IOMUXC_SD1_DATA5__I2C1_SDA				0x400001c2
 		>;
 	};
 
+	pinctrl_i2c1_gpio: i2c1gpiogrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06				0x1c2
+			MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07				0x1c2
+		>;
+	};
+
 	pinctrl_pmic: pmicgrp {
 		fsl,pins = <
 			MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04				0x1c0
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