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Add support for Variscite DART-MX8M-MINI and Sonata board

PATCH Superseded Stefano Radaelli 3 participants 8 messages Jun 27 – Jul 13

Subsystems (2)
Device tree bindings Arm i.MX and Layerscape

v2 of 3 Superseded Latest is v3 →

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Stefano Radaelli

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#0 lore raw

v2 cover Add support for Variscite DART-MX8M-MINI and Sonata board

This patch series adds support for the Variscite DART-MX8M-MINI system on module and the Sonata carrier board.

The series includes:
- SOM device tree with on-module peripherals
- Sonata carrier board device tree with board-specific features

The implementation follows the standard SOM + carrier board pattern where the SOM dtsi contains only peripherals mounted on the module, while carrier-specific interfaces are enabled in the board dts.

v1->v2:
- Remove HDMI from commit message
- Fixed eth regulator

Stefano Radaelli (3):
dt-bindings: arm: fsl: add Variscite DART-MX8M-MINI Boards
arm64: dts: freescale: Add support for Variscite DART-MX8M-MINI
arm64: dts: imx8mm-var-dart: Add support for Variscite Sonata board

 .../devicetree/bindings/arm/fsl.yaml          |   6 +
 arch/arm64/boot/dts/freescale/Makefile        |   1 +
 .../dts/freescale/imx8mm-var-dart-sonata.dts  | 517 ++++++++++++++++
 .../boot/dts/freescale/imx8mm-var-dart.dtsi   | 558 ++++++++++++++++++
 4 files changed, 1082 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-var-dart-sonata.dts
 create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi

base-commit: 23a7098c710673ce8f245af317903ae46325a694

Signature · 1 line
2.47.3
author
#1 lore raw

PATCH v2 1/3 dt-bindings: arm: fsl: add Variscite DART-MX8M-MINI Boards

From: Stefano Radaelli <[email protected]>

Add DT compatible strings for Variscite DART-MX8MM SoM and Variscite development carrier Board.

Acked-by Krzysztof Kozlowski <[email protected]>
Signed-off-by Stefano Radaelli <[email protected]>

---
v1->v2:
-

 Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++
 1 file changed, 6 insertions(+)
Documentation/devicetree/bindings/arm/fsl.yaml +6 -0
index 86876311ec59..c942d3d06469 100644
@@ -1064,6 +1064,12 @@ properties:
           - const: solidrun,imx8mm-sr-som
           - const: fsl,imx8mm
 
+      - description: Variscite DART-MX8MM based boards
+        items:
+          - const: variscite,var-dart-mx8mm-sonata # Variscite DART-MX8MM on Sonata Development Board
+          - const: variscite,var-dart-mx8mm # Variscite DART-MX8M-MINI SOM
+          - const: fsl,imx8mm
+
       - description: Variscite VAR-SOM-MX8MM based boards
         items:
           - const: variscite,var-som-mx8mm-symphony
Signature · 1 line
2.47.3
author
#2 lore raw

PATCH v2 2/3 arm64: dts: freescale: Add support for Variscite DART-MX8M-MINI

In reply to Stefano Radaelli

From: Stefano Radaelli <[email protected]>

Add device tree support for the Variscite DART-MX8MM system on module. This SOM is designed to be used with various carrier boards.

The module includes:
- NXP i.MX8M Mini MPU processor
- Up to 4GB of LPDDR4 memory
- Up to 128GB of eMMC storage memory
- Integrated 10/100/1000 Mbps Ethernet Transceiver
- Codec audio WM8904
- WIFI6 dual-band 802.11ax/ac/a/b/g/n with optional 802.15.4 and Bluetooth

Only SOM-specific peripherals are enabled by default. Carrier board specific interfaces are left disabled to be enabled in the respective carrier board device trees.

Link https://variscite.com/system-on-module-som/i-mx-8/i-mx-8m-mini/dart-mx8m-mini/
Signed-off-by Stefano Radaelli <[email protected]>

---
v1->v2:
- Fixed eth regulator

 .../boot/dts/freescale/imx8mm-var-dart.dtsi   | 558 ++++++++++++++++++
 1 file changed, 558 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi
arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi new file +558 -0
new file mode 100644
index 000000000000..2324063f8fd9
@@ -0,0 +1,558 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Common dtsi for Variscite DART-MX8M-MINI
+ *
+ * Link: https://variscite.com/system-on-module-som/i-mx-8/i-mx-8m-mini/dart-mx8m-mini/
+ *
+ * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/
+ *
+ */
+
+/dts-v1/;
+
+#include "imx8mm.dtsi"
+
+/ {
+	model = "Variscite DART-MX8M-MINI Module";
+	compatible = "variscite,var-dart-mx8mm", "fsl,imx8mm";
+
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0x0 0x40000000 0 0x80000000>;
+	};
+
+	reg_audio_supply: regulator-3p3v {
+		compatible = "regulator-fixed";
+		regulator-name = "wm8904-supply";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+	};
+
+	reg_eth_phy: regulator-eth-phy {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_reg_eth_phy>;
+		regulator-name = "eth_phy_pwr";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-enable-ramp-delay = <20000>;
+		gpio = <&gpio1 7 GPIO_ACTIVE_LOW>;
+	};
+
+	reg_phy_vddio: regulator-phy-vddio {
+		compatible = "regulator-fixed";
+		regulator-name = "vddio-1v8";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+
+	sound-wm8904 {
+		compatible = "simple-audio-card";
+		simple-audio-card,bitclock-master = <&codec_dai>;
+		simple-audio-card,format = "i2s";
+		simple-audio-card,frame-master = <&codec_dai>;
+		simple-audio-card,mclk-fs = <256>;
+		simple-audio-card,name = "wm8904-audio";
+		simple-audio-card,routing =
+			"Headphone Jack", "HPOUTL",
+			"Headphone Jack", "HPOUTR",
+			"IN2L", "Line In Jack",
+			"IN2R", "Line In Jack",
+			"IN1L", "Microphone Jack",
+			"IN1R", "Microphone Jack";
+		simple-audio-card,widgets =
+			"Microphone", "Microphone Jack",
+			"Headphone", "Headphone Jack",
+			"Line", "Line In Jack";
+
+		codec_dai: simple-audio-card,codec {
+			sound-dai = <&wm8904>;
+		};
+
+		simple-audio-card,cpu {
+			sound-dai = <&sai3>;
+		};
+	};
+
+	wifi_pwrseq: wifi-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		post-power-on-delay-ms = <100>;
+		power-off-delay-us = <10000>;
+		reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>, /* WIFI_RESET */
+			      <&gpio2 20 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */
+	};
+};
+
+&A53_0 {
+	cpu-supply = <&buck2_reg>;
+};
+
+&A53_1 {
+	cpu-supply = <&buck2_reg>;
+};
+
+&A53_2 {
+	cpu-supply = <&buck2_reg>;
+};
+
+&A53_3 {
+	cpu-supply = <&buck2_reg>;
+};
+
+&fec1 {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&pinctrl_fec1>;
+	pinctrl-1 = <&pinctrl_fec1_sleep>;
+	/*
+	 * The required RGMII TX and RX 2ns delays are implemented directly
+	 * in hardware via passive delay elements on the SOM PCB.
+	 * No delay configuration is needed in software via PHY driver.
+	 */
+	phy-mode = "rgmii";
+	phy-handle = <&ethphy0>;
+	phy-supply = <&reg_eth_phy>;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+			reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <10000>;
+			reset-deassert-us = <100000>;
+			vddio-supply = <&reg_phy_vddio>;
+		};
+	};
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	pinctrl-1 = <&pinctrl_i2c1_gpio>;
+	scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	status = "okay";
+
+	pmic@4b {
+		compatible = "rohm,bd71847";
+		reg = <0x4b>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_pmic>;
+		interrupt-parent = <&gpio2>;
+		interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
+		rohm,reset-snvs-powered;
+
+		regulators {
+			buck1_reg: BUCK1 {
+				regulator-name = "buck1";
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1300000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <1250>;
+			};
+
+			buck2_reg: BUCK2 {
+				regulator-name = "buck2";
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1300000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <1250>;
+				rohm,dvs-run-voltage = <1000000>;
+				rohm,dvs-idle-voltage = <900000>;
+			};
+
+			buck3_reg: BUCK3 {
+				// BUCK5 in datasheet
+				regulator-name = "buck3";
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck4_reg: BUCK4 {
+				// BUCK6 in datasheet
+				regulator-name = "buck4";
+				regulator-min-microvolt = <2600000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck5_reg: BUCK5 {
+				// BUCK7 in datasheet
+				regulator-name = "buck5";
+				regulator-min-microvolt = <1605000>;
+				regulator-max-microvolt = <1995000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck6_reg: BUCK6 {
+				// BUCK8 in datasheet
+				regulator-name = "buck6";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo1_reg: LDO1 {
+				regulator-name = "ldo1";
+				regulator-min-microvolt = <1600000>;
+				regulator-max-microvolt = <1900000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo2_reg: LDO2 {
+				regulator-name = "ldo2";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <900000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo3_reg: LDO3 {
+				regulator-name = "ldo3";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo4_reg: LDO4 {
+				regulator-name = "ldo4";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+			};
+
+			ldo5_reg: LDO5 {
+				regulator-name = "ldo5";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-always-on;
+			};
+
+			ldo6_reg: LDO6 {
+				regulator-name = "ldo6";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+&i2c3 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	pinctrl-1 = <&pinctrl_i2c3_gpio>;
+	scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	status = "okay";
+
+	wm8904: audio-codec@1a {
+		compatible = "wlf,wm8904";
+		reg = <0x1a>;
+		#sound-dai-cells = <0>;
+		clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
+		clock-names = "mclk";
+		AVDD-supply = <&ldo5_reg>;
+		CPVDD-supply = <&ldo5_reg>;
+		DBVDD-supply = <&reg_audio_supply>;
+		DCVDD-supply = <&ldo5_reg>;
+		MICVDD-supply = <&ldo5_reg>;
+		wlf,drc-cfg-names = "default", "peaklimiter", "tradition",
+				    "soft", "music";
+		/*
+		 * Config registers per name, respectively:
+		 * KNEE_IP = 0,   KNEE_OP = 0,     HI_COMP = 1,   LO_COMP = 1
+		 * KNEE_IP = -24, KNEE_OP = -6,    HI_COMP = 1/4, LO_COMP = 1
+		 * KNEE_IP = -42, KNEE_OP = -3,    HI_COMP = 0,   LO_COMP = 1
+		 * KNEE_IP = -45, KNEE_OP = -9,    HI_COMP = 1/8, LO_COMP = 1
+		 * KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1
+		 */
+		wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>,
+				   /bits/ 16 <0x04af 0x324b 0x0010 0x0408>,
+				   /bits/ 16 <0x04af 0x324b 0x0028 0x0704>,
+				   /bits/ 16 <0x04af 0x324b 0x0018 0x078c>,
+				   /bits/ 16 <0x04af 0x324b 0x0010 0x050e>;
+		/* GPIO1 = DMIC_CLK, don't touch others */
+		wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>;
+	};
+};
+
+&mu {
+	status = "okay";
+};
+
+&sai3 {
+	#sound-dai-cells = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sai3>;
+	assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
+	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
+	assigned-clock-rates = <1536000>;
+	fsl,sai-mclk-direction-output;
+	status = "okay";
+};
+
+/* BT module */
+&uart4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_bt>;
+	assigned-clocks = <&clk IMX8MM_CLK_UART4>;
+	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
+	uart-has-rtscts;
+	status = "okay";
+
+	bluetooth_iw61x: bluetooth {
+		compatible = "nxp,88w8987-bt";
+	};
+};
+
+/* WIFI */
+&usdhc1 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wifi>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wifi>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wifi>;
+	bus-width = <4>;
+	keep-power-in-suspend;
+	mmc-pwrseq = <&wifi_pwrseq>;
+	non-removable;
+	status = "okay";
+};
+
+/* eMMC */
+&usdhc3 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+&wdog1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,ext-reset-output;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl_bt: btgrp {
+		fsl,pins = <
+			MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6		0xc1
+			MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5		0xc1
+		>;
+	};
+
+	pinctrl_fec1: fec1grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3
+			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
+			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
+			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
+			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
+			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
+			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
+			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
+			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
+			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
+			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
+			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
+			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
+			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
+			MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x19
+		>;
+	};
+
+	pinctrl_fec1_sleep: fec1sleepgrp {
+		fsl,pins = <
+			MX8MM_IOMUXC_ENET_MDC_GPIO1_IO16		0x120
+			MX8MM_IOMUXC_ENET_MDIO_GPIO1_IO17		0x120
+			MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18		0x120
+			MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19		0x120
+			MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20		0x120
+			MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21		0x120
+			MX8MM_IOMUXC_ENET_RD3_GPIO1_IO29		0x120
+			MX8MM_IOMUXC_ENET_RD2_GPIO1_IO28		0x120
+			MX8MM_IOMUXC_ENET_RD1_GPIO1_IO27		0x120
+			MX8MM_IOMUXC_ENET_RD0_GPIO1_IO26		0x120
+			MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23		0x120
+			MX8MM_IOMUXC_ENET_RXC_GPIO1_IO25		0x120
+			MX8MM_IOMUXC_ENET_RX_CTL_GPIO1_IO24		0x120
+			MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22		0x120
+			MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x100
+		>;
+	};
+
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL			0x400001c3
+			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA			0x400001c3
+		>;
+	};
+
+	pinctrl_i2c1_gpio: i2c1-gpiogrp {
+		fsl,pins = <
+			MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14		0x400001c3
+			MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15		0x400001c3
+		>;
+	};
+
+	pinctrl_i2c3: i2c3grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL			0x400001c3
+			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA			0x400001c3
+		>;
+	};
+
+	pinctrl_i2c3_gpio: i2c3-gpiogrp {
+		fsl,pins = <
+			MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18		0x400001c3
+			MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19		0x400001c3
+		>;
+	};
+
+	pinctrl_pmic: pmicgrp {
+		fsl,pins = <
+			MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8		0x140
+		>;
+	};
+
+	pinctrl_reg_eth_phy: regeth-phygrp {
+		fsl,pins = <
+			MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7		0x41
+		>;
+	};
+
+	pinctrl_sai3: sai3grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC		0xd6
+			MX8MM_IOMUXC_SAI3_RXC_SAI3_RX_BCLK		0xd6
+			MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0		0xd6
+			MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC		0xd6
+			MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK		0xd6
+			MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0		0xd6
+			MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK		0xd6
+		>;
+	};
+
+	pinctrl_uart4: uart4grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX		0x140
+			MX8MM_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX		0x140
+			MX8MM_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B		0x140
+			MX8MM_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B	0x140
+		>;
+	};
+
+	pinctrl_usdhc1: usdhc1grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK			0x190
+			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD			0x1d0
+			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0		0x1d0
+			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1		0x1d0
+			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2		0x1d0
+			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3		0x1d0
+		>;
+	};
+
+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+		fsl,pins = <
+			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK			0x194
+			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD			0x1d4
+			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0		0x1d4
+			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1		0x1d4
+			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2		0x1d4
+			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3		0x1d4
+		>;
+	};
+
+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+		fsl,pins = <
+			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK			0x196
+			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD			0x1d6
+			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0		0x1d6
+			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1		0x1d6
+			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2		0x1d6
+			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3		0x1d6
+		>;
+	};
+
+	pinctrl_usdhc3: usdhc3grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x190
+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d0
+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d0
+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d0
+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d0
+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d0
+			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d0
+			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d0
+			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d0
+			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d0
+			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x190
+		>;
+	};
+
+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
+		fsl,pins = <
+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x194
+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d4
+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d4
+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d4
+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d4
+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d4
+			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d4
+			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d4
+			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d4
+			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d4
+			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x194
+		>;
+	};
+
+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
+		fsl,pins = <
+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x196
+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d6
+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d6
+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d6
+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d6
+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d6
+			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d6
+			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d6
+			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d6
+			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d6
+			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x196
+		>;
+	};
+
+	pinctrl_wdog: wdoggrp {
+		fsl,pins = <
+			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0xc6
+		>;
+	};
+
+	pinctrl_wifi: wifigrp {
+		fsl,pins = <
+			MX8MM_IOMUXC_SD2_WP_GPIO2_IO20			0x140
+			MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10		0xc1
+		>;
+	};
+};
Signature · 1 line
2.47.3
AI review
#3 lore raw

Re: [PATCH v2 2/3] arm64: dts: freescale: Add support for Variscite DART-MX8M-MINI

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider: - [Medium] Simultaneous assertion/deassertion of Wi-Fi power enable and reset pins in `wifi_pwrseq`…

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [Medium] Simultaneous assertion/deassertion of Wi-Fi power enable and reset pins in wifi_pwrseq, violating typical SDIO Wi-Fi power sequencing requirements.
- [Medium] Bluetooth GPIOs configured in pinctrl_bt are not assigned to or claimed by the Bluetooth device node, leaving them as unmanaged floating inputs.
- [Medium] WM8904 codec configuration contains contradictory settings blindly copied from binding examples, likely breaking microphone functionality. --

commit 4642338fef518c3eba73b9681507dd2dd37ee845
Author: Stefano Radaelli <[email protected]>

arm64: dts: freescale: Add support for Variscite DART-MX8M-MINI

Add device tree support for the Variscite DART-MX8MM system on module. This SOM is designed to be used with various carrier boards. Only SOM-specific peripherals are enabled by default.

Link https://variscite.com/system-on-module-som/i-mx-8/i-mx-8m-mini/dart-mx8m-mini/
Quoted 4 lines
arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi new file +0 -0
new file mode 100644

[ ... ]

Quoted 4 lines
arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi new file +4 -0
+	sound-wm8904 {
+		compatible = "simple-audio-card";
+		simple-audio-card,bitclock-master = <&codec_dai>;
+		simple-audio-card,format = "i2s";

arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi line 63

Quoted 10 lines
arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi new file +10 -0
+		simple-audio-card,frame-master = <&codec_dai>;
+		simple-audio-card,mclk-fs = <256>;
+		simple-audio-card,name = "wm8904-audio";
+		simple-audio-card,routing =
+			"Headphone Jack", "HPOUTL",
+			"Headphone Jack", "HPOUTR",
+			"IN2L", "Line In Jack",
+			"IN2R", "Line In Jack",
+			"IN1L", "Microphone Jack",
+			"IN1R", "Microphone Jack";

[Severity: Medium]
Is this analog microphone routing missing a connection to MICBIAS?

The simple-audio-card,routing property routes the Microphone Jack to the codec's analog inputs (IN1L/IN1R), but without a connection to the codec's MICBIAS pin, the analog microphone will likely not receive the required bias voltage to function.

Quoted 4 lines
arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi new file +4 -0
+		simple-audio-card,widgets =
+			"Microphone", "Microphone Jack",
+			"Headphone", "Headphone Jack",
+			"Line", "Line In Jack";

[ ... ]

arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi line 84

Quoted 7 lines
arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi new file +7 -0
+	wifi_pwrseq: wifi-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		post-power-on-delay-ms = <100>;
+		power-off-delay-us = <10000>;
+		reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>, /* WIFI_RESET */
+			      <&gpio2 20 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */
+	};

[Severity: Medium]
Does grouping both the power enable and reset pins in this single reset-gpios array violate SDIO Wi-Fi power sequencing requirements?

The mmc-pwrseq-simple driver toggles all GPIOs in the reset-gpios array simultaneously. During power-on, the Wi-Fi chip's power enable and reset lines will be driven high at the exact same moment.

Standard Wi-Fi power sequencing typically requires the power supply to be fully ramped and stable before the reset line is released.

[ ... ]

Quoted 12 lines

+&i2c3 {

arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi new file +11 -0
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	pinctrl-1 = <&pinctrl_i2c3_gpio>;
+	scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	status = "okay";
+
+	wm8904: audio-codec@1a {
+		compatible = "wlf,wm8904";
+		reg = <0x1a>;

[ ... ]

arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi line 294

Quoted 4 lines
arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi new file +4 -0
+		/* GPIO1 = DMIC_CLK, don't touch others */
+		wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>;
+	};
+};

[Severity: Medium]
Does this digital microphone clock configuration contradict the analog audio routing defined above?

Configuring GPIO1 as a digital microphone clock appears to be a direct copy from the wlf,wm8904 binding example, but it contradicts the analog routing for the Microphone Jack to IN1L/IN1R.

This might expose unintended side-effects by driving a digital clock out of GPIO1 when it's not needed for an analog microphone setup.

[ ... ]

arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi line 323

Quoted 13 lines
arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi new file +13 -0
+/* BT module */
+&uart4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_bt>;
+	assigned-clocks = <&clk IMX8MM_CLK_UART4>;
+	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
+	uart-has-rtscts;
+	status = "okay";
+
+	bluetooth_iw61x: bluetooth {
+		compatible = "nxp,88w8987-bt";
+	};
+};

[Severity: Medium]
Are the Bluetooth GPIOs defined in pinctrl_bt missing their assignments here?

The pinctrl_bt group defines GPIO2_IO6 and GPIO5_IO5 with floating pad configurations (0xc1), and the parent uart4 node applies them. However, because this bluetooth node doesn't map them to expected driver properties (such as device-wakeup-gpios or host-wakeup-gpios), they are left as unmanaged floating inputs.

If one of these acts as an enable or reset pin, floating inputs can cause erratic behavior due to voltage drift.

arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi line 336

Quoted 12 lines
arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi new file +12 -0
+/* WIFI */
+&usdhc1 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wifi>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wifi>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wifi>;
+	bus-width = <4>;
+	keep-power-in-suspend;
+	mmc-pwrseq = <&wifi_pwrseq>;
+	non-removable;
+	status = "okay";
+};

[Severity: Medium]
Should this node include a vmmc-supply linking to a regulator for the Wi-Fi power enable?

Modeling WIFI_PWR_EN as a regulator-fixed assigned to vmmc-supply in this usdhc1 node, while leaving only WIFI_RESET in the mmc-pwrseq-simple node, would ensure the power sequencing is handled correctly.

Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=2
#4 lore raw

Re: [PATCH v2 2/3] arm64: dts: freescale: Add support for Variscite DART-MX8M-MINI

Quoted 99 lines · On Sat, Jun 27, 2026 at 03:00:42PM +0000, [email protected] wrote:

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [Medium] Simultaneous assertion/deassertion of Wi-Fi power enable and reset pins in wifi_pwrseq, violating typical SDIO Wi-Fi power sequencing requirements.
- [Medium] Bluetooth GPIOs configured in pinctrl_bt are not assigned to or claimed by the Bluetooth device node, leaving them as unmanaged floating inputs.
- [Medium] WM8904 codec configuration contains contradictory settings blindly copied from binding examples, likely breaking microphone functionality. --

commit 4642338fef518c3eba73b9681507dd2dd37ee845
Author: Stefano Radaelli <[email protected]>

arm64: dts: freescale: Add support for Variscite DART-MX8M-MINI

Add device tree support for the Variscite DART-MX8MM system on module. This SOM is designed to be used with various carrier boards. Only SOM-specific peripherals are enabled by default.

Link https://variscite.com/system-on-module-som/i-mx-8/i-mx-8m-mini/dart-mx8m-mini/
Quoted 4 lines
arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi new file +0 -0
new file mode 100644

[ ... ]

Quoted 4 lines
arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi new file +4 -0
+	sound-wm8904 {
+		compatible = "simple-audio-card";
+		simple-audio-card,bitclock-master = <&codec_dai>;
+		simple-audio-card,format = "i2s";

arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi line 63

Quoted 10 lines
arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi new file +10 -0
+		simple-audio-card,frame-master = <&codec_dai>;
+		simple-audio-card,mclk-fs = <256>;
+		simple-audio-card,name = "wm8904-audio";
+		simple-audio-card,routing =
+			"Headphone Jack", "HPOUTL",
+			"Headphone Jack", "HPOUTR",
+			"IN2L", "Line In Jack",
+			"IN2R", "Line In Jack",
+			"IN1L", "Microphone Jack",
+			"IN1R", "Microphone Jack";

[Severity: Medium]
Is this analog microphone routing missing a connection to MICBIAS?

The simple-audio-card,routing property routes the Microphone Jack to the codec's analog inputs (IN1L/IN1R), but without a connection to the codec's MICBIAS pin, the analog microphone will likely not receive the required bias voltage to function.

Quoted 4 lines
arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi new file +4 -0
+		simple-audio-card,widgets =
+			"Microphone", "Microphone Jack",
+			"Headphone", "Headphone Jack",
+			"Line", "Line In Jack";

[ ... ]

arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi line 84

Quoted 7 lines
arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi new file +7 -0
+	wifi_pwrseq: wifi-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		post-power-on-delay-ms = <100>;
+		power-off-delay-us = <10000>;
+		reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>, /* WIFI_RESET */
+			      <&gpio2 20 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */
+	};

[Severity: Medium]
Does grouping both the power enable and reset pins in this single reset-gpios array violate SDIO Wi-Fi power sequencing requirements?

The mmc-pwrseq-simple driver toggles all GPIOs in the reset-gpios array simultaneously. During power-on, the Wi-Fi chip's power enable and reset lines will be driven high at the exact same moment.

Standard Wi-Fi power sequencing typically requires the power supply to be fully ramped and stable before the reset line is released.

[ ... ]

Quoted 12 lines

+&i2c3 {

arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi new file +11 -0
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	pinctrl-1 = <&pinctrl_i2c3_gpio>;
+	scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	status = "okay";
+
+	wm8904: audio-codec@1a {
+		compatible = "wlf,wm8904";
+		reg = <0x1a>;

[ ... ]

arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi line 294

Quoted 4 lines
arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi new file +4 -0
+		/* GPIO1 = DMIC_CLK, don't touch others */
+		wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>;
+	};
+};

[Severity: Medium]
Does this digital microphone clock configuration contradict the analog audio routing defined above?

Quoted 6 lines

Configuring GPIO1 as a digital microphone clock appears to be a direct copy from the wlf,wm8904 binding example, but it contradicts the analog routing for the Microphone Jack to IN1L/IN1R.

This might expose unintended side-effects by driving a digital clock out of GPIO1 when it's not needed for an analog microphone setup.

Please check it?

Quoted 20 lines

[ ... ]

arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi line 323

Quoted 13 lines
arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi new file +13 -0
+/* BT module */
+&uart4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_bt>;
+	assigned-clocks = <&clk IMX8MM_CLK_UART4>;
+	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
+	uart-has-rtscts;
+	status = "okay";
+
+	bluetooth_iw61x: bluetooth {
+		compatible = "nxp,88w8987-bt";
+	};
+};

[Severity: Medium]
Are the Bluetooth GPIOs defined in pinctrl_bt missing their assignments here?

Quoted 8 lines

The pinctrl_bt group defines GPIO2_IO6 and GPIO5_IO5 with floating pad configurations (0xc1), and the parent uart4 node applies them. However, because this bluetooth node doesn't map them to expected driver properties (such as device-wakeup-gpios or host-wakeup-gpios), they are left as unmanaged floating inputs.

If one of these acts as an enable or reset pin, floating inputs can cause erratic behavior due to voltage drift.

Please double check this also

Quoted 18 lines

arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi line 336

Quoted 13 lines
arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi new file +12 -0
+/* WIFI */
+&usdhc1 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wifi>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wifi>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wifi>;
+	bus-width = <4>;
+	keep-power-in-suspend;
+	mmc-pwrseq = <&wifi_pwrseq>;
+	non-removable;
+	status = "okay";
+};

[Severity: Medium]
Should this node include a vmmc-supply linking to a regulator for the Wi-Fi power enable?

Quoted 3 lines

Modeling WIFI_PWR_EN as a regulator-fixed assigned to vmmc-supply in this usdhc1 node, while leaving only WIFI_RESET in the mmc-pwrseq-simple node, would ensure the power sequencing is handled correctly.

Please double check this also

Frank

Quoted 3 lines

--
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=2

author
#5 lore raw

PATCH v2 3/3 arm64: dts: imx8mm-var-dart: Add support for Variscite Sonata board

In reply to Stefano Radaelli

From: Stefano Radaelli <[email protected]>

Add device tree support for the Variscite Sonata carrier board with the DART-MX8M-MINI system on module.

The Sonata board includes
- uSD Card support
- USB ports and OTG
- Uart, SPI and I2C interfaces
- GPIO Expanders
- RTC module
- TPM module
- CAN peripherals

Link https://variscite.com/carrier-boards/sonata-board/
Signed-off-by Stefano Radaelli <[email protected]>

---
v1->v2:
- Remove HDMI from commit message

 arch/arm64/boot/dts/freescale/Makefile        |   1 +
 .../dts/freescale/imx8mm-var-dart-sonata.dts  | 517 ++++++++++++++++++
 2 files changed, 518 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-var-dart-sonata.dts
arch/arm64/boot/dts/freescale/Makefile +1 -0
index 8ddaab127ab9..694c9aa32779 100644
@@ -166,6 +166,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-prt8mm.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mm-tqma8mqml-mba8mx.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mm-tx8m-1610-moduline-iv-306-d.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mm-tx8m-1610-moduline-mini-111.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-dart-sonata.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony-legacy.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw71xx-0x.dtb
arch/arm64/boot/dts/freescale/imx8mm-var-dart-sonata.dts new file +517 -0

517 lines not on this page · raw message

Signature · 1 line
2.47.3
AI review
#6 lore raw

Re: [PATCH v2 3/3] arm64: dts: imx8mm-var-dart: Add support for Variscite Sonata board

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider: - [High] The MCP251xFD CAN controller uses an active-low interrupt line that must be configured as…

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] The MCP251xFD CAN controller uses an active-low interrupt line that must be configured as level-triggered, but is configured as edge-triggered (IRQ_TYPE_EDGE_FALLING).
- [Low] The ads7846 touchscreen node uses deprecated properties.
- [Low] The pinmux MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 is configured as a GPIO in pinctrl_ecspi1 but GPIO4_IO22 is never used by ecspi1 or any of its subnodes. --

commit bb01573339283cd17f8253331852c339f7a84276
Author: Stefano Radaelli <[email protected]>

arm64: dts: imx8mm-var-dart: Add support for Variscite Sonata board

Add device tree support for the Variscite Sonata carrier board with the DART-MX8M-MINI system on module. This adds support for peripherals including uSD Card, USB, UART, SPI, I2C, RTC, TPM, and CAN interfaces.

Link https://variscite.com/carrier-boards/sonata-board/
Quoted 5 lines
arch/arm64/boot/dts/freescale/imx8mm-var-dart-sonata.dts new file +0 -0
new file mode 100644
index 0000000000000..93b0076987b82

[ ... ]

Quoted 7 lines
arch/arm64/boot/dts/freescale/imx8mm-var-dart-sonata.dts new file +7 -0
+	/* Resistive touch controller */
+	ads7846: touchscreen@0 {
+		compatible = "ti,ads7846";
+		reg = <0>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_restouch>;
+		interrupt-parent = <&gpio1>;

arch/arm64/boot/dts/freescale/imx8mm-var-dart-sonata.dts line 121

Quoted 10 lines
arch/arm64/boot/dts/freescale/imx8mm-var-dart-sonata.dts new file +10 -0
+		interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
+		spi-max-frequency = <1500000>;
+		pendown-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
+		ti,x-min = /bits/ 16 <125>;
+		ti,x-max = /bits/ 16 <4008>;
+		ti,y-min = /bits/ 16 <282>;
+		ti,y-max = /bits/ 16 <3864>;
+		ti,x-plate-ohms = /bits/ 16 <180>;
+		ti,pressure-max = /bits/ 16 <255>;
+		ti,debounce-max = /bits/ 16 <10>;

[Severity: Low]
Are these specific ti,ads7846 properties deprecated in favor of generic touchscreen properties? Using the standard generic bindings might avoid device tree validation warnings.

Quoted 5 lines
arch/arm64/boot/dts/freescale/imx8mm-var-dart-sonata.dts new file +5 -0
+		ti,debounce-tol = /bits/ 16 <3>;
+		ti,debounce-rep = /bits/ 16 <1>;
+		ti,settle-delay-usec = /bits/ 16 <150>;
+		ti,keep-vref-on;
+		wakeup-source;

arch/arm64/boot/dts/freescale/imx8mm-var-dart-sonata.dts line 136

Quoted 10 lines
arch/arm64/boot/dts/freescale/imx8mm-var-dart-sonata.dts new file +10 -0
+	};
+
+	can0: can@1 {
+		compatible = "microchip,mcp251xfd";
+		reg = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_can>;
+		clocks = <&clk40m>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <6 IRQ_TYPE_EDGE_FALLING>;

[Severity: High]
Does the mcp251xfd CAN controller require a level-triggered interrupt rather than edge-triggered? If the device holds the INT pin low while internal interrupts are pending, an edge-triggered setup might miss subsequent interrupts if the line does not transition high to low again, potentially stalling CAN communication.

[ ... ]

Quoted 4 lines
arch/arm64/boot/dts/freescale/imx8mm-var-dart-sonata.dts new file +4 -0
+	pinctrl_captouch: captouchgrp {
+		fsl,pins = <
+			MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14		0x16
+		>;

arch/arm64/boot/dts/freescale/imx8mm-var-dart-sonata.dts line 381

Quoted 10 lines
arch/arm64/boot/dts/freescale/imx8mm-var-dart-sonata.dts new file +10 -0
+	};
+
+	pinctrl_ecspi1: ecspi1grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK		0x13
+			MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI		0x13
+			MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO		0x13
+			MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9		0x13
+			MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12		0x13
+			MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22		0x13

[Severity: Low]
Is MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 used by ecspi1 or its subnodes? It appears to be included in the pinctrl_ecspi1 group without being referenced by the SPI interface, which could unnecessarily claim the pad or cause conflicts.

Quoted 2 lines
arch/arm64/boot/dts/freescale/imx8mm-var-dart-sonata.dts new file +2 -0
+		>;
+	};

[ ... ]

Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=3
#7 lore raw

Re: [PATCH v2 3/3] arm64: dts: imx8mm-var-dart: Add support for Variscite Sonata board

Quoted 37 lines · On Sat, Jun 27, 2026 at 02:57:54PM +0000, [email protected] wrote:

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] The MCP251xFD CAN controller uses an active-low interrupt line that must be configured as level-triggered, but is configured as edge-triggered (IRQ_TYPE_EDGE_FALLING).
- [Low] The ads7846 touchscreen node uses deprecated properties.
- [Low] The pinmux MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 is configured as a GPIO in pinctrl_ecspi1 but GPIO4_IO22 is never used by ecspi1 or any of its subnodes. --

commit bb01573339283cd17f8253331852c339f7a84276
Author: Stefano Radaelli <[email protected]>

arm64: dts: imx8mm-var-dart: Add support for Variscite Sonata board

Add device tree support for the Variscite Sonata carrier board with the DART-MX8M-MINI system on module. This adds support for peripherals including uSD Card, USB, UART, SPI, I2C, RTC, TPM, and CAN interfaces.

Link https://variscite.com/carrier-boards/sonata-board/
Quoted 5 lines
arch/arm64/boot/dts/freescale/imx8mm-var-dart-sonata.dts new file +0 -0
new file mode 100644
index 0000000000000..93b0076987b82

[ ... ]

Quoted 14 lines
arch/arm64/boot/dts/freescale/imx8mm-var-dart-sonata.dts new file +14 -0
+	/* Resistive touch controller */
+	ads7846: touchscreen@0 {
+		compatible = "ti,ads7846";
+		reg = <0>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_restouch>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
+		spi-max-frequency = <1500000>;
+		pendown-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
+		ti,x-min = /bits/ 16 <125>;
+		ti,x-max = /bits/ 16 <4008>;
+		ti,y-min = /bits/ 16 <282>;
+		ti,y-max = /bits/ 16 <3864>;
Quoted 8 lines

arch/arm64/boot/dts/freescale/imx8mm-var-dart-sonata.dts line 121

Quoted 3 lines
arch/arm64/boot/dts/freescale/imx8mm-var-dart-sonata.dts new file +3 -0
+		ti,x-plate-ohms = /bits/ 16 <180>;
+		ti,pressure-max = /bits/ 16 <255>;
+		ti,debounce-max = /bits/ 16 <10>;

[Severity: Low]
Are these specific ti,ads7846 properties deprecated in favor of generic touchscreen properties? Using the standard generic bindings might avoid device tree validation warnings.

Can you check it? should be simple fix.

Quoted 15 lines
Quoted 15 lines
arch/arm64/boot/dts/freescale/imx8mm-var-dart-sonata.dts new file +14 -0
+		ti,debounce-tol = /bits/ 16 <3>;
+		ti,debounce-rep = /bits/ 16 <1>;
+		ti,settle-delay-usec = /bits/ 16 <150>;
+		ti,keep-vref-on;
+		wakeup-source;
+	};
+
+	can0: can@1 {
+		compatible = "microchip,mcp251xfd";
+		reg = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_can>;
+		clocks = <&clk40m>;
+		interrupt-parent = <&gpio1>;
Quoted 8 lines

arch/arm64/boot/dts/freescale/imx8mm-var-dart-sonata.dts line 136

Quoted 1 line
arch/arm64/boot/dts/freescale/imx8mm-var-dart-sonata.dts new file +1 -0
+		interrupts = <6 IRQ_TYPE_EDGE_FALLING>;

[Severity: High]
Does the mcp251xfd CAN controller require a level-triggered interrupt rather than edge-triggered? If the device holds the INT pin low while internal interrupts are pending, an edge-triggered setup might miss subsequent interrupts if the line does not transition high to low again, potentially stalling CAN communication.

Most likely correct, please double check it.

Quoted 14 lines

[ ... ]

Quoted 12 lines
arch/arm64/boot/dts/freescale/imx8mm-var-dart-sonata.dts new file +12 -0
+	pinctrl_captouch: captouchgrp {
+		fsl,pins = <
+			MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14		0x16
+		>;
+	};
+
+	pinctrl_ecspi1: ecspi1grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK		0x13
+			MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI		0x13
+			MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO		0x13
+			MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9		0x13
Quoted 8 lines

arch/arm64/boot/dts/freescale/imx8mm-var-dart-sonata.dts line 381

Quoted 2 lines
arch/arm64/boot/dts/freescale/imx8mm-var-dart-sonata.dts new file +2 -0
+			MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12		0x13
+			MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22		0x13

[Severity: Low]
Is MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 used by ecspi1 or its subnodes? It appears to be included in the pinctrl_ecspi1 group without being referenced by the SPI interface, which could unnecessarily claim the pad or cause conflicts.

Can you check it?

Frank

Quoted 7 lines

arch/arm64/boot/dts/freescale/imx8mm-var-dart-sonata.dts

Quoted 3 lines
arch/arm64/boot/dts/freescale/imx8mm-var-dart-sonata.dts new file +2 -0
+		>;
+	};

[ ... ]

--
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=3