Add support for Variscite VAR-SOM-AM62 and Symphony board
Subsystems (2)
v4 cover Add support for Variscite VAR-SOM-AM62 and Symphony board
The series includes:
- Device tree bindings documentation
- SOM device tree with common peripherals
- Symphony carrier board device tree with board-specific features
The implementation follows the standard SOM + carrier board pattern where the SOM dtsi contains only peripherals mounted on the module, while carrier-specific interfaces are enabled in the board dts.
v3->v4:
- Fix gpio expander interrupt
v2->v3:
- Add audio_refclk1 clock
- Removed pinctrl_vdd_mmc2
- Fix reg_sdhc1_vmmc regulator
- Add missing properties on pca9534 node
v1->v2:
- Fix AM62X_MCU_IOPAD macro
- Fix OPP table comment
- Remove reg_vdd_mmc2 regulator
- Fix reg_sdhc1_vmmc pinctrl
- Add reg_ov5640_buf_en pinctrl
Stefano Radaelli (3):
dt-bindings: arm: ti: Add bindings for Variscite VAR-SOM-AM62
arm64: dts: ti: Add support for Variscite VAR-SOM-AM62
arm64: dts: ti: var-som-am62: Add support for Variscite Symphony Board
.../devicetree/bindings/arm/ti/k3.yaml | 6 + arch/arm64/boot/dts/ti/Makefile | 1 + .../boot/dts/ti/k3-am625-var-som-symphony.dts | 555 ++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am625-var-som.dtsi | 483 +++++++++++++++ 4 files changed, 1045 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am625-var-som-symphony.dts create mode 100644 arch/arm64/boot/dts/ti/k3-am625-var-som.dtsi
base-commit: 5c73cd9f0819c1c44e373e3dabb68318b1de1a12
Signature · 1 line
2.47.3
PATCH v4 1/3 dt-bindings: arm: ti: Add bindings for Variscite VAR-SOM-AM62
From: Stefano Radaelli <[email protected]>
Add devicetree bindings for Variscite VAR-SOM-AM62 System on Module and its carrier boards.
---v3->v4:
-
v2->v3:
-
v1->v2:
-
Documentation/devicetree/bindings/arm/ti/k3.yaml | 6 ++++++ 1 file changed, 6 insertions(+)
Documentation/devicetree/bindings/arm/ti/k3.yaml +6 -0
@@ -104,6 +104,12 @@ properties: - const: tq,am625-tqma6254 - const: ti,am625 + - description: K3 AM625 SoC Variscite SOM and Carrier Boards + items: + - const: variscite,var-som-am62-symphony + - const: variscite,var-som-am62 + - const: ti,am625 + - description: K3 AM62P5 SoC Toradex Verdin Modules and Carrier Boards items: - enum:
Signature · 1 line
2.47.3
PATCH v4 2/3 arm64: dts: ti: Add support for Variscite VAR-SOM-AM62
In reply to Stefano RadaelliFrom: Stefano Radaelli <[email protected]>
Add device tree support for the Variscite VAR-SOM-AM62 system on module. This SOM is designed to be used with various carrier boards.
The module includes:
- AM62x Sitara MPU processor
- Up to 4GB of DDR4-3733 memory
- Up to 128GB eMMC storage memory
- Integrated 10/100/1000 Mbps Ethernet Transceiver Analog Devices
- Audio codec wm8904
- Resistive touch panel interface controller
- I2C, UART and SPI interfaces
- Bluetooth 5.2 + WiFi single or dual band
Only SOM-specific peripherals are enabled by default. Carrier board specific interfaces are left disabled to be enabled in the respective carrier board device trees.
---v3->v4:
-
v2->v3:
- Add audio_refclk1 clock
- Removed pinctrl_vdd_mmc2
v1->v2:
- Fix AM62X_MCU_IOPAD macro
- Fix OPP table comment
- Remove reg_vdd_mmc2 regulator
arch/arm64/boot/dts/ti/k3-am625-var-som.dtsi | 483 +++++++++++++++++++ 1 file changed, 483 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am625-var-som.dtsi
arch/arm64/boot/dts/ti/k3-am625-var-som.dtsi new file +483 -0
@@ -0,0 +1,483 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Common dtsi for Variscite VAR-SOM-AM62 + * + * Link: https://variscite.com/system-on-module-som/ti-sitara-am62x/var-som-am62/ + * + * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ + * Copyright (C) 2026 Stefano Radaelli <[email protected]> + * + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pwm/pwm.h> +#include "k3-am625.dtsi" + +/ { + compatible = "variscite,var-som-am62", "ti,am625"; + + memory@80000000 { + /* 2G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>; + device_type = "memory"; + bootph-pre-ram; + }; + + mmc_pwrseq: mmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc_pwrseq>; + reset-gpios = <&main_gpio0 49 GPIO_ACTIVE_LOW>; + }; + + opp-table { + /* Add 1.4GHz OPP. Requires VDD_CORE to be at 0.85V */ + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-supported-hw = <0x01 0x0004>; + clock-latency-ns = <6000000>; + }; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ramoops@9ca00000 { + compatible = "ramoops"; + reg = <0x00 0x9ca00000 0x00 0x00100000>; + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x00>; + pmsg-size = <0x8000>; + }; + + /* global cma region */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x00 0x8000000>; + linux,cma-default; + }; + + rtos_ipc_memory_region: rtos-ipc-memory@9b500000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9b500000 0x00 0x00300000>; + no-map; + }; + + wkup_r5fss0_core0_dma_memory_region: memory@9da00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9da00000 0x00 0x100000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: memory@9db00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9db00000 0x00 0xc00000>; + no-map; + }; + + secure_tfa_ddr: tfa@9e780000 { + reg = <0x00 0x9e780000 0x00 0x80000>; + alignment = <0x1000>; + no-map; + }; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ + alignment = <0x1000>; + no-map; + }; + }; + + reg_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "On-module +V1.8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <®_3v3>; + regulator-always-on; + regulator-boot-on; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "On-module +V3.3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_3v3_phy: regulator-3v3-phy { + compatible = "regulator-fixed"; + regulator-name = "On-module +V3.3_PHY"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eth_phy>; + gpios = <&main_gpio0 45 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,format = "dsp_b"; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,name = "wm8904-audio"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "IN1L", "Microphone Jack", + "IN1R", "Microphone Jack"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Line", "Line In Jack"; + + codec_dai: simple-audio-card,codec { + sound-dai = <&wm8904>; + }; + + simple-audio-card,cpu { + sound-dai = <&mcasp1>; + }; + }; +}; + +&audio_refclk1 { + assigned-clock-rates = <12000000>; +}; + +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii1>; + status = "okay"; +}; + +&cpsw3g_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mdio1>; + status = "okay"; + + cpsw3g_phy0: ethernet-phy@4 { + compatible = "ethernet-phy-id0283.bc30"; + reg = <4>; + bootph-all; + reset-gpios = <&main_gpio0 46 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <20000>; + }; +}; + +&cpsw_port1 { + /* + * The required RGMII TX and RX 2ns delays are implemented directly + * in hardware via passive delay elements on the SOM PCB. + * No delay configuration is needed in software via PHY driver. + */ + phy-mode = "rgmii"; + phy-handle = <&cpsw3g_phy0>; + status = "okay"; +}; + +&main_i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clock-frequency = <400000>; + status = "okay"; + + wm8904: audio-codec@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + #sound-dai-cells = <0>; + clocks = <&audio_refclk1>; + clock-names = "mclk"; + AVDD-supply = <®_1v8>; + CPVDD-supply = <®_1v8>; + DBVDD-supply = <®_3v3>; + DCVDD-supply = <®_1v8>; + MICVDD-supply = <®_1v8>; + wlf,drc-cfg-names = "default", "peaklimiter", "tradition", + "soft", "music"; + /* + * Config registers per name, respectively: + * KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1 + * KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1 + * KNEE_IP = -42, KNEE_OP = -3, HI_COMP = 0, LO_COMP = 1 + * KNEE_IP = -45, KNEE_OP = -9, HI_COMP = 1/8, LO_COMP = 1 + * KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1 + */ + wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>, + /bits/ 16 <0x04af 0x324b 0x0010 0x0408>, + /bits/ 16 <0x04af 0x324b 0x0028 0x0704>, + /bits/ 16 <0x04af 0x324b 0x0018 0x078c>, + /bits/ 16 <0x04af 0x324b 0x0010 0x050e>; + /* GPIO1 = DMIC_CLK, don't touch others */ + wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>; + }; +}; + +&main_i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clock-frequency = <400000>; + status = "okay"; +}; + +&main_pmx0 { + pinctrl_i2c2: main-i2c2-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */ + AM62X_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */ + >; + }; + + pinctrl_i2c3: main-i2c3-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x01d0, PIN_INPUT, 2) /* (A15) UART0_CTSn.I2C3_SCL */ + AM62X_IOPAD(0x01d4, PIN_INPUT, 2) /* (B15) UART0_RTSn.I2C3_SDA */ + >; + }; + + pinctrl_mcasp1: main-mcasp1-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0090, PIN_INPUT, 2) /* (M24) GPMC0_BE0N_CLE.MCASP1_ACLKX */ + AM62X_IOPAD(0x0098, PIN_INPUT, 2) /* (U23) GPMC0_WAIT0.MCASP1_AFSX */ + AM62X_IOPAD(0x008c, PIN_OUTPUT, 2) /* (L25) GPMC0_WEN.MCASP1_AXR0 */ + AM62X_IOPAD(0x0084, PIN_INPUT, 2) /* (L23) GPMC0_ADVN_ALE.MCASP1_AXR2 */ + AM62X_IOPAD(0x00a0, PIN_OUTPUT, 1) /* (K25) GPMC0_WPn.AUDIO_EXT_REFCLK1 */ + >; + }; + + pinctrl_mdio1: main-mdio1-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x160, PIN_INPUT, 0) /* (AD24) MDIO0_MDC */ + AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */ + >; + }; + + pinctrl_mmc_pwrseq: pinmux-mmc-pwrseq-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x00c8, PIN_OUTPUT, 7) /* (Y25) VOUT0_DATA4.GPIO0_49 */ + >; + }; + + pinctrl_mmc0: main-mmc0-default-pins { + bootph-all; + pinctrl-single,pins = < + AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */ + AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */ + AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */ + AM62X_IOPAD(0x210, PIN_INPUT, 0) /* (AA1) MMC0_DAT1 */ + AM62X_IOPAD(0x20c, PIN_INPUT, 0) /* (AA3) MMC0_DAT2 */ + AM62X_IOPAD(0x208, PIN_INPUT, 0) /* (Y4) MMC0_DAT3 */ + AM62X_IOPAD(0x204, PIN_INPUT, 0) /* (AB2) MMC0_DAT4 */ + AM62X_IOPAD(0x200, PIN_INPUT, 0) /* (AC1) MMC0_DAT5 */ + AM62X_IOPAD(0x1fc, PIN_INPUT, 0) /* (AD2) MMC0_DAT6 */ + AM62X_IOPAD(0x1f8, PIN_INPUT, 0) /* (AC2) MMC0_DAT7 */ + >; + }; + + pinctrl_mmc2: main-mmc2-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x120, PIN_INPUT_PULLUP, 0) /* (C24) MMC2_CMD */ + AM62X_IOPAD(0x118, PIN_INPUT_PULLDOWN, 0) /* (D25) MMC2_CLK */ + AM62X_IOPAD(0x114, PIN_INPUT_PULLUP, 0) /* (B24) MMC2_DAT0 */ + AM62X_IOPAD(0x110, PIN_INPUT_PULLUP, 0) /* (C25) MMC2_DAT1 */ + AM62X_IOPAD(0x10c, PIN_INPUT_PULLUP, 0) /* (E23) MMC2_DAT2 */ + AM62X_IOPAD(0x108, PIN_INPUT_PULLUP, 0) /* (D24) MMC2_DAT3 */ + AM62X_IOPAD(0x11c, PIN_INPUT_PULLUP, 0) /* (#N/A) MMC2_CLKB */ + >; + }; + + pinctrl_restouch: main-restouch-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x00c4, PIN_INPUT_PULLUP, 7) /* (W24) VOUT0_DATA3.GPIO0_48 */ + >; + }; + + pinctrl_rgmii1: main-rgmii1-default-pins { + bootph-all; + pinctrl-single,pins = < + AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17) RGMII1_RD0 */ + AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17) RGMII1_RD1 */ + AM62X_IOPAD(0x154, PIN_INPUT, 0) /* (AB16) RGMII1_RD2 */ + AM62X_IOPAD(0x158, PIN_INPUT, 0) /* (AA15) RGMII1_RD3 */ + AM62X_IOPAD(0x148, PIN_INPUT, 0) /* (AD17) RGMII1_RXC */ + AM62X_IOPAD(0x144, PIN_INPUT, 0) /* (AE17) RGMII1_RX_CTL */ + AM62X_IOPAD(0x134, PIN_INPUT, 0) /* (AE20) RGMII1_TD0 */ + AM62X_IOPAD(0x138, PIN_INPUT, 0) /* (AD20) RGMII1_TD1 */ + AM62X_IOPAD(0x13c, PIN_INPUT, 0) /* (AE18) RGMII1_TD2 */ + AM62X_IOPAD(0x140, PIN_INPUT, 0) /* (AD18) RGMII1_TD3 */ + AM62X_IOPAD(0x130, PIN_INPUT, 0) /* (AE19) RGMII1_TXC */ + AM62X_IOPAD(0x12c, PIN_INPUT, 0) /* (AD19) RGMII1_TX_CTL */ + AM62X_IOPAD(0x00bc, PIN_INPUT, 7) /* (V24) VOUT0_DATA1.GPIO0_46 */ + >; + }; + + pinctrl_eth_phy: main-eth-phy-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x00b8, PIN_INPUT, 7) /* (U22) VOUT0_DATA0.GPIO0_45 */ + >; + }; + + pinctrl_spi0: main-spi0-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x01bc, PIN_OUTPUT, 0) /* (A14) SPI0_CLK */ + AM62X_IOPAD(0x01b4, PIN_OUTPUT, 0) /* (A13) SPI0_CS0 */ + AM62X_IOPAD(0x01c0, PIN_OUTPUT, 0) /* (B13) SPI0_D0 */ + AM62X_IOPAD(0x01c4, PIN_INPUT, 0) /* (B14) SPI0_D1 */ + >; + }; + + pinctrl_uart5: main-uart5-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x00ec, PIN_INPUT, 4) /* (AA24) VOUT0_DATA13.UART5_CTSn */ + AM62X_IOPAD(0x00e8, PIN_OUTPUT, 4) /* (AB25) VOUT0_DATA12.UART5_RTSn */ + AM62X_IOPAD(0x00d0, PIN_INPUT, 4) /* (Y23) VOUT0_DATA6.UART5_RXD */ + AM62X_IOPAD(0x00d4, PIN_OUTPUT, 4) /* (AA25) VOUT0_DATA7.UART5_TXD */ + >; + }; +}; + +&mcu_pmx0 { + pinctrl_wkup_clkout0: wkup-clkout0-default-pins { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x0084, PIN_OUTPUT, 0) /* (F13) WKUP_CLKOUT0 */ + >; + }; +}; + +&main_spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + ti,pindir-d0-out-d1-in; + status = "okay"; + + /* Resistive touch controller */ + ads7846: touchscreen@0 { + compatible = "ti,ads7846"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_restouch>; + interrupt-parent = <&main_gpio0>; + interrupts = <48 IRQ_TYPE_EDGE_FALLING>; + spi-max-frequency = <1500000>; + pendown-gpio = <&main_gpio0 48 GPIO_ACTIVE_LOW>; + ti,x-min = /bits/ 16 <125>; + ti,x-max = /bits/ 16 <4008>; + ti,y-min = /bits/ 16 <282>; + ti,y-max = /bits/ 16 <3864>; + ti,x-plate-ohms = /bits/ 16 <180>; + ti,pressure-max = /bits/ 16 <255>; + ti,debounce-max = /bits/ 16 <10>; + ti,debounce-tol = /bits/ 16 <3>; + ti,debounce-rep = /bits/ 16 <1>; + ti,settle-delay-usec = /bits/ 16 <150>; + ti,keep-vref-on; + wakeup-source; + }; +}; + +/* On-module Bluetooth */ +&main_uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + uart-has-rtscts; + status = "okay"; +}; + +&mcasp1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcasp1>; + op-mode = <0>; /* MCASP_IIS_MODE */ + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 1 0 2 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + >; + tdm-slots = <2>; + #sound-dai-cells = <0>; + status = "okay"; +}; + +/* On-module eMMC */ +&sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc0>; + bootph-all; + disable-wp; + mmc-pwrseq = <&mmc_pwrseq>; + non-removable; + status="okay"; +}; + +/* On-module Wi-Fi */ +&sdhci2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc2>, <&pinctrl_wkup_clkout0>; + #address-cells = <1>; + #size-cells = <0>; + assigned-clocks = <&k3_clks 157 158>; /* wkup_clkout_sel_out0 */ + assigned-clock-parents = <&k3_clks 157 164>; /* clk_32k_rc_sel_out0 */ + bus-width = <4>; + disable-wp; + non-removable; + cap-power-off-card; + status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + }; +}; + +&usbss0 { + ti,vbus-divider; +}; + +&usbss1 { + ti,vbus-divider; +}; + +/* mcu_gpio0 and mcu_gpio_intr are reserved for mcu firmware usage */ +&mcu_gpio0 { + status = "reserved"; +}; + +&mcu_gpio_intr { + status = "reserved"; +}; + +&wkup_rtc0 { + status = "disabled"; +}; + +&wkup_rti0 { + /* WKUP RTI0 is used by DM firmware */ + status = "reserved"; +}; + +&wkup_uart0 { + /* WKUP UART0 is used by DM firmware */ + status = "reserved"; +}; + +&main_uart1 { + /* Main UART1 is used by TIFS firmware */ + status = "reserved"; +}; + +#include "k3-am62-ti-ipc-firmware.dtsi"
Signature · 1 line
2.47.3
PATCH v4 3/3 arm64: dts: ti: var-som-am62: Add support for Variscite Symphony Board
In reply to Stefano RadaelliFrom: Stefano Radaelli <[email protected]>
Add device tree support for the Variscite Symphony carrier board with the VAR-SOM-AM62 system on module.
The Symphony board includes
- uSD Card support
- USB ports and OTG
- Additional Gigabit Ethernet interface
- Uart interfaces
- OV5640 Camera support
- GPIO Expander and TPM
- CAN, I2C and general purpose interfaces
- Capacitive touch controller
---v3->v4:
- Fix gpio expander interrupt
v2->v3:
- Fix reg_sdhc1_vmmc regulator
- Add missing properties on pca9534 node
v1->v2:
- Fix reg_sdhc1_vmmc pinctrl
- Add reg_ov5640_buf_en pinctrl
arch/arm64/boot/dts/ti/Makefile | 1 + .../boot/dts/ti/k3-am625-var-som-symphony.dts | 555 ++++++++++++++++++ 2 files changed, 556 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am625-var-som-symphony.dts
arch/arm64/boot/dts/ti/Makefile +1 -0
@@ -29,6 +29,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am625-beagleplay-csi2-tevi-ov5640.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-phyboard-lyra-rdk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-sk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-tqma62xx-mba62xx.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am625-var-som-symphony.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-dev-mezzanine-can.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-dev-mezzanine-panel-cap-touch-10inch-lvds.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-dev-nau8822-btl.dtbo
arch/arm64/boot/dts/ti/k3-am625-var-som-symphony.dts new file +555 -0
555 lines not on this page · raw message
Signature · 1 line
2.47.3
[email protected]
AI reviewRe: [PATCH v4 3/3] arm64: dts: ti: var-som-am62: Add support for Variscite Symphony Board
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider: - [High] Driver probe failure due to unsupported interrupt trigger type - [Medium] Pinmux configuration…
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] Driver probe failure due to unsupported interrupt trigger type
- [Medium] Pinmux configuration error for RGMII2 transmit pins
--
--- Patch [3]: [PATCH v4 3/3] arm64: dts: ti: var-som-am62: Add support for Variscite Symphony Board --- commit eae5a6eae63323e628c7dec958171ae3d0b8c5fd
Author: Stefano Radaelli <[email protected]>
arm64: dts: ti: var-som-am62: Add support for Variscite Symphony Board
Add device tree support for the Variscite Symphony carrier board with the VAR-SOM-AM62 system on module.
Quoted 5 lines
arch/arm64/boot/dts/ti/k3-am625-var-som-symphony.dts new file +0
-0
[ ... ]
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+&main_i2c0 {
arch/arm64/boot/dts/ti/k3-am625-var-som-symphony.dts new file +7
-0+ pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + clock-frequency = <400000>; + status = "okay"; + + /* GPIO expander */ + pca9534: gpio@20 {
arch/arm64/boot/dts/ti/k3-am625-var-som-symphony.dts line 246
Quoted 10 lines
arch/arm64/boot/dts/ti/k3-am625-var-som-symphony.dts new file +10
-0+ compatible = "nxp,pca9534"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pca9534>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&main_gpio1>; + interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
[Severity: High]
Will this interrupt trigger type cause the pca9534 probe to fail?
The parent interrupt controller main_gpio1 uses the gpio-davinci driver, which only supports edge triggers in its gpio_irq_type() callback. Requesting a level-low trigger here will return -EINVAL during IRQ setup.
If the probe fails, could it also break the secondary Ethernet PHY (cpsw3g_phy1) since it relies on this expander for its reset GPIO?
[ ... ]
Quoted 5 lines
arch/arm64/boot/dts/ti/k3-am625-var-som-symphony.dts new file +5
-0+ pinctrl_rgmii2: main-rgmii2-default-pins { + bootph-all; + pinctrl-single,pins = < + AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */ + AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */
arch/arm64/boot/dts/ti/k3-am625-var-som-symphony.dts line 436
Quoted 10 lines
arch/arm64/boot/dts/ti/k3-am625-var-som-symphony.dts new file +10
-0+ AM62X_IOPAD(0x18c, PIN_INPUT, 0) /* (AC21) RGMII2_RD2 */ + AM62X_IOPAD(0x190, PIN_INPUT, 0) /* (AE22) RGMII2_RD3 */ + AM62X_IOPAD(0x180, PIN_INPUT, 0) /* (AD23) RGMII2_RXC */ + AM62X_IOPAD(0x17c, PIN_INPUT, 0) /* (AD22) RGMII2_RX_CTL */ + AM62X_IOPAD(0x16c, PIN_INPUT, 0) /* (Y18) RGMII2_TD0 */ + AM62X_IOPAD(0x170, PIN_INPUT, 0) /* (AA18) RGMII2_TD1 */ + AM62X_IOPAD(0x174, PIN_INPUT, 0) /* (AD21) RGMII2_TD2 */ + AM62X_IOPAD(0x178, PIN_INPUT, 0) /* (AC20) RGMII2_TD3 */ + AM62X_IOPAD(0x168, PIN_INPUT_PULLDOWN, 0) /* (AE21) RGMII2_TXC */ + AM62X_IOPAD(0x164, PIN_INPUT, 0) /* (AA19) RGMII2_TX_CTL */
[Severity: Medium]
Should the RGMII2 transmit pins (TD0-TD3, TXC, TX_CTL) be configured as outputs rather than inputs?
Using PIN_INPUT_PULLDOWN on RGMII2_TXC enables an active pull-down resistor on the 125MHz transmit clock. Does this force the MAC output driver to constantly fight the pull-down and degrade the high-speed signal integrity?
Quoted 2 lines
arch/arm64/boot/dts/ti/k3-am625-var-som-symphony.dts new file +2
-0+ >; + };
Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=3
Hi Stefano Radaelli,
Quoted 8 lines · Stefano Radaelli
Add support for Variscite VAR-SOM-AM62 and Symphony board
The series includes:
- Device tree bindings documentation
- SOM device tree with common peripherals
- Symphony carrier board device tree with board-specific features[...]
I have applied the following to branch ti-k3-dts-next on [1]. Thank you!
[1/3] dt-bindings: arm: ti: Add bindings for Variscite VAR-SOM-AM62
commit: 8571d1e223a5d220aba7e323b4de36d7341ee37e
[2/3] arm64: dts: ti: Add support for Variscite VAR-SOM-AM62
commit: 5f865bbef8e5a91780064b847365d755845bc974
[3/3] arm64: dts: ti: var-som-am62: Add support for Variscite Symphony Board
commit: 5fde9c21c671ff501523d55138b4f5eeb577b97eAll being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent up the chain during the next merge window (or sooner if it is a relevant bug fix), however if problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying to this mail.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git
--
Vignesh