perf/x86: Fix perf_event_print_debug() on non-Intel PMUs
Subsystems (2)
cover perf/x86: Fix perf_event_print_debug() on non-Intel PMUs
Petr Tesarik reported that reading MSR_ARCH_PERFMON_FIXED_CTR_CTRL raises a #GP on AMD processors that support PerfMonV2, and proposed skipping that register when no fixed counters are implemented [1].
However, perf_event_print_debug() also dumps the global control and status registers whenever x86_pmu.version >= 2, and reads Intel Architectural PerfMon MSRs to do so. That condition used to be Intel-specific, but since commit 21d59e3e2c40 ("perf/x86/amd/core:
Detect PerfMonV2 support"), x86_pmu.version is also set to 2 on AMD processors that support PerfMonV2, where none of those registers are available.
The same reasoning therefore applies to the other registers read here, so rather than special-casing each one or reinstating a vendor check, this series makes the global register dump a vendor-specific operation.
[1] https://lore.kernel.org/all/[email protected]/
Sandipan Das (3):
perf/x86: Add x86_pmu::print_debug
perf/x86: Move MSR_CORE_PERF_GLOBAL_* dump to vendor code perf/x86/amd: Implement x86_pmu::print_debug
arch/x86/events/amd/core.c | 20 ++++++++++++ arch/x86/events/core.c | 56 +++++++++++++++------------------- arch/x86/events/intel/core.c | 32 +++++++++++++++++++ arch/x86/events/perf_event.h | 4 +++ arch/x86/events/zhaoxin/core.c | 18 +++++++++++ 5 files changed, 98 insertions(+), 32 deletions(-)
Signature · 1 line
2.53.0
PATCH 1/3 perf/x86: Add x86_pmu::print_debug
perf_event_print_debug() dumps the global control and status MSRs whenever x86_pmu.version >= 2, reading registers that exist only on Intel-compatible PMUs. This is not safe since x86_pmu.version is not Intel-specific and is now set by other vendors whose global registers use different addresses.
As a first step, split perf_event_print_debug() in two. The register dump moves into a new common helper, x86_pmu_print_debug(), leaving perf_event_print_debug() to handle the preamble and dispatch to an optional x86_pmu::print_debug method. This lets each vendor-specific PMU dump its own global state before chaining into the common helper. PMUs that do not implement the method, such as those with x86_pmu.version < 2, get the common helper alone.
No functional change intended.
--- arch/x86/events/core.c | 29 ++++++++++++++++++++++------- arch/x86/events/perf_event.h | 4 ++++ 2 files changed, 26 insertions(+), 7 deletions(-)
arch/x86/events/core.c +22 -7
@@ -1557,7 +1557,7 @@ static void x86_pmu_start(struct perf_event *event, int flags)perf_event_update_userpage (event); } -void perf_event_print_debug (void ) +void x86_pmu_print_debug (int cpu) {u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;unsigned long *cntr_mask, *fixed_cntr_mask;
@@ -1566,17 +1566,11 @@ void perf_event_print_debug(void)u64 pebs, debugctl;int cpu, idx; -guard (irqsave)(); - - cpu =smp_processor_id (); cpuc = &per_cpu (cpu_hw_events, cpu); cntr_mask =hybrid (cpuc->pmu, cntr_mask); fixed_cntr_mask =hybrid (cpuc->pmu, fixed_cntr_mask); pebs_constraints =hybrid (cpuc->pmu, pebs_constraints); -if (!*(u64 *)cntr_mask) -return ; -if (x86_pmu.version >=2 ) {rdmsrq (MSR_CORE_PERF_GLOBAL_CTRL , ctrl);rdmsrq (MSR_CORE_PERF_GLOBAL_STATUS , status);
@@ -1622,6 +1616,27 @@ void perf_event_print_debug(void) } } +void perf_event_print_debug (void ) +{ +struct cpu_hw_events *cpuc; +unsigned long *cntr_mask; +int cpu; + +guard (irqsave)(); + + cpu =smp_processor_id (); + cpuc = &per_cpu (cpu_hw_events, cpu); + cntr_mask =hybrid (cpuc->pmu, cntr_mask); + +if (!*(u64 *)cntr_mask) +return ; + +if (x86_pmu.print_debug) + x86_pmu.print_debug (cpu); +else +x86_pmu_print_debug (cpu); +} +void x86_pmu_stop (struct perf_event *event,int flags) {struct cpu_hw_events *cpuc =this_cpu_ptr (&cpu_hw_events);
arch/x86/events/perf_event.h +4 -0
@@ -1052,6 +1052,8 @@ struct x86_pmu {int num_hybrid_pmus;struct x86_hybrid_pmu *hybrid_pmu;enum intel_cpu_type (*get_hybrid_cpu_type) (void ); + +void (*print_debug)(int cpu); };struct x86_perf_task_context_opt {
@@ -1316,6 +1318,8 @@ int x86_pmu_handle_irq(struct pt_regs *regs);void x86_pmu_show_pmu_cap (struct pmu *pmu); +void x86_pmu_print_debug (int cpu); +static inline int x86_pmu_num_counters (struct pmu *pmu) {return hweight64 (hybrid (pmu, cntr_mask64));
Signature · 1 line
2.53.0
[email protected]
AI reviewRe: [PATCH 1/3] perf/x86: Add x86_pmu::print_debug
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [Low] The function `x86_pmu_print_debug` takes `cpu` as a parameter but also declares it as a local…
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The function x86_pmu_print_debug takes cpu as a parameter but also declares it as a local variable. This results in a compilation error due to the redefinition of the identifier in the same scope. --
--- Patch [1]: [PATCH 1/3] perf/x86: Add x86_pmu::print_debug --- commit 020114d6f9bb4628136240e2b9270b949589ab7b
Author: Sandipan Das <[email protected]>
perf/x86: Add x86_pmu::print_debug
This commit splits out the register dumping portion of perf_event_print_debug() into a new x86_pmu_print_debug() helper. It adds an optional print_debug method to x86_pmu to allow vendor-specific PMUs to dump their global state.
Quoted 14 lines
arch/x86/events/core.c +1
-1@@ -1557,7 +1557,7 @@ static void x86_pmu_start(struct perf_event *event, int flags)perf_event_update_userpage (event); } -void perf_event_print_debug (void ) +void x86_pmu_print_debug (int cpu) {u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;unsigned long *cntr_mask, *fixed_cntr_mask;
arch/x86/events/core.c void perf_event_print_debug(void) · line 1567
Quoted 2 lines
arch/x86/events/core.c +0
-0@@ -1566,17 +1566,11 @@ void perf_event_print_debug(void)u64 pebs, debugctl;int cpu, idx;
[Severity: Low]
Will this cause a compilation error? The x86_pmu_print_debug() function now takes 'cpu' as a parameter, but the local variable declaration 'int cpu' was left in place, which redefines the identifier in the same scope.
Quoted 5 lines
arch/x86/events/core.c +0
-3-guard (irqsave)(); - - cpu =smp_processor_id (); cpuc = &per_cpu (cpu_hw_events, cpu);
Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=1
Re: [PATCH 1/3] perf/x86: Add x86_pmu::print_debug
In reply to Sandipan DasQuoted 66 lines · Sandipan Das
perf_event_print_debug()dumps the global control and status MSRs whenever x86_pmu.version >= 2, reading registers that exist only on Intel-compatible PMUs. This is not safe since x86_pmu.version is not Intel-specific and is now set by other vendors whose global registers use different addresses.As a first step, split
perf_event_print_debug()in two. The register dump moves into a new common helper,x86_pmu_print_debug(), leavingperf_event_print_debug()to handle the preamble and dispatch to an optionalx86_pmu::print_debugmethod. This lets each vendor-specific PMU dump its own global state before chaining into the common helper. PMUs that do not implement the method, such as those with x86_pmu.version < 2, get the common helper alone.No functional change intended.
Signed-off-by Sandipan Das <[email protected]>--- arch/x86/events/core.c | 29 ++++++++++++++++++++++------- arch/x86/events/perf_event.h | 4 ++++ 2 files changed, 26 insertions(+), 7 deletions(-)arch/x86/events/core.c +10
-7@@ -1557,7 +1557,7 @@ static void x86_pmu_start(struct perf_event *event, int flags)perf_event_update_userpage (event); } -void perf_event_print_debug (void ) +void x86_pmu_print_debug (int cpu) {u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;unsigned long *cntr_mask, *fixed_cntr_mask;@@ -1566,17 +1566,11 @@ void perf_event_print_debug(void)u64 pebs, debugctl;int cpu, idx; -guard (irqsave)(); - - cpu =smp_processor_id (); cpuc = &per_cpu (cpu_hw_events, cpu); cntr_mask =hybrid (cpuc->pmu, cntr_mask); fixed_cntr_mask =hybrid (cpuc->pmu, fixed_cntr_mask); pebs_constraints =hybrid (cpuc->pmu, pebs_constraints); -if (!*(u64 *)cntr_mask) -return ; -if (x86_pmu.version >=2 ) {rdmsrq (MSR_CORE_PERF_GLOBAL_CTRL , ctrl);rdmsrq (MSR_CORE_PERF_GLOBAL_STATUS , status);@@ -1622,6 +1616,27 @@ void perf_event_print_debug(void) } } +void perf_event_print_debug (void ) +{ +struct cpu_hw_events *cpuc; +unsigned long *cntr_mask; +int cpu; + +guard (irqsave)(); + + cpu =smp_processor_id ();
arch/x86/events/core.c void perf_event_print_debug(void) · line 1637
Quoted 10 lines
arch/x86/events/core.c +10
-0+ cpuc = &per_cpu (cpu_hw_events, cpu); + cntr_mask =hybrid (cpuc->pmu, cntr_mask); + +if (!*(u64 *)cntr_mask) +return ; + +if (x86_pmu.print_debug) + x86_pmu.print_debug (cpu); +else +x86_pmu_print_debug (cpu);
The logic looks good, but better change this to the static_call() just like other x86_pmu callbacks. It eliminates the branch prediction cost. Thanks.
Quoted 27 lines
arch/x86/events/core.c +2
-0+} +void x86_pmu_stop (struct perf_event *event,int flags) {struct cpu_hw_events *cpuc =this_cpu_ptr (&cpu_hw_events);arch/x86/events/perf_event.h +4
-0@@ -1052,6 +1052,8 @@ struct x86_pmu {int num_hybrid_pmus;struct x86_hybrid_pmu *hybrid_pmu;enum intel_cpu_type (*get_hybrid_cpu_type) (void ); + +void (*print_debug)(int cpu); };struct x86_perf_task_context_opt {@@ -1316,6 +1318,8 @@ int x86_pmu_handle_irq(struct pt_regs *regs);void x86_pmu_show_pmu_cap (struct pmu *pmu); +void x86_pmu_print_debug (int cpu); +static inline int x86_pmu_num_counters (struct pmu *pmu) {return hweight64 (hybrid (pmu, cntr_mask64));
Re: [PATCH 1/3] perf/x86: Add x86_pmu::print_debug
Quoted 72 lines · Dapeng
Quoted 71 lines · Sandipan Das
perf_event_print_debug()dumps the global control and status MSRs whenever x86_pmu.version >= 2, reading registers that exist only on Intel-compatible PMUs. This is not safe since x86_pmu.version is not Intel-specific and is now set by other vendors whose global registers use different addresses.As a first step, split
perf_event_print_debug()in two. The register dump moves into a new common helper,x86_pmu_print_debug(), leavingperf_event_print_debug()to handle the preamble and dispatch to an optionalx86_pmu::print_debugmethod. This lets each vendor-specific PMU dump its own global state before chaining into the common helper. PMUs that do not implement the method, such as those with x86_pmu.version < 2, get the common helper alone.No functional change intended.
Signed-off-by Sandipan Das <[email protected]>--- arch/x86/events/core.c | 29 ++++++++++++++++++++++------- arch/x86/events/perf_event.h | 4 ++++ 2 files changed, 26 insertions(+), 7 deletions(-)arch/x86/events/core.c +15
-7@@ -1557,7 +1557,7 @@ static void x86_pmu_start(struct perf_event *event, int flags)perf_event_update_userpage (event); } -void perf_event_print_debug (void ) +void x86_pmu_print_debug (int cpu) {u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;unsigned long *cntr_mask, *fixed_cntr_mask;@@ -1566,17 +1566,11 @@ void perf_event_print_debug(void)u64 pebs, debugctl;int cpu, idx; -guard (irqsave)(); - - cpu =smp_processor_id (); cpuc = &per_cpu (cpu_hw_events, cpu); cntr_mask =hybrid (cpuc->pmu, cntr_mask); fixed_cntr_mask =hybrid (cpuc->pmu, fixed_cntr_mask); pebs_constraints =hybrid (cpuc->pmu, pebs_constraints); -if (!*(u64 *)cntr_mask) -return ; -if (x86_pmu.version >=2 ) {rdmsrq (MSR_CORE_PERF_GLOBAL_CTRL , ctrl);rdmsrq (MSR_CORE_PERF_GLOBAL_STATUS , status);@@ -1622,6 +1616,27 @@ void perf_event_print_debug(void) } } +void perf_event_print_debug (void ) +{ +struct cpu_hw_events *cpuc; +unsigned long *cntr_mask; +int cpu; + +guard (irqsave)(); + + cpu =smp_processor_id (); + cpuc = &per_cpu (cpu_hw_events, cpu); + cntr_mask =hybrid (cpuc->pmu, cntr_mask); + +if (!*(u64 *)cntr_mask) +return ;
Quoted 8 lines
arch/x86/events/core.c void perf_event_print_debug(void) · line 1637
Quoted 5 lines
arch/x86/events/core.c +5
-0+ +if (x86_pmu.print_debug) + x86_pmu.print_debug (cpu); +else +x86_pmu_print_debug (cpu);The logic looks good, but better change this to the
static_call()just like otherx86_pmucallbacks. It eliminates the branch prediction cost. Thanks.
Is it worth the extra complexity for code that is used only by SysRq debugging?
Of course, if it's trivial, let's do it anyway.
Petr T
Re: [PATCH 1/3] perf/x86: Add x86_pmu::print_debug
Quoted 82 lines · Petr Tesarik
Quoted 71 lines · Dapeng
Quoted 70 lines · Sandipan Das
perf_event_print_debug()dumps the global control and status MSRs whenever x86_pmu.version >= 2, reading registers that exist only on Intel-compatible PMUs. This is not safe since x86_pmu.version is not Intel-specific and is now set by other vendors whose global registers use different addresses.As a first step, split
perf_event_print_debug()in two. The register dump moves into a new common helper,x86_pmu_print_debug(), leavingperf_event_print_debug()to handle the preamble and dispatch to an optionalx86_pmu::print_debugmethod. This lets each vendor-specific PMU dump its own global state before chaining into the common helper. PMUs that do not implement the method, such as those with x86_pmu.version < 2, get the common helper alone.No functional change intended.
Signed-off-by Sandipan Das <[email protected]>--- arch/x86/events/core.c | 29 ++++++++++++++++++++++------- arch/x86/events/perf_event.h | 4 ++++ 2 files changed, 26 insertions(+), 7 deletions(-)arch/x86/events/core.c +14
-7@@ -1557,7 +1557,7 @@ static void x86_pmu_start(struct perf_event *event, int flags)perf_event_update_userpage (event); } -void perf_event_print_debug (void ) +void x86_pmu_print_debug (int cpu) {u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;unsigned long *cntr_mask, *fixed_cntr_mask;@@ -1566,17 +1566,11 @@ void perf_event_print_debug(void)u64 pebs, debugctl;int cpu, idx; -guard (irqsave)(); - - cpu =smp_processor_id (); cpuc = &per_cpu (cpu_hw_events, cpu); cntr_mask =hybrid (cpuc->pmu, cntr_mask); fixed_cntr_mask =hybrid (cpuc->pmu, fixed_cntr_mask); pebs_constraints =hybrid (cpuc->pmu, pebs_constraints); -if (!*(u64 *)cntr_mask) -return ; -if (x86_pmu.version >=2 ) {rdmsrq (MSR_CORE_PERF_GLOBAL_CTRL , ctrl);rdmsrq (MSR_CORE_PERF_GLOBAL_STATUS , status);@@ -1622,6 +1616,27 @@ void perf_event_print_debug(void) } } +void perf_event_print_debug (void ) +{ +struct cpu_hw_events *cpuc; +unsigned long *cntr_mask; +int cpu; + +guard (irqsave)(); + + cpu =smp_processor_id (); + cpuc = &per_cpu (cpu_hw_events, cpu); + cntr_mask =hybrid (cpuc->pmu, cntr_mask); + +if (!*(u64 *)cntr_mask)Quoted 8 lines
arch/x86/events/core.c void perf_event_print_debug(void) · line 1637
Quoted 6 lines
arch/x86/events/core.c +6
-0+return ; + +if (x86_pmu.print_debug) + x86_pmu.print_debug (cpu); +else +x86_pmu_print_debug (cpu);The logic looks good, but better change this to the
static_call()just like otherx86_pmucallbacks. It eliminates the branch prediction cost. Thanks.
Quoted 2 lines
Is it worth the extra complexity for code that is used only by SysRq debugging?
perf_event_print_debug() is not just called in sysrq debugging, it's also called by intel_pmu_handle_irq() which is a NMI handler. Any code in NMI handler should be as simple as possible. Thanks.
Quoted 4 lines
Of course, if it's trivial, let's do it anyway.
Petr T
PATCH 2/3 perf/x86: Move MSR_CORE_PERF_GLOBAL_* dump to vendor code
In reply to Sandipan DasMSR_CORE_PERF_GLOBAL_{CTRL,STATUS} and MSR_ARCH_PERFMON_FIXED_CTR_CTRL are Intel Architectural PerfMon registers that are not available on AMD processors.
Since commit 21d59e3e2c40 ("perf/x86/amd/core: Detect PerfMonV2 support"), x86_pmu.version is also set to 2 on AMD processors that support PerfMonV2, which makes perf_event_print_debug() attempt to read these non-existent MSRs. The resulting #GP is caught by the exception fixup, but as the reads are unchecked, SysRq-P logs an "unchecked MSR access error" for each one and then prints zeroes as if they were valid register contents.
Implement x86_pmu::print_debug for the Intel and Zhaoxin PMUs, which do have these registers, and drop the reads from common code. Both are wired up through PMU descriptors that are selected only when the PMU version is at least 2, so the version check is no longer needed.
MSR_CORE_PERF_GLOBAL_OVF_CTRL is also dropped from the dump since it is write-to-clear and does not read back the overflow state.
--- arch/x86/events/core.c | 29 +++-------------------------- arch/x86/events/intel/core.c | 32 ++++++++++++++++++++++++++++++++ arch/x86/events/zhaoxin/core.c | 18 ++++++++++++++++++ 3 files changed, 53 insertions(+), 26 deletions(-)
arch/x86/events/core.c +3 -26
@@ -1559,38 +1559,15 @@ static void x86_pmu_start(struct perf_event *event, int flags)void x86_pmu_print_debug (int cpu) { -u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;unsigned long *cntr_mask, *fixed_cntr_mask; -struct event_constraint *pebs_constraints; +u64 pmc_ctrl, pmc_count, prev_left;struct cpu_hw_events *cpuc; -u64 pebs, debugctl; -int cpu, idx; +int idx; cpuc = &per_cpu (cpu_hw_events, cpu); cntr_mask =hybrid (cpuc->pmu, cntr_mask); fixed_cntr_mask =hybrid (cpuc->pmu, fixed_cntr_mask); - pebs_constraints =hybrid (cpuc->pmu, pebs_constraints); - -if (x86_pmu.version >=2 ) { -rdmsrq (MSR_CORE_PERF_GLOBAL_CTRL , ctrl); -rdmsrq (MSR_CORE_PERF_GLOBAL_STATUS , status); -rdmsrq (MSR_CORE_PERF_GLOBAL_OVF_CTRL , overflow); -rdmsrq (MSR_ARCH_PERFMON_FIXED_CTR_CTRL , fixed); - -pr_info ("\n" ); -pr_info ("CPU#%d: ctrl: %016llx\n" , cpu, ctrl); -pr_info ("CPU#%d: status: %016llx\n" , cpu, status); -pr_info ("CPU#%d: overflow: %016llx\n" , cpu, overflow); -pr_info ("CPU#%d: fixed: %016llx\n" , cpu, fixed); -if (pebs_constraints) { -rdmsrq (MSR_IA32_PEBS_ENABLE , pebs); -pr_info ("CPU#%d: pebs: %016llx\n" , cpu, pebs); - } -if (x86_pmu.lbr_nr) { -rdmsrq (MSR_IA32_DEBUGCTLMSR , debugctl); -pr_info ("CPU#%d: debugctl: %016llx\n" , cpu, debugctl); - } - } +pr_info ("CPU#%d: active: %016llx\n" , cpu, *(u64 *)cpuc->active_mask);for_each_set_bit (idx, cntr_mask,X86_PMC_IDX_MAX ) {
arch/x86/events/intel/core.c +32 -0
@@ -3736,6 +3736,36 @@ static void intel_pmu_reset(void)local_irq_restore (flags); } +static void intel_pmu_print_debug (int cpu) +{ +struct event_constraint *pebs_constraints; +struct cpu_hw_events *cpuc; +u64 ctrl, status, fixed; +u64 pebs, debugctl; + + cpuc = &per_cpu (cpu_hw_events, cpu); + pebs_constraints =hybrid (cpuc->pmu, pebs_constraints); + +rdmsrq (MSR_CORE_PERF_GLOBAL_CTRL , ctrl); +rdmsrq (MSR_CORE_PERF_GLOBAL_STATUS , status); +rdmsrq (MSR_ARCH_PERFMON_FIXED_CTR_CTRL , fixed); + +pr_info ("\n" ); +pr_info ("CPU#%d: ctrl: %016llx\n" , cpu, ctrl); +pr_info ("CPU#%d: status: %016llx\n" , cpu, status); +pr_info ("CPU#%d: fixed: %016llx\n" , cpu, fixed); +if (pebs_constraints) { +rdmsrq (MSR_IA32_PEBS_ENABLE , pebs); +pr_info ("CPU#%d: pebs: %016llx\n" , cpu, pebs); + } +if (x86_pmu.lbr_nr) { +rdmsrq (MSR_IA32_DEBUGCTLMSR , debugctl); +pr_info ("CPU#%d: debugctl: %016llx\n" , cpu, debugctl); + } + +x86_pmu_print_debug (cpu); +} +/* * We may be running with guest PEBS events created by KVM, and the * PEBS records are logged into the guest's DS and invisible to host.
@@ -6680,6 +6710,8 @@ static __initconst const struct x86_pmu intel_pmu = {* counting SMM by default. */ .attr_freeze_on_smi = 1, + + .print_debug = intel_pmu_print_debug, };static __init void intel_clovertown_quirk (void )
arch/x86/events/zhaoxin/core.c +18 -0
@@ -288,6 +288,22 @@ static inline void zxc_pmu_ack_status(u64 ack)zhaoxin_pmu_disable_all (); } +static void zhaoxin_pmu_print_debug (int cpu) +{ +u64 ctrl, status, fixed; + +rdmsrq (MSR_CORE_PERF_GLOBAL_CTRL , ctrl); +rdmsrq (MSR_CORE_PERF_GLOBAL_STATUS , status); +rdmsrq (MSR_ARCH_PERFMON_FIXED_CTR_CTRL , fixed); + +pr_info ("\n" ); +pr_info ("CPU#%d: ctrl: %016llx\n" , cpu, ctrl); +pr_info ("CPU#%d: status: %016llx\n" , cpu, status); +pr_info ("CPU#%d: fixed: %016llx\n" , cpu, fixed); + +x86_pmu_print_debug (cpu); +} +static void zhaoxin_pmu_disable_fixed (struct hw_perf_event *hwc) {int idx = hwc->idx -INTEL_PMC_IDX_FIXED ;
@@ -479,6 +495,8 @@ static const struct x86_pmu zhaoxin_pmu __initconst = { .format_attrs = zx_arch_formats_attr, .events_sysfs_show = zhaoxin_event_sysfs_show, + + .print_debug = zhaoxin_pmu_print_debug, };static const struct {int id;char *name; } zx_arch_events_map[]__initconst = {
Signature · 1 line
2.53.0
PATCH 3/3 perf/x86/amd: Implement x86_pmu::print_debug
In reply to Sandipan DasImplement x86_pmu::print_debug for PerfMonV2 capable processors to dump MSR_AMD64_PERF_CNTR_GLOBAL_{CTL,STATUS}, plus MSR_AMD_DBG_EXTN_CFG if LBR Extension Version 2 is available. Chain into x86_pmu_print_debug() afterwards to dump the event selectors and counters.
MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_{CLR,SET} are left out since they are write-only.
--- arch/x86/events/amd/core.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+)
arch/x86/events/amd/core.c +20 -0
@@ -841,6 +841,25 @@ static void amd_pmu_v2_disable_all(void)amd_pmu_check_overflow (); } +static void amd_pmu_v2_print_debug (int cpu) +{ +u64 ctrl, status, debugextn; + +rdmsrq (MSR_AMD64_PERF_CNTR_GLOBAL_CTL , ctrl); +rdmsrq (MSR_AMD64_PERF_CNTR_GLOBAL_STATUS , status); + +pr_info ("\n" ); +pr_info ("CPU#%d: ctrl: %016llx\n" , cpu, ctrl); +pr_info ("CPU#%d: status: %016llx\n" , cpu, status); + +if (cpu_feature_enabled (X86_FEATURE_AMD_LBR_V2 )) { +rdmsrq (MSR_AMD_DBG_EXTN_CFG , debugextn); +pr_info ("CPU#%d: debugextn: %016llx\n" , cpu, debugextn); + } + +x86_pmu_print_debug (cpu); +} +DEFINE_STATIC_CALL_NULL (amd_pmu_branch_add, *x86_pmu.add);static void amd_pmu_add_event (struct perf_event *event)
@@ -1452,6 +1471,7 @@ static int __init amd_core_pmu_init(void) x86_pmu.disable_all = amd_pmu_v2_disable_all; x86_pmu.enable = amd_pmu_v2_enable_event; x86_pmu.handle_irq = amd_pmu_v2_handle_irq; + x86_pmu.print_debug = amd_pmu_v2_print_debug;static_call_update (amd_pmu_test_overflow, amd_pmu_test_overflow_status); }
Signature · 1 line
2.53.0
Re: [PATCH 3/3] perf/x86/amd: Implement x86_pmu::print_debug
Quoted 5 lines · On Thu, 6 Aug 2026 15:33:28 +0530 Sandipan Das <[email protected]> wrote:
Implement
x86_pmu::print_debugfor PerfMonV2 capable processors to dump MSR_AMD64_PERF_CNTR_GLOBAL_{CTL,STATUS}, plusMSR_AMD_DBG_EXTN_CFGif LBR Extension Version 2 is available. Chain intox86_pmu_print_debug()afterwards to dump the event selectors and counters.
Quoted 8 lines
MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_{CLR,SET} are left out since they are write-only.
Fixes 21d59e3e2c40 ("perf/x86/amd/core: Detect PerfMonV2 support")Reported-by Petr Tesarik <[email protected]>Signed-off-by Sandipan Das <[email protected]>
This works great on my system, no more unchecked MSR access errors, and the logged values look correct. Feel free to add
Thank you!
Petr T
Quoted 42 lines
--- arch/x86/events/amd/core.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+)arch/x86/events/amd/core.c +20
-0@@ -841,6 +841,25 @@ static void amd_pmu_v2_disable_all(void)amd_pmu_check_overflow (); } +static void amd_pmu_v2_print_debug (int cpu) +{ +u64 ctrl, status, debugextn; + +rdmsrq (MSR_AMD64_PERF_CNTR_GLOBAL_CTL , ctrl); +rdmsrq (MSR_AMD64_PERF_CNTR_GLOBAL_STATUS , status); + +pr_info ("\n" ); +pr_info ("CPU#%d: ctrl: %016llx\n" , cpu, ctrl); +pr_info ("CPU#%d: status: %016llx\n" , cpu, status); + +if (cpu_feature_enabled (X86_FEATURE_AMD_LBR_V2 )) { +rdmsrq (MSR_AMD_DBG_EXTN_CFG , debugextn); +pr_info ("CPU#%d: debugextn: %016llx\n" , cpu, debugextn); + } + +x86_pmu_print_debug (cpu); +} +DEFINE_STATIC_CALL_NULL (amd_pmu_branch_add, *x86_pmu.add);static void amd_pmu_add_event (struct perf_event *event)@@ -1452,6 +1471,7 @@ static int __init amd_core_pmu_init(void) x86_pmu.disable_all = amd_pmu_v2_disable_all; x86_pmu.enable = amd_pmu_v2_enable_event; x86_pmu.handle_irq = amd_pmu_v2_handle_irq; + x86_pmu.print_debug = amd_pmu_v2_print_debug;static_call_update (amd_pmu_test_overflow, amd_pmu_test_overflow_status); }