ls1021aiot: Fix the boot on current main and enable FIT

These patches get the LS1021A-IoT board booting on current main and let it boot FIT images.

Tested on my board (rev 1.0 silicon), which also needs a local RCW change for the UART.

Changes in v2:
- Rebase on main. Only 4/6 conflicted, with commit 8ab9f25f7e39.

Mateus Lima Alves (6):
armv7: ls102xa: Apply erratum A-008850 on all LS1021A boards
armv7: ls102xa: Terminate CCI-400 barriers before cpu_init_cp15
configs: ls1021aiot_sdcard: Reserve 1 MiB for U-Boot in the SPL memory
map
configs: ls1021aiot: Enable FIT image support
configs: ls1021aiot: Allow 64 MiB decompressed OS images
board: nxp: ls1021aiot: Keep the IFC enabled in the OS device tree

 arch/arm/cpu/armv7/ls102xa/Kconfig  |  2 +-
 arch/arm/cpu/armv7/ls102xa/soc.c    |  3 ---
 arch/arm/cpu/armv7/start.S          |  6 ++++++
 board/nxp/ls1021aiot/ls1021aiot.c   | 16 ++++++++++++++++
 configs/ls1021aiot_qspi_defconfig   |  3 +++
 configs/ls1021aiot_sdcard_defconfig |  7 +++++--
 include/fsl_ddr_sdram.h             |  4 ----
 include/fsl_immap.h                 |  4 ++++
 8 files changed, 35 insertions(+), 10 deletions(-)

2.43.0

Commit f9147d636ce2 ("Convert CONFIG_CHIP_SELECTS_PER_CTRL to Kconfig") made SYS_FSL_ERRATUM_A008850 depend on SYS_FSL_DDR, since soc.c includes fsl_ddr_sdram.h for the DDR_EOR bits and that header needs CONFIG_CHIP_SELECTS_PER_CTRL. The ls1021aiot and ls1021atwr boards set up the DDR controller in ddrmc_init() and do not select SYS_FSL_DDR, so the workaround is silently compiled out there, even though both boards still call erratum_a008850_post() from dram_init().

Move the two DDR_EOR bits next to struct ccsr_ddr in fsl_immap.h, drop the fsl_ddr_sdram.h include from soc.c and select the erratum again for all LS1021A boards.

---
Cc: Tom Rini <[email protected]>
Cc: Peng Fan <[email protected]>
Cc: Alison Wang <[email protected]>

Changes in v2:
- Rebase on main, no other changes

---
 arch/arm/cpu/armv7/ls102xa/Kconfig | 2 +-
 arch/arm/cpu/armv7/ls102xa/soc.c   | 3 ---
 include/fsl_ddr_sdram.h            | 4 ----
 include/fsl_immap.h                | 4 ++++
 4 files changed, 5 insertions(+), 8 deletions(-)

index 9ce94555ed0..70170e735be 100644
@@ -9,7 +9,7 @@ config ARCH_LS1021A
 	select SYS_FSL_IFC_BE
 	select SYS_FSL_ERRATUM_A008378
 	select SYS_FSL_ERRATUM_A008407
-	select SYS_FSL_ERRATUM_A008850 if SYS_FSL_DDR
+	select SYS_FSL_ERRATUM_A008850
 	select SYS_FSL_ERRATUM_A008997 if USB
 	select SYS_FSL_ERRATUM_A009008 if USB
 	select SYS_FSL_ERRATUM_A009663

index 7ff59edd452..60f63da73f8 100644
@@ -12,9 +12,6 @@
 #include <asm/arch/ls102xa_soc.h>
 #include <asm/arch/ls102xa_stream_id.h>
 #include <fsl_csu.h>
-#ifdef CONFIG_SYS_FSL_ERRATUM_A008850
-#include <fsl_ddr_sdram.h>
-#endif
 
 struct liodn_id_table sec_liodn_tbl[] = {
 	SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10),

index 182f5836533..650bfc29b49 100644
@@ -146,10 +146,6 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t;
 #define WR_DATA_DELAY_SHIFT	10
 #endif
 
-/* DDR_EOR register */
-#define DDR_EOR_RD_REOD_DIS	0x07000000
-#define DDR_EOR_WD_REOD_DIS	0x00100000
-
 /* DDR_MD_CNTL */
 #define MD_CNTL_MD_EN		0x80000000
 #define MD_CNTL_CS_SEL_CS0	0x00000000

index 54d6e0ab377..759a484a926 100644
@@ -136,6 +136,10 @@ struct ccsr_ddr {
 	u32     debug[64];		/* debug_1 to debug_64 */
 };
 
+/* DDR_EOR register */
+#define DDR_EOR_RD_REOD_DIS	0x07000000
+#define DDR_EOR_WD_REOD_DIS	0x00100000
+
 #ifdef CONFIG_SYS_FSL_HAS_CCI400
 #define CCI400_CTRLORD_TERM_BARRIER	0x00000008
 #define CCI400_CTRLORD_EN_BARRIER	0

2.43.0

On LS1021A rev 1.0 the DDR controller does not respond to the barrier transactions that the CCI-400 forwards before the DDR is initialized. The first DSB in cpu_init_cp15 then never completes and the SPL hangs before printing anything. The A-008850 workaround terminates the barriers in arch_soc_init(), which runs after that DSB.

Terminate the barrier transactions in the CCI-400 Control Override register right after VBAR is set, as done in the Layerscape SDK by commit da25dce4aac5 ("arm: ls102xa: Add workaround for Barrier Transaction issue") in LS1021A-SDK-V1.3. erratum_a008850_post() enables them again once the DDR is up.

Tested on an LS1021A-IoT board with rev 1.0 silicon (SVR 0x87081110):
without this change the SPL is silent from power-on; with it the board boots Linux from cold and warm reset, and 0x01180000 reads 0 after DDR init.

---
Cc: Tom Rini <[email protected]>
Cc: Peng Fan <[email protected]>
Cc: Alison Wang <[email protected]>

Changes in v2:
- Rebase on main, no other changes

---
 arch/arm/cpu/armv7/start.S | 6 ++++++
 1 file changed, 6 insertions(+)

index 833486817f8..b7c883cab91 100644
@@ -114,6 +114,12 @@ switch_to_hypervisor_ret:
 #endif
 #endif
 
+#ifdef CONFIG_ARCH_LS1021A
+	ldr r1, =0x01180000
+	mov r2, #0x00000008
+	str r2, [r1]
+#endif
+
 	/* the mask ROM code should have PLL and others stable */
 #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
 #ifdef CONFIG_CPU_V7A

2.43.0

As more features were added, U-Boot for the LS1021A-IoT board grew beyond the 512 KiB that CONFIG_SYS_MONITOR_LEN reserves for it:
u-boot.bin for ls1021aiot_sdcard_defconfig is 604 KiB on v2026.07. The SPL malloc pool starts right after that space, at 0x82080000, so loading U-Boot to 0x82000000 overwrites the pool, including the struct mmc used for the load, and the SPL takes a data abort after "Trying to boot from MMC1".

Reserve 1 MiB for U-Boot and start the SPL malloc pool right after it, at 0x82100000, as the LS1021A-TWR and LS1021A-TSN boards do. The same adjustment was made for the LS1021A-QDS board in commit 7ee52af455c2 ("ls102xa: Adjust some macros for SD boot on LS1021A QDS board") and for the LS1021A-TWR board in commit 9b6639fa85bd ("LS1021ATWR: Modify u-boot size for sd secure boot").

---
Cc: Tom Rini <[email protected]>
Cc: Peng Fan <[email protected]>
Cc: Alison Wang <[email protected]>

Changes in v2:
- Rebase on main, no other changes

---
 configs/ls1021aiot_sdcard_defconfig | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

index 6327ca61d86..1fb8f7b0f6a 100644
@@ -13,7 +13,7 @@ CONFIG_SYS_I2C_MXC_I2C2=y
 CONFIG_SYS_I2C_MXC_I2C3=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-iot-duart"
-CONFIG_SYS_MONITOR_LEN=524288
+CONFIG_SYS_MONITOR_LEN=1048576
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK=0x1001d000

@@ -49,7 +49,7 @@ CONFIG_SPL_PAD_TO=0x1c000
 CONFIG_SPL_FSL_PBL=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
-CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x82080000
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x82100000
 CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
 CONFIG_SPL_ENV_SUPPORT=y

2.43.0

Commit 397b0d9e2971 ("arm: ls1021a: Enable CONFIG_OF_LIBFDT and CONFIG_FIT in defconfig") enabled FIT support for the LS1021A boards, but the LS1021A-IoT board was added later, in commit 20c700f8daee ("armv7: Add support of ls1021a-iot board"), without it. It is now the only LS1021A board that cannot boot a FIT image: bootm stops with "Wrong Image Type for bootm command".

Distributions ship FIT images for this board: the OpenWrt fsl_ls1021a-iot-sdboot images are a FIT with the kernel and its device tree. Enable FIT, with FIT_VERBOSE as on the LS1021A-TWR, for both the SD card and QSPI configurations.

---
Cc: Tom Rini <[email protected]>
Cc: Peng Fan <[email protected]>
Cc: Alison Wang <[email protected]>

Changes in v2:
- Rebase on main, resolving the conflict with commit 8ab9f25f7e39 ("configs: ls1021aiot_sdcard: Limit the U-Boot image to 1 MiB")

---
 configs/ls1021aiot_qspi_defconfig   | 2 ++
 configs/ls1021aiot_sdcard_defconfig | 2 ++
 2 files changed, 4 insertions(+)

index 7a301138f1b..00346509706 100644
@@ -18,6 +18,8 @@ CONFIG_PCI=y
 CONFIG_LAYERSCAPE_NS_ACCESS=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
 CONFIG_QSPI_BOOT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y

index 1fb8f7b0f6a..c574e7c6b29 100644
@@ -32,6 +32,8 @@ CONFIG_PCIE1=y
 CONFIG_PCIE2=y
 CONFIG_HAS_BOARD_SIZE_LIMIT=y
 CONFIG_BOARD_SIZE_LIMIT=1048576
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
 CONFIG_RAMBOOT_PBL=y
 CONFIG_SYS_FSL_PBL_PBI="board/nxp/ls1021aiot/ls102xa_pbi.cfg"
 CONFIG_SYS_FSL_PBL_RCW="board/nxp/ls1021aiot/ls102xa_rcw_sd.cfg"

2.43.0

Commit cc7b8b9abb1d ("armv7: ls102xa: Increase the supported kernel size") raised the maximum size of a decompressed OS image to 64 MiB for the LS1021A boards, but the LS1021A-IoT board was added later, in commit 20c700f8daee ("armv7: Add support of ls1021a-iot board"), and kept the 8 MiB default. Its kernels outgrow it: an OpenWrt initramfs FIT image holds a 16 MiB kernel, and bootm stops with "Error: inflate() returned -5".

Set CONFIG_SYS_BOOTM_LEN to 64 MiB, as on the other LS1021A boards, for both the SD card and QSPI configurations.

---
Cc: Tom Rini <[email protected]>
Cc: Peng Fan <[email protected]>
Cc: Alison Wang <[email protected]>

Changes in v2:
- Rebase on main, no other changes

---
 configs/ls1021aiot_qspi_defconfig   | 1 +
 configs/ls1021aiot_sdcard_defconfig | 1 +
 2 files changed, 2 insertions(+)

index 00346509706..8f01b649ea7 100644
@@ -12,6 +12,7 @@ CONFIG_SYS_I2C_MXC_I2C2=y
 CONFIG_SYS_I2C_MXC_I2C3=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-iot-duart"
+CONFIG_SYS_BOOTM_LEN=0x4000000
 CONFIG_SYS_LOAD_ADDR=0x82000000
 CONFIG_PCI=y
 # CONFIG_DEEP_SLEEP is not set

index c574e7c6b29..6d5bbbfd2f9 100644
@@ -21,6 +21,7 @@ CONFIG_SPL_TEXT_BASE=0x10000000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x80100000
 CONFIG_SPL_BSS_MAX_SIZE=0x80000
+CONFIG_SYS_BOOTM_LEN=0x4000000
 CONFIG_SYS_LOAD_ADDR=0x82000000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_HAVE_INIT_STACK=y

2.43.0

ft_cpu_setup() disables the IFC node of the OS device tree when U-Boot boots with QSPI enabled (CONFIG_SD_BOOT_QSPI or CONFIG_QSPI_BOOT), since the IFC and the QSPI share pins on most LS1021A boards. Both ls1021aiot configurations enable QSPI, so Linux never sees the IFC on this board, although its system CPLD sits on IFC chip select 0 and works alongside the QSPI flash.

Keep the IFC enabled when the device tree passed to the OS enables it, so the CPLD driver can bind; a device tree that leaves it disabled is not changed.

---
Cc: Tom Rini <[email protected]>
Cc: Peng Fan <[email protected]>
Cc: Alison Wang <[email protected]>

Changes in v2:
- Rebase on main, no other changes

---
 board/nxp/ls1021aiot/ls1021aiot.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

index 52a3c3abdb4..66f7ca659a0 100644
@@ -7,6 +7,7 @@
 #include <config.h>
 #include <clock_legacy.h>
 #include <fdt_support.h>
+#include <fdtdec.h>
 #include <init.h>
 #include <net.h>
 #include <asm/arch/immap_ls102xa.h>

@@ -183,8 +184,23 @@ int misc_init_r(void)
 
 int ft_board_setup(void *blob, struct bd_info *bd)
 {
+	int off = fdt_node_offset_by_compat_reg(blob, FSL_IFC_COMPAT,
+						CFG_SYS_IFC_ADDR);
+	bool ifc_enabled = off >= 0 && fdtdec_get_is_enabled(blob, off);
+
 	ft_cpu_setup(blob, bd);
 
+	/*
+	 * ft_cpu_setup() disables the IFC when booting with QSPI, but on this
+	 * board the system CPLD on IFC CS0 works alongside QSPI. Keep the IFC
+	 * enabled when the device tree enables it.
+	 */
+	if (ifc_enabled) {
+		off = fdt_node_offset_by_compat_reg(blob, FSL_IFC_COMPAT,
+						    CFG_SYS_IFC_ADDR);
+		fdt_set_node_status(blob, off, FDT_STATUS_OKAY);
+	}
+
 #ifdef CONFIG_PCI
 	ft_pci_setup(blob, bd);
 #endif

2.43.0