H8/300 support update (2/4)

diff -u -r1.1.1.1 -r1.2
@@ -101,7 +101,4 @@
 #define smp_mb__before_atomic_inc()    barrier()
 #define smp_mb__after_atomic_inc() barrier()
 
-#define atomic_sub_and_test(i,v) (atomic_sub_return((i), (v)) == 0)
-#define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0)
-
 #endif /* __ARCH_H8300_ATOMIC __ */

95 lines not on this page · raw message

diff -u -r1.1.1.1 -r1.2
@@ -49,4 +49,11 @@
 #define pgtable_cache_init()   do { } while (0)
 #define io_remap_page_range	remap_page_range
 
+/*
+ * All 32bit addresses are effectively valid for vmalloc...
+ * Sort of meaningless for non-VM targets.
+ */
+#define	VMALLOC_START	0
+#define	VMALLOC_END	0xffffffff
+
 #endif /* _H8300_PGTABLE_H */

diff -u -r1.1.1.1 -r1.2
@@ -52,17 +52,16 @@
 #define MCA_bus 0
 
 struct thread_struct {
-	unsigned long  ksp;		/* kernel stack pointer */
-	unsigned long  usp;		/* user stack pointer */
-	unsigned short ccr;		/* saved status register */
-	unsigned long  esp0;            /* points to SR of stack frame */
-	unsigned long  vfork_ret;
-	unsigned long  debugreg[8];     /* debug info */
-} __attribute__((aligned(2),packed));
+	unsigned long ksp;		/* kernel stack pointer */
+	unsigned long usp;		/* user stack pointer */
+	unsigned long ccr;		/* saved status register */
+	unsigned long esp0;             /* points to SR of stack frame */
+	unsigned long debugreg[8];      /* debug info */
+};
 
 #define INIT_THREAD  { \
 	sizeof(init_stack) + (unsigned long) init_stack, 0, \
-	PS_S,  0, 0, \
+	PS_S, \
 }
 
 /*

@@ -73,9 +72,9 @@
  */
 #define start_thread(_regs, _pc, _usp)			        \
 do {							        \
+	set_fs(USER_DS);           /* reads from user space */  \
 	(_regs)->pc = (_pc);				        \
 	(_regs)->ccr &= ~0x10;				        \
-        *((unsigned long *)(_usp)-1) = _pc;                     \
 	wrusp((unsigned long)(_usp) - sizeof(unsigned long)*3);	\
 } while(0)
 

diff -u -r1.1.1.1 -r1.2
@@ -19,6 +19,10 @@
    stack during a system call. */
 
 struct pt_regs {
+	long     retpc;
+	long     er4;
+	long     er5;
+	long     er6;
 	long     er3;
 	long     er2;
 	long     er1;

@@ -26,19 +30,11 @@
 	unsigned short ccr;
 	long     er0;
 	long     vector;
+#if defined(CONFIG_CPU_H8S)
+	unsigned short exr;
+#endif
 	unsigned long  pc;
 } __attribute__((aligned(2),packed));
-
-/*
- * This is the extended stack used by signal handlers and the context
- * switcher: it's pushed after the normal "struct pt_regs".
- */
-struct switch_stack {
-	unsigned long  er6;
-	unsigned long  er5;
-	unsigned long  er4;
-	unsigned long  retpc;
-};
 
 #define PTRACE_GETREGS            12
 #define PTRACE_SETREGS            13

diff -u -r1.1.1.1 -r1.3
@@ -36,17 +36,20 @@
  * H8/300 Porting 2002/09/04 Yoshinori Sato
  */
 asmlinkage void resume(void);
-#define switch_to(prev,next,last) { \
-  void *_last;								        \
-  __asm__ __volatile__(								\
-  			"mov.l	%1, er0\n\t"					\
-			"mov.l	%2, er1\n\t"					\
-			"jsr @_resume"                                          \
-		       : "=r" (_last)						\
-		       : "r" (&(prev->thread)),				        \
-			 "r" (&(next->thread))				        \
-		       : "cc", "er0", "er1", "er2", "er3");	                \
-  (last) = _last; 								\
+#define switch_to(prev,next,last) {                         \
+  void *_last;						    \
+  __asm__ __volatile__(					    \
+  			"mov.l	%1, er0\n\t"		    \
+			"mov.l	%2, er1\n\t"		    \
+                        "mov.l  %3, er2\n\t"                \
+			"jsr @_resume\n\t"                  \
+                        "mov.l  er2,%0\n\t"                 \
+		       : "=r" (_last)			    \
+		       : "r" (&(prev->thread)),		    \
+			 "r" (&(next->thread)),		    \
+                         "g" (prev)                         \
+		       : "cc", "er0", "er1", "er2", "er3"); \
+  (last) = _last; 					    \
 }
 
 #if defined(__H8300H__)

@@ -80,15 +83,15 @@
 #define iret() __asm__ __volatile__ ("rte": : :"memory", "sp", "cc")
 
 /* For spinlocks etc */
-#define local_irq_disable()	asm volatile ("orc  #0x80,ccr")
-#define local_irq_enable()      asm volatile ("andc #0x7f,ccr")
+#define local_irq_disable()	__cli()
+#define local_irq_enable()      __sti()
 #define local_irq_save(x)	({ __save_flags(x); local_irq_disable(); })
 #define local_irq_restore(x)	__restore_flags(x)
 #define local_save_flags(x)     __save_flags(x)
 
 /*
  * Force strict CPU ordering.
- * Not really required on m68k...
+ * Not really required on H8...
  */
 #define nop()  asm volatile ("nop"::)
 #define mb()   asm volatile (""   : : :"memory")

diff -u -r1.1.1.1 -r1.2
@@ -405,8 +405,39 @@
 			  "g" ((long)b),					\
 			  "g" ((long)c),					\
 			  "g" ((long)d),					\
-			  "g" ((long)e)						\
-			: "cc", "er1", "er2", "er3", "er4");			\
+			  "m" ((long)e)						\
+			: "cc", "er1", "er2", "er3", "er4", "er5");		\
+  if ((unsigned long)(__res) >= (unsigned long)(-125)) {		       	\
+    errno = -__res;								\
+    __res = -1;									\
+  }										\
+  return (type)__res;								\
+}
+		
+#define _syscall6(type, name, atype, a, btype, b, ctype, c, dtype, d,           \
+                              etype, e, ftype, f)	                        \
+type name(atype a, btype b, ctype c, dtype d, etype e, ftype f)			\
+{										\
+  register long __res __asm__("er0");						\
+  __asm__ __volatile__ ("mov.l	er6,@-sp\n\t"					\
+                        "mov.l	%7, er6\n\t"					\
+                        "mov.l	%6, er5\n\t"					\
+			"mov.l	%5, er4\n\t"					\
+			"mov.l	%4, er3\n\t"					\
+			"mov.l	%3, er2\n\t"					\
+  			"mov.l	%2, er1\n\t"					\
+			"mov.l	%1, er0\n\t"					\
+  			"trapa	#0\n\t"						\
+  			"mov.l	@sp+,er6"					\
+			: "=r" (__res)						\
+			: "ir" (__NR_##name),					\
+			  "g" ((long)a),					\
+			  "g" ((long)b),					\
+			  "g" ((long)c),					\
+			  "g" ((long)d),					\
+			  "m" ((long)e),					\
+			  "m" ((long)e)						\
+			: "cc", "er1", "er2", "er3", "er4", "er5");		\
   if ((unsigned long)(__res) >= (unsigned long)(-125)) {		       	\
     errno = -__res;								\
     __res = -1;									\