dev Digest, Vol 180, Issue 152
A message that is not in the archive (sent off-list or not yet received): [email protected]
Hi Beilei,
I was looking at the patches and have few queries regarding support-multi-driver.
1) With these patches, we have 2 different values for some of the global registers depending upon whether single driver or multi-driver is using all ports of the NIC. Does it impact any functionality/performance if we use DPDK drivers in single driver vs multi-driver support?
2) Why can't we have same settings for both the cases? That way we don't have to care for extra parameter.
3) Does this issue need any update for kernel driver also?
Regards,
Nitin
-----Original Message-----
From: dev [mailto:[email protected]] On Behalf Of [email protected]
Sent: Friday, February 02, 2018 5:55 PM
To: [email protected]
Subject: dev Digest, Vol 180, Issue 152
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Today's Topics:
1. [PATCH v3 2/4] net/i40e: add debug logs when writing global
registers (Beilei Xing)
2. [PATCH v3 3/4] net/i40e: fix multiple driver support issue
(Beilei Xing)
3. [PATCH v3 4/4] net/i40e: fix interrupt conflict when using
multi-driver (Beilei Xing)
----------------------------------------------------------------------
Message: 1
Date: Fri, 2 Feb 2018 20:25:08 +0800
From: Beilei Xing <[email protected]>
To: [email protected], [email protected]
Cc: [email protected]
Subject: [dpdk-dev] [PATCH v3 2/4] net/i40e: add debug logs when
writing global registers
Message-ID: <[email protected]>
Add debug logs when writing global registers.
--- drivers/net/i40e/i40e_ethdev.c | 127 +++++++++++++++++++++++++---------------- drivers/net/i40e/i40e_ethdev.h | 8 +++ 2 files changed, 87 insertions(+), 48 deletions(-)
drivers/net/i40e/i40e_ethdev.c +51 -25
@@ -716,6 +716,15 @@ rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,return 0 ; } +static inline void +i40e_write_global_rx_ctl (struct i40e_hw *hw,u32 reg_addr,u32 reg_val) +{ +i40e_write_rx_ctl (hw, reg_addr, reg_val); +PMD_DRV_LOG (DEBUG ,"Global register 0x%08x is modified " +"with value 0x%08x" , + reg_addr, reg_val); +} +RTE_PMD_REGISTER_PCI (net_i40e, rte_i40e_pmd.pci_drv);RTE_PMD_REGISTER_PCI_TABLE (net_i40e, pci_id_i40e_map);
@@ -735,9 +744,9 @@ static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)* configuration API is added to avoid configuration conflicts * between ports of the same device. */ -I40E_WRITE_REG (hw,I40E_GLQF_ORT (33 ),0x000000E0 ); -I40E_WRITE_REG (hw,I40E_GLQF_ORT (34 ),0x000000E3 ); -I40E_WRITE_REG (hw,I40E_GLQF_ORT (35 ),0x000000E6 ); +I40E_WRITE_GLB_REG (hw,I40E_GLQF_ORT (33 ),0x000000E0 ); +I40E_WRITE_GLB_REG (hw,I40E_GLQF_ORT (34 ),0x000000E3 ); +I40E_WRITE_GLB_REG (hw,I40E_GLQF_ORT (35 ),0x000000E6 );i40e_global_cfg_warning (I40E_WARNING_ENA_FLX_PLD );/*
@@ -746,8 +755,8 @@ static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)* configuration API is added to avoid configuration conflicts * between ports of the same device. */ -I40E_WRITE_REG (hw,I40E_GLQF_ORT (40 ),0x00000029 ); -I40E_WRITE_REG (hw,I40E_GLQF_PIT (9 ),0x00009420 ); +I40E_WRITE_GLB_REG (hw,I40E_GLQF_ORT (40 ),0x00000029 ); +I40E_WRITE_GLB_REG (hw,I40E_GLQF_PIT (9 ),0x00009420 );i40e_global_cfg_warning (I40E_WARNING_QINQ_PARSER ); }
@@ -2799,8 +2808,9 @@ i40e_vlan_tpid_set(struct rte_eth_dev *dev, "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);return ret; } -PMD_DRV_LOG (DEBUG ,"Debug write 0x%08" PRIx64" to " -"I40E_GL_SWT_L2TAGCTRL[%d]" , reg_w, reg_id); +PMD_DRV_LOG (DEBUG , +"Global register 0x%08x is changed with value 0x%08x" , +I40E_GL_SWT_L2TAGCTRL (reg_id), (uint32_t )reg_w);i40e_global_cfg_warning (I40E_WARNING_TPID );
@@ -3030,16 +3040,16 @@ i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) }/* config the water marker both based on the packets and bytes */ -I40E_WRITE_REG (hw,I40E_GLRPB_PHW , +I40E_WRITE_GLB_REG (hw,I40E_GLRPB_PHW , (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS ] <<I40E_KILOSHIFT ) /I40E_PACKET_AVERAGE_SIZE ); -I40E_WRITE_REG (hw,I40E_GLRPB_PLW , +I40E_WRITE_GLB_REG (hw,I40E_GLRPB_PLW , (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS ] <<I40E_KILOSHIFT ) /I40E_PACKET_AVERAGE_SIZE ); -I40E_WRITE_REG (hw,I40E_GLRPB_GHW , +I40E_WRITE_GLB_REG (hw,I40E_GLRPB_GHW , pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS ] <<I40E_KILOSHIFT ); -I40E_WRITE_REG (hw,I40E_GLRPB_GLW , +I40E_WRITE_GLB_REG (hw,I40E_GLRPB_GLW , pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS ] <<I40E_KILOSHIFT );i40e_global_cfg_warning (I40E_WARNING_FLOW_CTL );
@@ -6880,6 +6890,9 @@ i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len) reg, NULL);if (ret !=0 )return ret; +PMD_DRV_LOG (DEBUG ,"Global register 0x%08x is changed " +"with value 0x%08x" , +I40E_GL_PRS_FVBM (2 ), reg);i40e_global_cfg_warning (I40E_WARNING_GRE_KEY_LEN ); }else { ret =0 ;
@@ -7124,41 +7137,43 @@ i40e_set_hash_filter_global_config(struct i40e_hw *hw, I40E_GLQF_HSYM_SYMH_ENA_MASK :0 ;if (hw->mac.type ==I40E_MAC_X722 ) {if (pctype ==I40E_FILTER_PCTYPE_NONF_IPV4_UDP ) { -i40e_write_rx_ctl (hw,I40E_GLQF_HSYM ( +i40e_write_global_rx_ctl (hw,I40E_GLQF_HSYM (I40E_FILTER_PCTYPE_NONF_IPV4_UDP ), reg); -i40e_write_rx_ctl (hw,I40E_GLQF_HSYM ( +i40e_write_global_rx_ctl (hw,I40E_GLQF_HSYM (I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP ), reg); -i40e_write_rx_ctl (hw,I40E_GLQF_HSYM ( +i40e_write_global_rx_ctl (hw,I40E_GLQF_HSYM (I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP ), reg); }else if (pctype ==I40E_FILTER_PCTYPE_NONF_IPV4_TCP ) { -i40e_write_rx_ctl (hw,I40E_GLQF_HSYM ( +i40e_write_global_rx_ctl (hw,I40E_GLQF_HSYM (I40E_FILTER_PCTYPE_NONF_IPV4_TCP ), reg); -i40e_write_rx_ctl (hw,I40E_GLQF_HSYM ( +i40e_write_global_rx_ctl (hw,I40E_GLQF_HSYM (I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK ), reg); }else if (pctype ==I40E_FILTER_PCTYPE_NONF_IPV6_UDP ) { -i40e_write_rx_ctl (hw,I40E_GLQF_HSYM ( +i40e_write_global_rx_ctl (hw,I40E_GLQF_HSYM (I40E_FILTER_PCTYPE_NONF_IPV6_UDP ), reg); -i40e_write_rx_ctl (hw,I40E_GLQF_HSYM ( +i40e_write_global_rx_ctl (hw,I40E_GLQF_HSYM (I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP ), reg); -i40e_write_rx_ctl (hw,I40E_GLQF_HSYM ( +i40e_write_global_rx_ctl (hw,I40E_GLQF_HSYM (I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP ), reg); }else if (pctype ==I40E_FILTER_PCTYPE_NONF_IPV6_TCP ) { -i40e_write_rx_ctl (hw,I40E_GLQF_HSYM ( +i40e_write_global_rx_ctl (hw,I40E_GLQF_HSYM (I40E_FILTER_PCTYPE_NONF_IPV6_TCP ), reg); -i40e_write_rx_ctl (hw,I40E_GLQF_HSYM ( +i40e_write_global_rx_ctl (hw,I40E_GLQF_HSYM (I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK ), reg); }else { -i40e_write_rx_ctl (hw,I40E_GLQF_HSYM (pctype), - reg); +i40e_write_global_rx_ctl (hw, +I40E_GLQF_HSYM (pctype), + reg); } }else { -i40e_write_rx_ctl (hw,I40E_GLQF_HSYM (pctype), reg); +i40e_write_global_rx_ctl (hw,I40E_GLQF_HSYM (pctype), + reg); }i40e_global_cfg_warning (I40E_WARNING_HSYM ); }
@@ -7184,7 +7199,7 @@ i40e_set_hash_filter_global_config(struct i40e_hw *hw,/* Use the default, and keep it as it is */ goto out; -i40e_write_rx_ctl (hw,I40E_GLQF_CTL , reg); +i40e_write_global_rx_ctl (hw,I40E_GLQF_CTL , reg);i40e_global_cfg_warning (I40E_WARNING_QF_CTL ); out:
@@ -7799,6 +7814,18 @@ i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val) }static void +i40e_check_write_global_reg (struct i40e_hw *hw,uint32_t addr,uint32_t +val) { +uint32_t reg =i40e_read_rx_ctl (hw, addr); + +PMD_DRV_LOG (DEBUG ,"[0x%08x] original: 0x%08x" , addr, reg); +if (reg != val) +i40e_write_global_rx_ctl (hw, addr, val); +PMD_DRV_LOG (DEBUG ,"[0x%08x] after: 0x%08x" , addr, + (uint32_t )i40e_read_rx_ctl (hw, addr)); } + +static void i40e_filter_input_set_init (struct i40e_pf *pf) { struct i40e_hw *hw = I40E_PF_TO_HW(pf); @@ -7831,24 +7858,28 @@ i40e_filter_input_set_init(struct i40e_pf *pf) i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1), (uint32_t)((inset_reg >>
I40E_32_BIT_WIDTH) & UINT32_MAX));
- i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
+ i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
(uint32_t)(inset_reg & UINT32_MAX));
- i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
+ i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
(uint32_t)((inset_reg >> I40E_32_BIT_WIDTH) & UINT32_MAX));
for (i = 0; i < num; i++) {
- i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
- mask_reg[i]);
- i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
- mask_reg[i]);
+ i40e_check_write_global_reg(hw,
+ I40E_GLQF_FD_MSK(i, pctype),
+ mask_reg[i]);
+ i40e_check_write_global_reg(hw,
+ I40E_GLQF_HASH_MSK(i, pctype),
+ mask_reg[i]);
}
/*clear unused mask registers of the pctype */ for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
- i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
- 0);
- i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
- 0);
+ i40e_check_write_global_reg(hw,
+ I40E_GLQF_FD_MSK(i, pctype),
+ 0);
+ i40e_check_write_global_reg(hw,
+ I40E_GLQF_HASH_MSK(i, pctype),
+ 0);
}
I40E_WRITE_FLUSH(hw);
@@ -7920,20 +7951,20 @@ i40e_hash_filter_inset_select(struct i40e_hw *hw,
inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
- i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
- (uint32_t)(inset_reg & UINT32_MAX));
- i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
- (uint32_t)((inset_reg >>
- I40E_32_BIT_WIDTH) & UINT32_MAX));
+ i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
+ (uint32_t)(inset_reg & UINT32_MAX));
+ i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
+ (uint32_t)((inset_reg >>
+ I40E_32_BIT_WIDTH) & UINT32_MAX));
i40e_global_cfg_warning(I40E_WARNING_HASH_INSET);
for (i = 0; i < num; i++)
- i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
- mask_reg[i]);
+ i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
+ mask_reg[i]);
/*clear unused mask registers of the pctype */ for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
- i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
- 0);
+ i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
+ 0);
i40e_global_cfg_warning(I40E_WARNING_HASH_MSK); I40E_WRITE_FLUSH(hw);
@@ -8007,12 +8038,12 @@ i40e_fdir_filter_inset_select(struct i40e_pf *pf,
I40E_32_BIT_WIDTH) & UINT32_MAX));
for (i = 0; i < num; i++)
- i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
- mask_reg[i]);
+ i40e_check_write_global_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
+ mask_reg[i]);
/*clear unused mask registers of the pctype */ for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
- i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
- 0);
+ i40e_check_write_global_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
+ 0);
i40e_global_cfg_warning(I40E_WARNING_FD_MSK); I40E_WRITE_FLUSH(hw);
drivers/net/i40e/i40e_ethdev.h +8 -0
@@ -103,6 +103,14 @@ (((vf)->version_major ==I40E_VIRTCHNL_VERSION_MAJOR ) && \ ((vf)->version_minor == 1)) +static inline void +I40E_WRITE_GLB_REG (struct i40e_hw *hw,uint32_t reg,uint32_t value) { +I40E_WRITE_REG (hw, reg, value); +PMD_DRV_LOG (DEBUG ,"Global register 0x%08x is modified " +"with value 0x%08x" , + reg, value); +} +/* index flex payload per layer */ enum i40e_flxpld_layer_idx {I40E_FLXPLD_L2_IDX =0 ,
--
2.5.5
------------------------------
Message: 2
Date: Fri, 2 Feb 2018 20:25:09 +0800
From: Beilei Xing <[email protected]>
To: [email protected], [email protected]
Cc: [email protected]
Subject: [dpdk-dev] [PATCH v3 3/4] net/i40e: fix multiple driver
support issue
Message-ID: <[email protected]>
This patch provides the option to disable writing some global registers in PMD, in order to avoid affecting other drivers, when multiple drivers run on the same NIC and control different physical ports. Because there are few global resources shared among different physical ports.
--- drivers/net/i40e/i40e_ethdev.c | 215 ++++++++++++++++++++++++++++++++--------- drivers/net/i40e/i40e_ethdev.h | 2 + 2 files changed, 171 insertions(+), 46 deletions(-)
drivers/net/i40e/i40e_ethdev.c +169 -46
322 lines not on this page · raw message
drivers/net/i40e/i40e_ethdev.h +2 -0
@@ -485,6 +485,8 @@ struct i40e_pf {bool floating_veb;/* The flag to use the floating VEB */ /* The floating enable flag for the specific VF */ bool floating_veb_list[I40E_MAX_VF ]; + +bool support_multi_driver;/* 1 - support multiple driver */ };enum pending_msg {
Signature · 29 lines
2.5.5 ------------------------------ Message: 3 Date: Fri, 2 Feb 2018 20:25:10 +0800 From: Beilei Xing <[email protected]> To: [email protected], [email protected] Cc: [email protected] Subject: [dpdk-dev] [PATCH v3 4/4] net/i40e: fix interrupt conflict when using multi-driver Message-ID: <[email protected]> There's interrupt conflict when using DPDK and Linux i40e on different ports of the same Ethernet controller, this patch fixes it by switching from IntN to Int0 if multiple drivers are used. Fixes: be6c228d4da3 ("i40e: support Rx interrupt") Cc: [email protected] Signed-off-by: Beilei Xing <[email protected]> --- drivers/net/i40e/i40e_ethdev.c | 93 +++++++++++++++++++++++++-------------- drivers/net/i40e/i40e_ethdev.h | 10 +++-- drivers/net/i40e/i40e_ethdev_vf.c | 4 +- 3 files changed, 68 insertions(+), 39 deletions(-)
drivers/net/i40e/i40e_ethdev.c +59 -34
180 lines not on this page · raw message
drivers/net/i40e/i40e_ethdev.h +7 -3
@@ -720,10 +720,14 @@ i40e_align_floor(int n) }static inline uint16_t -i40e_calc_itr_interval (int16_t interval) +i40e_calc_itr_interval (int16_t interval,bool is_multi_drv) { -if (interval <0 || interval >I40E_QUEUE_ITR_INTERVAL_MAX ) - interval =I40E_QUEUE_ITR_INTERVAL_DEFAULT ; +if (interval <0 || interval >I40E_QUEUE_ITR_INTERVAL_MAX ) { +if (is_multi_drv) + interval =I40E_QUEUE_ITR_INTERVAL_MAX ; +else + interval =I40E_QUEUE_ITR_INTERVAL_DEFAULT ; + }/* Convert to hardware count, as writing each 1 represents 2 us */ return interval /2 ;
drivers/net/i40e/i40e_ethdev_vf.c +2 -2
@@ -1246,7 +1246,7 @@ i40evf_init_vf(struct rte_eth_dev *dev)struct i40e_vf *vf =I40EVF_DEV_PRIVATE_TO_VF (dev->data->dev_private);struct ether_addr *p_mac_addr;uint16_t interval = -i40e_calc_itr_interval (I40E_QUEUE_ITR_INTERVAL_MAX ); +i40e_calc_itr_interval (I40E_QUEUE_ITR_INTERVAL_MAX ,0 ); vf->adapter =I40E_DEV_PRIVATE_TO_ADAPTER (dev->data->dev_private); vf->dev_data = dev->data;
@@ -1986,7 +1986,7 @@ i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;struct i40e_hw *hw =I40E_DEV_PRIVATE_TO_HW (dev->data->dev_private);uint16_t interval = -i40e_calc_itr_interval (RTE_LIBRTE_I40E_ITR_INTERVAL ); +i40e_calc_itr_interval (RTE_LIBRTE_I40E_ITR_INTERVAL ,0 );uint16_t msix_intr; msix_intr = intr_handle->intr_vec[queue_id];
Signature · 6 lines
2.5.5 End of dev Digest, Vol 180, Issue 152 *************************************