Q: stack coherency

Can I access a structure that's stored on the stack of one CPU from another CPU? I'm just noisy because I always did that [e.g SysV message code ipc/msg.c], and now a friend asked me if that's true for all cpu architecures.

CPU1:
- initialize linked list element [local variable]
- spin_lock
- add to linked list
- spin_unlock
- ...

CPU2:
- spin_lock
- walk the linked list
- spin_unlock.

--
Manfred

Manfred> Can I access a structure that's stored on the stack of one Manfred> CPU from another CPU?

IA-64 is no different in this respect from other architectures. If you have an SMP/NUMA/whatever system where the CPUs share the address-space, you will be able to access the stack of another thread (assuming the thread's stack is mapped in the address space). Of course, you also need to have proper synchronization to ensure the stack is still live when the second CPU is trying to access it.

I'm not 100% sure what you're asking though, because the "subject" line of your mail asks about stack coherency. Coherency is an orthogonal issue to accessibility. IA-64 uses a weakly ordered memory model to achieve high performance. It's probably best to read the IA-64 architecture manual for the details (see Section 4.4 at
http://devresource.hp.com/devresource/Docs/Refs/IA64ISA/), but loosely speaking, memory accesses that happen between a spin-lock/-unlock pair, will be ordered with respect to accesses by other CPUs.

	--david