4 SGI patches - non-identity mapped kernel + misc fixes
Bjorn -
Attached are 4 patches for the SGI platform. These are against the latest 2.4 bitkeeper tree.
The patches:
linux/arch/ia64/config.in
- delete some remnents of support for the SGI SN1 platform
- add config option for SN2.
linux_base/arch/ia64/kernel/Makefile
- fix compile error (SN2 needs iosapic.o)
linux/arch/ia64/acpi.c
- update acpi.c to recognize the SN2 platform
linux/arch/ia64/kernel/efi_stub.S linux/arch/ia64/kernel/head.S linux/arch/ia64/kernel/pal.S
- backport of 2.6 "ia64_switch_mode" changes for non-identity mapped kernels
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linux/arch/ia64/config.in | 12 +----- linux/arch/ia64/kernel/Makefile | 1 linux/arch/ia64/kernel/acpi.c | 5 +- linux/arch/ia64/kernel/efi_stub.S | 4 +- linux/arch/ia64/kernel/head.S | 74 +++++++++++++++++++++++++++++++------- linux/arch/ia64/kernel/pal.S | 10 ++--- 6 files changed, 76 insertions(+), 30 deletions(-)
arch/ia64/config.in +3 -9
@@ -35,7 +35,6 @@ DIG-compliant CONFIG_IA64_DIG \ HP-simulator CONFIG_IA64_HP_SIM \ HP-zx1 CONFIG_IA64_HP_ZX1 \ - SGI-SN1 CONFIG_IA64_SGI_SN1 \ SGI-SN2 CONFIG_IA64_SGI_SN2" generic if [ "$CONFIG_ITANIUM" = "y" ]; then
@@ -54,11 +53,7 @@ if [ "$CONFIG_ITANIUM" = "y" ]; then define_bool CONFIG_IA64_BRL_EMU y bool ' Enable Itanium B-step specific code' CONFIG_ITANIUM_BSTEP_SPECIFIC - if [ "$CONFIG_IA64_SGI_SN1" = "y" ]; then - define_int CONFIG_IA64_L1_CACHE_SHIFT 7 # align cache-sensitive data to 128 bytes - else - define_int CONFIG_IA64_L1_CACHE_SHIFT 6 # align cache-sensitive data to 64 bytes - fi + define_int CONFIG_IA64_L1_CACHE_SHIFT 6 # align cache-sensitive data to 64 bytes fi if [ "$CONFIG_MCKINLEY" = "y" ]; then
@@ -74,13 +69,12 @@ define_bool CONFIG_PM y fi -if [ "$CONFIG_IA64_SGI_SN1" = "y" -o "$CONFIG_IA64_SGI_SN2" = "y" ]; then +if [ "$CONFIG_IA64_SGI_SN2" = "y" ]; then define_bool CONFIG_IA64_SGI_SN y bool ' Enable extra debugging code' CONFIG_IA64_SGI_SN_DEBUG bool ' Enable SGI Medusa Simulator Support' CONFIG_IA64_SGI_SN_SIM - bool ' Enable autotest (llsc). Option to run cache test instead of booting' \ - CONFIG_IA64_SGI_AUTOTEST bool ' Enable protocol mode for the L1 console' CONFIG_SERIAL_SGI_L1_PROTOCOL + define_bool CONFIG_HWGFS_FS y define_bool CONFIG_DISCONTIGMEM y define_bool CONFIG_IA64_MCA y define_bool CONFIG_NUMA y
arch/ia64/kernel/Makefile +1 -0
@@ -17,6 +17,7 @@ machvec.o pal.o process.o perfmon.o ptrace.o sal.o salinfo.o semaphore.o setup.o \ signal.o sys_ia64.o traps.o time.o unaligned.o unwind.o obj-$(CONFIG_IA64_GENERIC) += iosapic.o +obj-$(CONFIG_IA64_SGI_SN2) += iosapic.o obj-$(CONFIG_IA64_HP_ZX1) += iosapic.o obj-$(CONFIG_IA64_DIG) += iosapic.o obj-$(CONFIG_IA64_PALINFO) += palinfo.o
arch/ia64/kernel/acpi.c +3 -2
@@ -98,6 +98,9 @@if (!strcmp (hdr->oem_id,"HP" )) {return "hpzx1" ; } +else if (!strcmp (hdr->oem_id,"SGI" )) { +return "sn2" ; + }return "dig" ;#else
@@ -105,8 +108,6 @@return "hpsim" ;# elif defined (CONFIG_IA64_HP_ZX1 )return "hpzx1" ; -# elif defined (CONFIG_IA64_SGI_SN1 ) -return "sn1" ;# elif defined (CONFIG_IA64_SGI_SN2 )return "sn2" ;# elif defined (CONFIG_IA64_DIG )
arch/ia64/kernel/efi_stub.S +2 -2
@@ -62,7 +62,7 @@ mov b6=r2 ;; andcm r16=loc3,r16 // get psr with IT, DT, and RT bits cleared - br.call.sptk.many rp=ia64_switch_mode + br.call.sptk.many rp=ia64_switch_mode_phys .ret0: mov out4=in5 mov out0=in1 mov out1=in2
@@ -73,7 +73,7 @@ br.call.sptk.many rp¶ // call the EFI function .ret1: mov ar.rsc=0 // put RSE in enforced lazy, LE mode mov r16=loc3 - br.call.sptk.many rp=ia64_switch_mode // return to virtual mode + br.call.sptk.many rp=ia64_switch_mode_virt // return to virtual mode .ret2: mov ar.rsc=loc4 // restore RSE configuration mov ar.pfs=loc1 mov rp=loc0
arch/ia64/kernel/head.S +62 -12
105 lines not on this page · raw message
arch/ia64/kernel/pal.S +5 -5
@@ -164,7 +164,7 @@ ;; mov loc4=ar.rsc // save RSE configuration dep.z loc2=loc2,0,61 // convert pal entry point to physical - dep.z r8=r8,0,61 // convert rp to physical + tpa r8=r8 // convert rp to physical ;; mov b7 = loc2 // install target to branch reg mov ar.rsc=0 // put RSE in enforced lazy, LE mode
@@ -174,13 +174,13 @@ or loc3=loc3,r17 // add in psr the bits to set ;; andcm r16=loc3,r16 // removes bits to clear from psr - br.call.sptk.many rp=ia64_switch_mode + br.call.sptk.many rp=ia64_switch_mode_phys .ret1: mov rp = r8 // install return address (physical) br.cond.sptk.many b7 1: mov ar.rsc=0 // put RSE in enforced lazy, LE mode mov r16=loc3 // r16= original psr - br.call.sptk.many rp=ia64_switch_mode // return to virtual mode + br.call.sptk.many rp=ia64_switch_mode_virt // return to virtual mode .ret2: mov psr.l = loc3 // restore init PSR
@@ -228,13 +228,13 @@ mov b7 = loc2 // install target to branch reg ;; andcm r16=loc3,r16 // removes bits to clear from psr - br.call.sptk.many rp=ia64_switch_mode + br.call.sptk.many rp=ia64_switch_mode_phys .ret6: br.call.sptk.many rp· // now make the call .ret7: mov ar.rsc=0 // put RSE in enforced lazy, LE mode mov r16=loc3 // r16= original psr - br.call.sptk.many rp=ia64_switch_mode // return to virtual mode + br.call.sptk.many rp=ia64_switch_mode_virt // return to virtual mode .ret8: mov psr.l = loc3 // restore init PSR mov ar.pfs = loc1
Signature · 4 lines
Thanks Jack Steiner ([email protected]) 651-683-5302 Principal Engineer SGI - Silicon Graphics, Inc.