2.4.23 MCA TLB error recovery
PATCH 1/1 2.4.23 MCA TLB error recovery
Here's the backport of the MCA TLB recovery code
to 2.4.23-ia64-031205
-Tony
arch/ia64/kernel/efi.c +12 -0
@@ -30,6 +30,7 @@#include <asm/kregs.h> #include <asm/pgtable.h> #include <asm/processor.h> +#include <asm/mca.h> #define EFI_DEBUG 0
@@ -395,6 +396,9 @@int pal_code_count =0 ;u64 mask, psr;u64 vaddr; +#ifdef CONFIG_IA64_MCA +int cpu; +#endif efi_map_start =__va (ia64_boot_param->efi_memmap); efi_map_end = efi_map_start + ia64_boot_param->efi_memmap_size;
@@ -454,6 +458,14 @@ pte_val(mk_pte_phys(md->phys_addr, PAGE_KERNEL)), IA64_GRANULE_SHIFT);ia64_set_psr (psr);/* restore psr */ ia64_srlz_i (); + +#ifdef CONFIG_IA64_MCA + cpu =smp_processor_id (); + +/* insert this TR into our list for MCA recovery purposes */ + ia64_mca_tlb_list[cpu].pal_base=vaddr & mask; + ia64_mca_tlb_list[cpu].pal_paddr=pte_val (mk_pte_phys (md->phys_addr,PAGE_KERNEL )); +#endif } }
arch/ia64/kernel/mca_asm.S +222 -120
419 lines not on this page · raw message
arch/ia64/kernel/mca.c +17 -30
88 lines not on this page · raw message
arch/ia64/mm/init.c +21 -0
@@ -28,6 +28,7 @@#include <asm/sal.h> #include <asm/system.h> #include <asm/uaccess.h> +#include <asm/mca.h> /* References to section boundaries: */ extern char _stext, _etext, _edata, __init_begin, __init_end;
@@ -281,6 +282,10 @@ {unsigned long psr, rid, pta, impl_va_bits;extern void __init tlb_init (void ); +#ifdef CONFIG_IA64_MCA +int cpu; +#endif +#ifdef CONFIG_DISABLE_VHPT # define VHPT_ENABLE_BIT 0#else
@@ -351,6 +356,22 @@ia64_set_pta (pta | (0 <<8 ) | (vmlpt_bits <<2 ) |VHPT_ENABLE_BIT );ia64_tlb_init (); + +#ifdef CONFIG_IA64_MCA + cpu =smp_processor_id (); + +/* mca handler uses cr.lid as key to pick the right entry */ + ia64_mca_tlb_list[cpu].cr_lid =ia64_get_lid (); + +/* insert this percpu data information into our list for MCA recovery purposes */ + ia64_mca_tlb_list[cpu].percpu_paddr =pte_val (mk_pte_phys (__pa (my_cpu_data),PAGE_KERNEL )); +/* Also save per-cpu tlb flush recipe for use in physical mode mca handler */ + ia64_mca_tlb_list[cpu].ptce_base = local_cpu_data->ptce_base; + ia64_mca_tlb_list[cpu].ptce_count[0 ] = local_cpu_data->ptce_count[0 ]; + ia64_mca_tlb_list[cpu].ptce_count[1 ] = local_cpu_data->ptce_count[1 ]; + ia64_mca_tlb_list[cpu].ptce_stride[0 ] = local_cpu_data->ptce_stride[0 ]; + ia64_mca_tlb_list[cpu].ptce_stride[1 ] = local_cpu_data->ptce_stride[1 ]; +#endif } static int
arch/ia64/tools/print_offsets.c +2 -0
@@ -21,6 +21,7 @@#include <asm-ia64/ptrace.h> #include <asm-ia64/siginfo.h> #include <asm-ia64/sigcontext.h> +#include <asm-ia64/mca.h> #include "../kernel/sigframe.h"
@@ -179,6 +180,7 @@ { "IA64_CPU_IRQ_COUNT_OFFSET", offsetof (struct cpuinfo_ia64, irq_stat.f.irq_count) }, { "IA64_CPU_BH_COUNT_OFFSET", offsetof (struct cpuinfo_ia64, irq_stat.f.bh_count) }, { "IA64_CPU_PHYS_STACKED_SIZE_P8_OFFSET",offsetof (struct cpuinfo_ia64, phys_stacked_size_p8)}, + { "IA64_MCA_TLB_INFO_SIZE", sizeof (struct ia64_mca_tlb_info) }, }; static const char *tabs = "\t\t\t\t\t\t\t\t\t\t";
include/asm-ia64/mca.h +12 -2
@@ -15,6 +15,7 @@#include <asm/param.h> #include <asm/sal.h> #include <asm/processor.h> +#include <asm/mca_asm.h> /* These are the return codes from all the IA64_MCA specific interfaces */ typedef int ia64_mca_return_code_t ;
@@ -58,6 +59,17 @@IA64_MCA_RENDEZ_CHECKIN_DONE =0x1 }; +/* the following data structure is used for TLB error recovery purposes */ +extern struct ia64_mca_tlb_info { +u64 cr_lid; +u64 percpu_paddr; +u64 ptce_base; +u32 ptce_count[2 ]; +u32 ptce_stride[2 ]; +u64 pal_paddr; +u64 pal_base; +} ia64_mca_tlb_list[NR_CPUS ]; +/* Information maintained by the MC infrastructure */ typedef struct ia64_mc_info_s { u64 imi_mca_handler;
@@ -105,8 +117,6 @@IA64_MCA_NEW_CONTEXT =-1 /* SAL to return to new context */ }; -#define MIN_STATE_AREA_SIZE 57 - typedef struct ia64_mca_os_to_sal_state_s { u64 imots_os_status; /* OS status to SAL as to what happened * with the MCA handling.