riscv: traps_misaligned: properly sign extend value in misaligned load handler
PATCH 1/1 riscv: traps_misaligned: properly sign extend value in misaligned load handler
Add missing cast to signed long.
--- arch/riscv/kernel/traps_misaligned.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
arch/riscv/kernel/traps_misaligned.c +1 -1
@@ -461,7 +461,7 @@ static int handle_scalar_misaligned_load(struct pt_regs *regs) }if (!fp) -SET_RD (insn, regs, val.data_ulong << shift >> shift); +SET_RD (insn, regs, (long )(val.data_ulong << shift) >> shift);else if (len ==8 )set_f64_rd (insn, regs, val.data_u64);else
Signature · 12 lines
2.50.0 -- Andreas Schwab, SUSE Labs, [email protected] GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE 1748 E4D4 88E3 0EEA B9D7 "And now for something completely different." _______________________________________________ linux-riscv mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-riscv
Quoted 12 lines · Andreas Schwab
Add missing cast to signed long.
Signed-off-by Andreas Schwab <[email protected]>--- arch/riscv/kernel/traps_misaligned.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)arch/riscv/kernel/traps_misaligned.c +0
-0
arch/riscv/kernel/traps_misaligned.c static int handle_scalar_misaligned_load(struct pt_regs *regs) · line 467
Quoted 8 lines
arch/riscv/kernel/traps_misaligned.c +1
-1@@ -461,7 +461,7 @@ static int handle_scalar_misaligned_load(struct pt_regs *regs) }if (!fp) -SET_RD (insn, regs, val.data_ulong << shift >> shift); +SET_RD (insn, regs, (long )(val.data_ulong << shift) >> shift);else if (len ==8 )set_f64_rd (insn, regs, val.data_u64);else
Hi Andreas,
After modify my test to catch sign extension problems, I can confirm it fixes it.
Thanks,
Clément
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Alexandre Ghiti
reviewerHi Andreas,
Quoted 12 lines · Andreas Schwab
Add missing cast to signed long.
Signed-off-by Andreas Schwab <[email protected]>--- arch/riscv/kernel/traps_misaligned.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)arch/riscv/kernel/traps_misaligned.c +0
-0
arch/riscv/kernel/traps_misaligned.c static int handle_scalar_misaligned_load(struct pt_regs *regs) · line 467
Quoted 8 lines
arch/riscv/kernel/traps_misaligned.c +1
-1@@ -461,7 +461,7 @@ static int handle_scalar_misaligned_load(struct pt_regs *regs) }if (!fp) -SET_RD (insn, regs, val.data_ulong << shift >> shift); +SET_RD (insn, regs, (long )(val.data_ulong << shift) >> shift);else if (len ==8 )set_f64_rd (insn, regs, val.data_u64);else
Let's add:
Does that fix the issue you reported when booting with opensbi 1.7?
Thanks,
Alex
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Quoted 1 line · Alexandre Ghiti
Does that fix the issue you reported when booting with opensbi 1.7?
Yes, it does.
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Andreas Schwab, SUSE Labs, [email protected] GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE 1748 E4D4 88E3 0EEA B9D7 "And now for something completely different." _______________________________________________ linux-riscv mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-riscv
Palmer Dabbelt
maintainerQuoted 12 lines · On Thu, 10 Jul 2025 06:32:18 PDT (-0700), [email protected] wrote:
Add missing cast to signed long.
Signed-off-by Andreas Schwab <[email protected]>--- arch/riscv/kernel/traps_misaligned.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)arch/riscv/kernel/traps_misaligned.c +0
-0
arch/riscv/kernel/traps_misaligned.c static int handle_scalar_misaligned_load(struct pt_regs *regs) · line 464
Quoted 5 lines
arch/riscv/kernel/traps_misaligned.c +1
-1@@ -461,7 +461,7 @@ static int handle_scalar_misaligned_load(struct pt_regs *regs) }if (!fp) -SET_RD (insn, regs, val.data_ulong << shift >> shift); +SET_RD (insn, regs, (long )(val.data_ulong << shift) >> shift);
Thanks. I ran into another assembly sign extension issue recently, I think we need to scrub through the port for these...
arch/riscv/kernel/traps_misaligned.c static int handle_scalar_misaligned_load(struct pt_regs *regs) · line 467
Quoted 3 lines
arch/riscv/kernel/traps_misaligned.c +0
-0else if (len ==8 )set_f64_rd (insn, regs, val.data_u64);else
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This patch was applied to riscv/linux.git (fixes) by Palmer Dabbelt <[email protected]>:
Hello:
This patch was applied to riscv/linux.git (fixes)
by Palmer Dabbelt <[email protected]>:
Quoted 6 lines · On Thu, 10 Jul 2025 15:32:18 +0200 you wrote:
Add missing cast to signed long.
Signed-off-by Andreas Schwab <[email protected]>--- arch/riscv/kernel/traps_misaligned.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
Here is the summary with links:
- riscv: traps_misaligned: properly sign extend value in misaligned load handler
https://git.kernel.org/riscv/c/b3510183ab7d
You are awesome, thank you!
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Quoted 1 line · Alexandre Ghiti
Does that fix the issue you reported when booting with opensbi 1.7?
Yes, it does.
Signature · 8 lines
Andreas Schwab, SUSE Labs, [email protected] GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE 1748 E4D4 88E3 0EEA B9D7 "And now for something completely different." _______________________________________________ linux-riscv mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-riscv