Adding uC5272 dimm module support

---
    Makefile                         |   46 +++++
    board/Arcturus/uC5272/Makefile   |   44 +++++
    board/Arcturus/uC5272/config.mk  |    1 +
    board/Arcturus/uC5272/u-boot.lds |  142 +++++++++++++++
    board/Arcturus/uC5272/uC5272.c   |   57 ++++++
    include/configs/uC5272.h         |  354
++++++++++++++++++++++++++++++++++++++
    6 files changed, 644 insertions(+), 0 deletions(-)
    create mode 100644 board/Arcturus/uC5272/Makefile
    create mode 100644 board/Arcturus/uC5272/config.mk
    create mode 100644 board/Arcturus/uC5272/u-boot.lds
    create mode 100644 board/Arcturus/uC5272/uC5272.c
    create mode 100644 include/configs/uC5272.h

index 1b61049..c9215d0 100644
@@ -2222,6 +2222,52 @@ M5485HFE_config :	unconfig
    TASREG_config :		unconfig
    	@$(MKCONFIG) $(@:_config=) m68k mcf52x2 tasreg esd
 
+uC5272-4E16U48_config \
+uC5272-8EE16U66_config \
+uC5272-8E32U66_config \
+uC5272-4EE16U48_config \
+uC5272-4E8U48_config \
+uC5272-4EE8U48_config \
+uC5272-4E8U66_config \
+uC5272-4EE8U66_config \
+uC5272-4E16U66_config \
+uC5272-4EE16U66_config \
+uC5272-4EE32U66_config \
+uC5272-8EE32U66_config:		unconfig
+	@mkdir -p $(obj)include
+	@if [ "$(findstring U48,$@)" ] ; then \
+		echo "#define SYSCLK_48MHZ " >>$(obj)include/config.h ;\
+	fi ;
+	@if [ "$(findstring U66,$@)" ] ; then \
+		echo "#define SYSCLK_66MHZ " >>$(obj)include/config.h ;\
+	fi ;
+	@if [ "$(findstring EE,$@)" ] ; then \
+		echo "#define HAS_ETH1 " >>$(obj)include/config.h ;\
+	fi ;
+	@if [ "$(findstring 4E,$@)" ] ; then \
+		echo "#define __4MFlash__ " >>$(obj)include/config.h ;\
+		echo "#define CONFIG_SYS_FLASH_SIZE 0x00400000"

+ echo "TEXT_BASE = 0x10c00000" > board/Arcturus/uC5272/config.mk ;\
+ fi ;
+ @if [ "$(findstring 8E,$@)" ] ; then \
+ echo "#define __8MFlash__ " >>$(obj)include/config.h ;\
+ echo "#define CONFIG_SYS_FLASH_SIZE 0x00800000"

+ echo "TEXT_BASE = 0x40000000" > board/Arcturus/uC5272/config.mk ;\
+ fi ;
+ @if [ "$(findstring E8,$@)" ] ; then \
+ echo "#define __8MRam__ " >>$(obj)include/config.h ;\
+ echo "#define CONFIG_SYS_SDRAM_SIZE 8" >>$(obj)include/config.h ;\
+ fi ;
+ @if [ "$(findstring E16,$@)" ] ; then \
+ echo "#define __16MRam__ " >>$(obj)include/config.h ;\
+ echo "#define CONFIG_SYS_SDRAM_SIZE 16" >>$(obj)include/config.h ;\
+ fi ;
+ @if [ "$(findstring E32,$@)" ] ; then \
+ echo "#define __32MRam__ " >>$(obj)include/config.h ;\
+ echo "#define CONFIG_SYS_SDRAM_SIZE 32" >>$(obj)include/config.h ;\
+ fi ;
+ @$(MKCONFIG) -a uC5272 m68k mcf52x2 uC5272 Arcturus
+

    #########################################################################
    ## MPC83xx Systems
    #########################################################################

b/board/Arcturus/uC5272/Makefile
new file mode 100644
index 0000000..424ab1c

b/board/Arcturus/uC5272/config.mk
new file mode 100644
index 0000000..e6d701d

@@ -0,0 +1 @@
+TEXT_BASE = 0x40000000

b/board/Arcturus/uC5272/u-boot.lds
new file mode 100644
index 0000000..9d20b22

b/board/Arcturus/uC5272/uC5272.c
new file mode 100644
index 0000000..9b62bb8

Flash
+ */
+#if defined(__8MFlash__)
+#define CONFIG_SYS_CS0_BASE 0x40000000
+#define CONFIG_SYS_BR0_PRELIM 0x40000201
+#define CONFIG_SYS_OR0_PRELIM 0xff800028
+#define CONFIG_ENV_ADDR 0x40040000
+#else
+#define CONFIG_SYS_CS0_BASE 0x10c00000
+#define CONFIG_SYS_BR0_PRELIM 0x10c00201
+#define CONFIG_ENV_ADDR 0x10c40000
+#if defined(__4MFlash__)
+#define CONFIG_SYS_OR0_PRELIM 0xffc00028
+#else
+#define CONFIG_SYS_OR0_PRELIM 0xffe00028 /* default 2M */
+#endif
+#endif
+#define CONFIG_ENV_SIZE 0x40000
+#define CONFIG_ENV_IS_IN_FLASH 1
+/* default kernel image address, end of ENV */
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_MEMORY
+
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_LOADB
+
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+# define CONFIG_NET_MULTI 1
+# define CONFIG_MII 1
+# define CONFIG_MII_INIT 1
+# define CONFIG_SYS_DISCOVER_PHY
+# define CONFIG_SYS_RX_ETH_BUFFER 8
+# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+
+# define CONFIG_SYS_FEC0_PINMUX 0
+# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
+# define MCFFEC_TOUT_LOOP 50000
+# ifndef CONFIG_SYS_DISCOVER_PHY
+# define FECDUPLEX FULL
+# define FECSPEED _100BASET
+# else
+# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+# endif
+# endif /* CONFIG_SYS_DISCOVER_PHY */
+#endif
+
+#define CONFIG_BOOTDELAY 5
+#ifdef CONFIG_MCFFEC
+# define CONFIG_ETHADDR 00:00:00:00:00:00
+# define CONFIG_IPADDR 192.168.1.200
+# define CONFIG_NETMASK 255.255.255.0
+# define CONFIG_SERVERIP 192.168.1.1
+# define CONFIG_GATEWAYIP 192.168.1.1
+# define CONFIG_OVERWRITE_ETHADDR_ONCE
+#endif /* CONFIG_MCFFEC */
+
+#define BOOT_ADDR MK_STR(CONFIG_SYS_FLASH_BASE)
+
+#define CONFIG_HOSTNAME uC5272
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "REVISION="PRODUCT_REVISION"\0" \
+ "netdev=eth0\0" \
+ "loadaddr=10000\0" \
+ "u-boot=u-boot.bin\0" \
+ "load=tftp ${loadaddr) ${u-boot}\0" \
+ "bootaddr="BOOT_ADDR"\0" \
+ "upd=run load; run prog\0" \
+ "prog=prot off ${bootaddr} +${filesize};"\
+ "era ${bootaddr} +${filesize};" \
+ "cp.b ${loadaddr} ${bootaddr} ${filesize};"\
+ "setenv filesize;save\0" \
+ ""
+
+#define CONFIG_SYS_PROMPT "uC5272-> "
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+ /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /*Boot Argument Buffer Size
*/
+#define CONFIG_SYS_MEMTEST_START 0x400
+#define CONFIG_SYS_MEMTEST_END 0x380000
+
+#define CONFIG_SYS_HZ 1000
+
+#if defined(SYSCLK_48MHZ)
+#define CONFIG_SYS_CLK 48000000
+#endif
+
+#if !defined(CONFIG_SYS_CLK)
+#define CONFIG_SYS_CLK 66000000
+#endif
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
+#define CONFIG_SYS_SCR 0x0003
+#define CONFIG_SYS_SPR 0xffff
+ +/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
+#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in internal
SRAM */
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE 64
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
+ CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#if !defined(CONFIG_SYS_SDRAM_SIZE)
+#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
+#endif
+#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
+
+#ifdef CONFIG_MONITOR_IS_IN_RAM
+#define CONFIG_SYS_MONITOR_BASE 0x20000
+#else
+#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN 0x20000
+#define CONFIG_SYS_MALLOC_LEN (256 << 10)
+#define CONFIG_SYS_BOOTPARAMS_LEN (64*1024)
+
+#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE+(CONFIG_SYS_SDRAM_SIZE<<20))
+
+/*
+ * FLASH organization
+ */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER 1
+# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+#if !defined(CONFIG_SYS_MAX_FLASH_BANKS)
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#endif
+#if !defined(CONFIG_SYS_MAX_FLASH_SECT)
+#define CONFIG_SYS_MAX_FLASH_SECT 264 /* max number of sectors on one chip */
+#endif
+#define CONFIG_SYS_FLASH_PROTECTION
+ +/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE 16
+
+#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
+#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
+ CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+ CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
+ CF_CACR_DISD | CF_CACR_INVI | \
+ CF_CACR_CEIB | CF_CACR_DCM | \
+ CF_CACR_EUSP)
+ +/*-----------------------------------------------------------------------
+ * Memory bank definitions
+ */
+/* CS1--cs8900 Ethernet controller */
+#define CONFIG_SYS_BR1_PRELIM 0x30000201
+#define CONFIG_SYS_OR1_PRELIM 0xfffff028
+
+#if CONFIG_SYS_MAX_FLASH_BANKS == 1
+#if defined(__4MFlash__)
+/* CS2 asserted for BACKWARDS COMPATIBILITY for 4M Flash */
+#define CONFIG_SYS_BR2_PRELIM 0x40000201
+#define CONFIG_SYS_OR2_PRELIM 0xfffff028
+#endif
+#else /* assume CONFIG_SYS_MAX_FLASH_BANKS == 2 */
+#define CONFIG_SYS_CS2_BASE 0x20000000
+/* CS2 for another Flash */
+#define CONFIG_SYS_BR2_PRELIM 0x20000201
+#define CONFIG_SYS_OR2_PRELIM 0xff400028 /* set to 4M Flash */
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS2_BASE }
+#endif
+
+#define CONFIG_SYS_BR3_PRELIM 0x50000201
+#define CONFIG_SYS_OR3_PRELIM 0xfffff028
+#define CONFIG_SYS_BR4_PRELIM 0x60000201
+#define CONFIG_SYS_OR4_PRELIM 0xfffff028
+#define CONFIG_SYS_BR5_PRELIM 0x70000201
+#define CONFIG_SYS_OR5_PRELIM 0xfffff028
+#define CONFIG_SYS_BR6_PRELIM 0x80000201
+#define CONFIG_SYS_OR6_PRELIM 0xfffff028
+#define CONFIG_SYS_BR7_PRELIM 0x00000601
+#if defined(SYSCLK_66MHZ)
+#define CONFIG_SYS_SDTR 0xf515 /* SDRAM Timing Register setting */
+#else /* SYSCLK_48MHZ */
+#define CONFIG_SYS_SDTR 0xad15 /* SDRAM Timing Register setting */
+#endif
+#if defined(__8MRam__)
+#define CONFIG_SYS_OR7_PRELIM 0xff80017c
+#define CONFIG_SYS_SDCR 0x00002211 /* SDRAM Control Register: A8 +
A22/A24 */
+#elif defined(__16MRam__)
+#define CONFIG_SYS_OR7_PRELIM 0xff00017c
+#define CONFIG_SYS_SDCR 0x00004311 /* SDRAM Control Register: A9 +
A23/A22 */
+#elif defined(__32MRam__)
+#define CONFIG_SYS_OR7_PRELIM 0xfe00017c
+#define CONFIG_SYS_SDCR 0x00004411 /* SDRAM Control Register: A9 +
A24/A23 */
+#else
+#error "SDRAM size is not defined and SDCR has no setting" +#endif
+ +/*-----------------------------------------------------------------------
+ * Port configuration
+ */
+#define CONFIG_SYS_PACNT 0x00000000
+#define CONFIG_SYS_PADDR 0x0000
+#define CONFIG_SYS_PADAT 0xffbf
+#define CONFIG_SYS_PBCNT 0x55554155 /* Ethernet/UART configuration */
+#define CONFIG_SYS_PBDDR 0x0000
+#define CONFIG_SYS_PBDAT 0x17ea
+#define CONFIG_SYS_PDCNT 0x00005eaa
+#endif /* _CONFIG_UC5272_H */

1.5.6

Dear "David Wu",

I hereby NAK the whole patch series, which seems to have none of the issues fixed that I raised in my earlier review comments.

Best regards,

Wolfgang Denk

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
:       I've tried (in vi) "g/[a-z]\n[a-z]/s//_/"...but that doesn't
: cut it.  Any ideas?  (I take it that it may be a two-pass sort of solution).
In the first pass, install perl. :-) Larry Wall <[email protected]>