PowerPC Embedded KVM qemu enablement patches

@@ -50,9 +50,10 @@ typedef uint32_t ppc_gpr_t;
 /* Specific definitions for PowerPC embedded */
 /* BookE have 36 bits physical address space */
 #define TARGET_PHYS_ADDR_BITS 64
-#if defined(CONFIG_USER_ONLY)
+#if defined(CONFIG_USER_ONLY) || defined(USE_KVM)
 /* It looks like a lot of Linux programs assume page size
  * is 4kB long. This is evil, but we have to deal with it...
+ * Also kvm for embedded powerpc needs (atm) 4kB aligned pages
  */
 #define TARGET_PAGE_BITS 12
 #else /* defined(CONFIG_USER_ONLY) */

@@ -9313,10 +9313,10 @@ int main(int argc, char **argv)
 
 #if USE_KVM
     /* Initialize kvm */
-#ifdef TARGET_IA64
+#if defined(TARGET_I386) || defined(TARGET_X86_64)
+#define KVM_EXTRA_PAGES 3
+#else
 #define KVM_EXTRA_PAGES 0
-#else
-#define KVM_EXTRA_PAGES 3
 #endif
     if (kvm_allowed) {
 	    phys_ram_size += KVM_EXTRA_PAGES * TARGET_PAGE_SIZE;

@@ -26,15 +26,17 @@
 #include <errno.h>
 #include <stdio.h>
 
-int handle_dcr(struct kvm_run *run,  kvm_context_t kvm)
+int handle_dcr(struct kvm_run *run,  kvm_context_t kvm, int vcpu)
 {
 	int ret = 0;
 
 	if (run->dcr.is_write)
-		ret = kvm->callbacks->powerpc_dcr_write(run->dcr.dcrn,
+		ret = kvm->callbacks->powerpc_dcr_write(vcpu,
+							run->dcr.dcrn,
 							run->dcr.data);
 	else
-		ret = kvm->callbacks->powerpc_dcr_read(run->dcr.dcrn,
+		ret = kvm->callbacks->powerpc_dcr_read(vcpu,
+							run->dcr.dcrn,
 							&(run->dcr.data));
 
 	return ret;

@@ -102,7 +104,7 @@ int kvm_arch_run(struct kvm_run *run, kv
 
 	switch (run->exit_reason){
 	case KVM_EXIT_DCR:
-		ret = handle_dcr(run, kvm);
+		ret = handle_dcr(run, kvm, vcpu);
 		break;
 	default:
 		ret = 1;

@@ -66,8 +66,8 @@ struct kvm_callbacks {
     int (*pre_kvm_run)(void *opaque, int vcpu);
     int (*tpr_access)(void *opaque, int vcpu, uint64_t rip, int is_write);
 #if defined(__powerpc__)
-    int (*powerpc_dcr_read)(uint32_t dcrn, uint32_t *data);
-    int (*powerpc_dcr_write)(uint32_t dcrn, uint32_t data);
+    int (*powerpc_dcr_read)(int vcpu, uint32_t dcrn, uint32_t *data);
+    int (*powerpc_dcr_write)(int vcpu, uint32_t dcrn, uint32_t data);
 #endif
 };
 

new file mode 100644
@@ -0,0 +1,198 @@
+
+#include "config.h"
+#include "config-host.h"
+
+extern int kvm_allowed;
+extern int kvm_irqchip;
+
+#ifdef USE_KVM
+
+#include <string.h>
+#include "hw/hw.h"
+#include "sysemu.h"
+#include "cpu.h"
+#include "helper_regs.h"
+
+#include "qemu-kvm.h"
+#include <libkvm.h>
+#include <pthread.h>
+#include <sys/utsname.h>
+
+extern kvm_context_t kvm_context;
+extern __thread CPUState *vcpu_env;
+
+void cpu_reset(CPUState *env)
+{
+	cpu_ppc_reset(env);
+}
+
+
+int kvm_arch_qemu_create_context(void)
+{
+	return 0;
+}
+
+void kvm_arch_load_regs(CPUState *env)
+{
+    struct kvm_regs regs;
+    int rc,i;
+
+    rc = kvm_get_regs(kvm_context, env->cpu_index, &regs);
+    if (rc == -1)
+        perror("kvm_get_regs FAILED");
+
+    /* cr is untouched in qemu and not existant in CPUState fr ppr */
+    /* hflags is a morphed to MSR on ppc, no need to sync that down to kvm */
+
+    regs.pc = env->nip;
+
+    regs.ctr = env->ctr;
+    regs.lr  = env->lr;
+    regs.xer = ppc_load_xer(env);
+    regs.msr = env->msr; 
+
+    regs.srr0 = env->spr[SPR_SRR0];
+    regs.srr1 = env->spr[SPR_SRR1];
+
+    regs.sprg0 = env->spr[SPR_SPRG0];
+    regs.sprg1 = env->spr[SPR_SPRG1];
+    regs.sprg2 = env->spr[SPR_SPRG2];
+    regs.sprg3 = env->spr[SPR_SPRG3];
+    regs.sprg4 = env->spr[SPR_SPRG4];
+    regs.sprg5 = env->spr[SPR_SPRG5];
+    regs.sprg6 = env->spr[SPR_SPRG6];
+    regs.sprg7 = env->spr[SPR_SPRG7];
+
+    for (i = 0;i < 32; i++){
+        regs.gpr[i] = env->gpr[i];
+        regs.fpr[i] = env->fpr[i];
+    }
+
+    rc = kvm_set_regs(kvm_context, env->cpu_index, &regs);
+    if (rc == -1)
+        perror("kvm_set_regs FAILED");
+}
+
+
+void kvm_arch_save_regs(CPUState *env)
+{
+    struct kvm_regs regs;
+    uint32_t i, rc;
+
+    rc = kvm_get_regs(kvm_context, env->cpu_index, &regs);
+    if (rc == -1)
+        perror("kvm_get_regs FAILED");
+
+    env->ctr =regs.ctr;
+    env->lr = regs.lr;
+    ppc_store_xer(env,regs.xer);
+    env->msr = regs.msr;
+    /* calculate hflags based on the current msr using the ppc qemu helper */
+    hreg_compute_hflags(env);
+
+    env->nip = regs.pc;
+
+    env->spr[SPR_SRR0] = regs.srr0;
+    env->spr[SPR_SRR1] = regs.srr1;
+
+    env->spr[SPR_SPRG0] = regs.sprg0;
+    env->spr[SPR_SPRG1] = regs.sprg1;
+    env->spr[SPR_SPRG2] = regs.sprg2;
+    env->spr[SPR_SPRG3] = regs.sprg3;
+    env->spr[SPR_SPRG4] = regs.sprg4;
+    env->spr[SPR_SPRG5] = regs.sprg5;
+    env->spr[SPR_SPRG6] = regs.sprg6;
+    env->spr[SPR_SPRG7] = regs.sprg7;
+
+    for (i = 0;i < 32; i++){
+        env->gpr[i] = regs.gpr[i];
+        env->fpr[i] = regs.fpr[i];
+    }
+
+}
+
+int kvm_arch_qemu_init_env(CPUState *cenv)
+{
+    return 0;
+}
+
+int kvm_arch_halt(void *opaque, int vcpu)
+{
+    CPUState *env = cpu_single_env;
+
+    if (!(env->interrupt_request & CPU_INTERRUPT_HARD) 
+	&& (msr_ee))
+    {
+            env->halted = 1;
+	    env->exception_index = EXCP_HLT;
+    }
+    return 1;
+}
+
+void kvm_arch_pre_kvm_run(void *opaque, int vcpu)
+{
+	return;
+}
+
+void kvm_arch_post_kvm_run(void *opaque, int vcpu)
+{  
+    CPUState *env = qemu_kvm_cpu_env(vcpu);
+    cpu_single_env = env;
+    env->ready_for_interrupt_injection = \
+	kvm_is_ready_for_interrupt_injection(kvm_context, vcpu);
+}
+
+int kvm_arch_has_work(CPUState *env)
+{
+    if ((env->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXIT)) &&
+	(msr_ee))
+	return 1;
+    return 0;
+}
+
+int kvm_arch_try_push_interrupts(void *opaque)
+{
+    CPUState *env = cpu_single_env;
+    int r;
+    unsigned irq;
+
+    if (env->ready_for_interrupt_injection &&
+        (env->interrupt_request & CPU_INTERRUPT_HARD))
+       { 
+            env->interrupt_request &= ~CPU_INTERRUPT_HARD;
+
+            /* For now KVM disregards the 'irq' argument. However, in the
+             * future KVM could cache it in-kernel to avoid a heavyweight exit
+             * when reading the UIC. 
+             */
+            irq = -1U;
+
+            r = kvm_inject_irq(kvm_context, env->cpu_index, irq);
+            if (r < 0)
+                printf("cpu %d fail inject %x\n", env->cpu_index, irq);
+    }
+
+    return (env->interrupt_request & CPU_INTERRUPT_HARD) != 0;
+}
+
+void kvm_arch_update_regs_for_sipi(CPUState *env)
+{
+    printf("%s: no kvm-powerpc multi processor support yet!\n", __func__);
+}
+
+/* map dcr access to existing qemu dcr emulation */
+int handle_powerpc_dcr_read(int vcpu, uint32_t dcrn, uint32_t *data)
+{
+    CPUState *env = qemu_kvm_cpu_env(vcpu);
+    ppc_dcr_read(env->dcr_env, dcrn, data);
+    return 0; /* XXX ignore failed DCR ops */
+}
+
+int handle_powerpc_dcr_write(int vcpu, uint32_t dcrn, uint32_t data)
+{
+    CPUState *env = qemu_kvm_cpu_env(vcpu);
+    ppc_dcr_write(env->dcr_env, dcrn, data);
+    return 0; /* XXX ignore failed DCR ops */
+}
+
+#endif

@@ -55,8 +55,8 @@ int handle_tpr_access(void *opaque, int 
 			     uint64_t rip, int is_write);
 
 #ifdef TARGET_PPC
-int handle_powerpc_dcr_read(uint32_t dcrn, uint32_t *data);
-int handle_powerpc_dcr_write(uint32_t dcrn, uint32_t data);
+int handle_powerpc_dcr_read(int vcpu, uint32_t dcrn, uint32_t *data);
+int handle_powerpc_dcr_write(int vcpu,uint32_t dcrn, uint32_t data);
 #endif
 
 #define ALIGN(x, y)  (((x)+(y)-1) & ~((y)-1))

@@ -573,6 +573,10 @@ struct CPUPPCState {
     target_ulong msr;
     /* temporary general purpose registers */
     ppc_gpr_t tgpr[4]; /* Used to speed-up TLB assist handlers */
+	
+#ifdef USE_KVM
+    uint8_t ready_for_interrupt_injection;
+#endif
 
     /* Floating point execution context */
     /* temporary float registers */

@@ -1421,4 +1425,11 @@ enum {
 
 /*****************************************************************************/
 
+/* hidden flags (hflags) - used internally by qemu to represent additional
+ * cpu states.
+ */
+#define HF_HALTED_SHIFT 1
+
+#define HF_HALTED_MASK 1<<HF_HALTED_SHIFT
+
 #endif /* !defined (__CPU_PPC_H__) */

@@ -32,6 +32,7 @@ extern QEMUMachine heathrow_machine;
 extern QEMUMachine heathrow_machine;
 extern QEMUMachine ref405ep_machine;
 extern QEMUMachine taihu_machine;
+extern QEMUMachine bamboo_machine;
 
 /* mips_r4k.c */
 extern QEMUMachine mips_machine;

56 lines not on this page · raw message

new file mode 100644
@@ -0,0 +1,29 @@
+/*
+ * Qemu PowerPC 440 board emualtion
+ *
+ * Copyright 2007 IBM Corporation.
+ * Authors: Jerone Young <jyoung5-r/[email protected]>
+ *          
+ * This work is licensed under the GNU LGPL license, version 2.
+ *
+ */
+
+#ifndef QEMU_PPC440_H
+#define QEMU_PPC440_H
+
+#include "hw.h"
+#include "ppc.h"
+#include "ppc405.h"
+#include "pc.h"
+#include "qemu-timer.h"
+#include "sysemu.h"
+#include "exec-all.h"
+#include "boards.h"
+
+void ppc440_init(CPUState *env,
+		target_phys_addr_t ram_bases[2],
+		target_phys_addr_t ram_sizes[2],
+		qemu_irq **picp,
+		int do_init);
+
+#endif

124 lines not on this page · raw message

@@ -8318,6 +8318,7 @@ static void register_machines(void)
     qemu_register_machine(&prep_machine);
     qemu_register_machine(&ref405ep_machine);
     qemu_register_machine(&taihu_machine);
+    qemu_register_machine(&bamboo_machine);
 #elif defined(TARGET_MIPS)
     qemu_register_machine(&mips_machine);
     qemu_register_machine(&mips_malta_machine);