kernel boot error.
Quoted 2 lines · Ralf Baechle
Quoted 2 lines · Jason Ormes
I'm using an ip27 (origin 200), and an acenic network card.
[...]
Quoted 4 lines
His particular machine is a uniprocessor machine, a very rare configuration. In all the years I'm working with Origins this is just the second I encounter. Note that disabling one of the processor doesn't suffice; this problem really only seems to hit machines with one physical processor.
1-CPU Origin-200's are not that uncommon.. I have one right here. Although we mostly used to buy 2-CPU Origins we also bought 1-CPU Origins now and then, depending on what we planned to use them for. It's all about price in the end.
-Tor
Quoted 9 lines · Tor Arntsen
Quoted 4 lines
His particular machine is a uniprocessor machine, a very rare configuration. In all the years I'm working with Origins this is just the second I encounter. Note that disabling one of the processor doesn't suffice; this problem really only seems to hit machines with one physical processor.
1-CPU Origin-200's are not that uncommon.. I have one right here. Although we mostly used to buy 2-CPU Origins we also bought 1-CPU Origins now and then, depending on what we planned to use them for. It's all about price in the end.
Maybe my machine room at SGI was just equipped to well :-)
Ralf
Re: [RFC] synchronized CPU count registers on SMP machines
In reply to a message not in the archiveQuoted 6 lines · Ralf Baechle
Quoted 4 lines · Jun Sun
1) clocks on different CPUs don't have the same frequency
2) clocks on different CPUs drift to each other
2) some fancy power saving feature such as frequency scaling
Quoted 7 lines
Quoted 3 lines
But I think for a foreseeable future most MIPS SMP machines don't have the above issues (true?). And it is probably worthwile to synchronize count registers for them.
1) and 2) affect most SGI systems.
Ralf
1) sometimes to the extreme, on SGI Challenge systems:
Quoted 1 line
hinv -c processor
Processor 0: 150 MHZ IP19
CPU: MIPS R4400 Processor Chip Revision: 5.0
FPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0 Processor 1: 150 MHZ IP19
CPU: MIPS R4400 Processor Chip Revision: 5.0
FPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0 Processor 2: 200 MHZ IP19
CPU: MIPS R4400 Processor Chip Revision: 6.0
FPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0 Processor 3: 200 MHZ IP19
CPU: MIPS R4400 Processor Chip Revision: 6.0
FPU: MIPS R4000 Floating Point Coprocessor Revision: 0.0
(and the secondary cache sizes are 1MB and 4MB respectively as well)
-Tor