tools headers: Sync x86 cpufeatures.h with the kernel sources
tip-bot for Arnaldo Carvalho de Melo
merge botCommit-ID: a20d23bb7b04bac27df096d6be4565a1ffdd1ec4 Gitweb: https://git.kernel.org/tip/a20d23bb7b04bac27df096d6be4565a1ffdd1ec4 Author: Arnaldo Carvalho de Melo <[email protected]> AuthorDate: Fri, 1 Jun 2018 11:27:37 -0300 Committer: Arnaldo Carvalho de Melo <[email protected]> CommitDate: Fri, 1 Jun 2018 16:13:16 -0300
tools headers: Sync x86 cpufeatures.h with the kernel sources
To pick up changes found in these csets:
11fb0683493b x86/speculation: Add virtualized speculative store bypass disable support d1035d971829 x86/cpufeatures: Add FEATURE_ZEN
52817587e706 x86/cpufeatures: Disentangle SSBD enumeration
7eb8956a7fec x86/cpufeatures: Disentangle MSR_SPEC_CTRL enumeration from IBRS e7c587da1252 x86/speculation: Use synthetic bits for IBRS/IBPB/STIBP 9f65fb29374e x86/bugs: Rename _RDS to _SSBD
764f3c21588a x86/bugs/AMD: Add support to disable RDS on Fam[15,16,17]h if requested 24f7fc83b920 x86/bugs: Provide boot parameters for the spec_store_bypass_disable mitigation 0cc5fa00b0a8 x86/cpufeatures: Add X86_FEATURE_RDS
c456442cd3a5 x86/bugs: Expose /sys/../spec_store_bypass
The usage of this file in tools doesn't use the newly added X86_FEATURE_ defines:
CC /tmp/build/perf/bench/mem-memcpy-x86-64-asm.o CC /tmp/build/perf/bench/mem-memset-x86-64-asm.o LD /tmp/build/perf/bench/perf-in.o LD /tmp/build/perf/perf-in.o
Silencing this perf build warning:
Warning: Kernel ABI header at 'tools/arch/x86/include/asm/cpufeatures.h' differs from latest version at 'arch/x86/include/asm/cpufeatures.h'
Cc Adrian Hunter <[email protected]>
Cc Borislav Petkov <[email protected]>
Cc David Ahern <[email protected]>
Cc Jiri Olsa <[email protected]>
Cc Konrad Rzeszutek Wilk <[email protected]>
Cc Namhyung Kim <[email protected]>
Cc Thomas Gleixner <[email protected]>
Cc Tom Lendacky <[email protected]>
Cc Wang Nan <[email protected]>
Signed-off-by Arnaldo Carvalho de Melo <[email protected]>
--- tools/arch/x86/include/asm/cpufeatures.h | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-)
tools/arch/x86/include/asm/cpufeatures.h +14 -6
@@ -198,7 +198,6 @@#define X86_FEATURE_CAT_L2 ( 7*32+ 5)/* Cache Allocation Technology L2 */ #define X86_FEATURE_CDP_L3 ( 7*32+ 6)/* Code and Data Prioritization L3 */ #define X86_FEATURE_INVPCID_SINGLE ( 7*32+ 7)/* Effectively INVPCID && CR4.PCIDE=1 */ -#define X86_FEATURE_HW_PSTATE ( 7*32+ 8)/* AMD HW-PState */ #define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9)/* AMD ProcFeedbackInterface */ #define X86_FEATURE_SME ( 7*32+10)/* AMD Secure Memory Encryption */
@@ -207,13 +206,19 @@#define X86_FEATURE_RETPOLINE_AMD ( 7*32+13)/* "" AMD Retpoline mitigation for Spectre variant 2 */ #define X86_FEATURE_INTEL_PPIN ( 7*32+14)/* Intel Processor Inventory Number */ #define X86_FEATURE_CDP_L2 ( 7*32+15)/* Code and Data Prioritization L2 */ - +#define X86_FEATURE_MSR_SPEC_CTRL ( 7*32+16)/* "" MSR SPEC_CTRL is implemented */ +#define X86_FEATURE_SSBD ( 7*32+17)/* Speculative Store Bypass Disable */ #define X86_FEATURE_MBA ( 7*32+18)/* Memory Bandwidth Allocation */ #define X86_FEATURE_RSB_CTXSW ( 7*32+19)/* "" Fill RSB on context switches */ #define X86_FEATURE_SEV ( 7*32+20)/* AMD Secure Encrypted Virtualization */ -#define X86_FEATURE_USE_IBPB ( 7*32+21)/* "" Indirect Branch Prediction Barrier enabled */ #define X86_FEATURE_USE_IBRS_FW ( 7*32+22)/* "" Use IBRS during runtime firmware calls */ +#define X86_FEATURE_SPEC_STORE_BYPASS_DISABLE ( 7*32+23)/* "" Disable Speculative Store Bypass. */ +#define X86_FEATURE_LS_CFG_SSBD ( 7*32+24)/* "" AMD SSBD implementation via LS_CFG MSR */ +#define X86_FEATURE_IBRS ( 7*32+25)/* Indirect Branch Restricted Speculation */ +#define X86_FEATURE_IBPB ( 7*32+26)/* Indirect Branch Prediction Barrier */ +#define X86_FEATURE_STIBP ( 7*32+27)/* Single Thread Indirect Branch Predictors */ +#define X86_FEATURE_ZEN ( 7*32+28)/* "" CPU is AMD family 0x17 (Zen) */ /* Virtualization flags: Linux defined, word 8 */ #define X86_FEATURE_TPR_SHADOW ( 8*32+ 0)/* Intel TPR Shadow */
@@ -274,9 +279,10 @@#define X86_FEATURE_CLZERO (13*32+ 0)/* CLZERO instruction */ #define X86_FEATURE_IRPERF (13*32+ 1)/* Instructions Retired Count */ #define X86_FEATURE_XSAVEERPTR (13*32+ 2)/* Always save/restore FP error pointers */ -#define X86_FEATURE_IBPB (13*32+12)/* Indirect Branch Prediction Barrier */ -#define X86_FEATURE_IBRS (13*32+14)/* Indirect Branch Restricted Speculation */ -#define X86_FEATURE_STIBP (13*32+15)/* Single Thread Indirect Branch Predictors */ +#define X86_FEATURE_AMD_IBPB (13*32+12)/* "" Indirect Branch Prediction Barrier */ +#define X86_FEATURE_AMD_IBRS (13*32+14)/* "" Indirect Branch Restricted Speculation */ +#define X86_FEATURE_AMD_STIBP (13*32+15)/* "" Single Thread Indirect Branch Predictors */ +#define X86_FEATURE_VIRT_SSBD (13*32+25)/* Virtualized Speculative Store Bypass Disable */ /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */ #define X86_FEATURE_DTHERM (14*32+ 0)/* Digital Thermal Sensor */
@@ -334,6 +340,7 @@#define X86_FEATURE_SPEC_CTRL (18*32+26)/* "" Speculation Control (IBRS + IBPB) */ #define X86_FEATURE_INTEL_STIBP (18*32+27)/* "" Single Thread Indirect Branch Predictors */ #define X86_FEATURE_ARCH_CAPABILITIES (18*32+29)/* IA32_ARCH_CAPABILITIES MSR (Intel) */ +#define X86_FEATURE_SPEC_CTRL_SSBD (18*32+31)/* "" Speculative Store Bypass Disable */ /* * BUG word(s)
@@ -363,5 +370,6 @@#define X86_BUG_CPU_MELTDOWN X86_BUG(14)/* CPU is affected by meltdown attack and needs kernel page table isolation */ #define X86_BUG_SPECTRE_V1 X86_BUG(15)/* CPU is affected by Spectre variant 1 attack with conditional branches */ #define X86_BUG_SPECTRE_V2 X86_BUG(16)/* CPU is affected by Spectre variant 2 attack with indirect branches */ +#define X86_BUG_SPEC_STORE_BYPASS X86_BUG(17)/* CPU is affected by speculative store bypass attack */ #endif /* _ASM_X86_CPUFEATURES_H */