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perf/x86: Add SNB offcore event constraints

tip:perf/urgent tip-bot for Peter Zijlstra 2 participants 3 messages Mar 27, 2012

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#0 lore raw
Commit-ID:  c370117c978adba861fad467427a9301c2c7082b
Gitweb:     http://git.kernel.org/tip/c370117c978adba861fad467427a9301c2c7082b
Author:     Peter Zijlstra <[email protected]>
AuthorDate: Thu, 22 Mar 2012 11:41:23 +0100
Committer:  Ingo Molnar <[email protected]>
CommitDate: Tue, 27 Mar 2012 14:53:46 +0200

perf/x86: Add SNB offcore event constraints

As found in the Intel SDM (March 2012 edition) in Volume 3 section 18.8.5, the offcore response events are constrained to PMC0 and PMC3 resp..

Signed-off-by Peter Zijlstra <[email protected]>
Cc Stephane Eranian <[email protected]>
Cc <[email protected]>
Link http://lkml.kernel.org/n/[email protected] open here
Signed-off-by Ingo Molnar <[email protected]>
---
 arch/x86/kernel/cpu/perf_event_intel.c |   14 ++++++++------
 1 files changed, 8 insertions(+), 6 deletions(-)
arch/x86/kernel/cpu/perf_event_intel.c +8 -6
index 26b3e2f..bab8c6d 100644
@@ -96,12 +96,14 @@ static struct event_constraint intel_westmere_event_constraints[] __read_mostly
 
 static struct event_constraint intel_snb_event_constraints[] __read_mostly =
 {
-	FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
-	FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
-	FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
-	INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
-	INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
-	INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
+	FIXED_EVENT_CONSTRAINT(0x00c0, 0),	/* INST_RETIRED.ANY */
+	FIXED_EVENT_CONSTRAINT(0x003c, 1),	/* CPU_CLK_UNHALTED.CORE */
+	FIXED_EVENT_CONSTRAINT(0x0300, 2),	/* CPU_CLK_UNHALTED.REF */
+	INTEL_EVENT_CONSTRAINT(0x48, 0x4),	/* L1D_PEND_MISS.PENDING */
+	INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2),	/* INST_RETIRED.PREC_DIST */
+	INTEL_EVENT_CONSTRAINT(0xcd, 0x8),	/* MEM_TRANS_RETIRED.LOAD_LATENCY */
+	INTEL_UEVENT_CONSTRAINT(0x01b7, 0x1),	/* OFFCORE_RSP_0 */
+	INTEL_UEVENT_CONSTRAINT(0x01bb, 0x8),	/* OFFCORE_RSP_1 */
 	EVENT_CONSTRAINT_END
 };
#1 lore raw
Quoted 7 lines · tip-bot for Peter Zijlstra

Commit-ID:  c370117c978adba861fad467427a9301c2c7082b
Gitweb:     http://git.kernel.org/tip/c370117c978adba861fad467427a9301c2c7082b
Author:     Peter Zijlstra <[email protected]>
AuthorDate: Thu, 22 Mar 2012 11:41:23 +0100
Committer:  Ingo Molnar <[email protected]>
CommitDate: Tue, 27 Mar 2012 14:53:46 +0200

Quoted 6 lines

perf/x86: Add SNB offcore event constraints

As found in the Intel SDM (March 2012 edition) in Volume 3 section 18.8.5, the offcore response events are constrained to PMC0 and PMC3 resp..

I don't believe this is correct in the SDM. It may be a side effect of how Intel tools work. I'll check again.

Quoted 34 lines
Signed-off-by Peter Zijlstra <[email protected]>
Cc Stephane Eranian <[email protected]>
Cc <[email protected]>
Link http://lkml.kernel.org/n/[email protected] open here
Signed-off-by Ingo Molnar <[email protected]>

---
 arch/x86/kernel/cpu/perf_event_intel.c |   14 ++++++++------

 1 files changed, 8 insertions(+), 6 deletions(-)
arch/x86/kernel/cpu/perf_event_intel.c +0 -0
index 26b3e2f..bab8c6d 100644
@@ -96,12 +96,14 @@ static struct event_constraint intel_westmere_event_constraints[] __read_mostly

 static struct event_constraint intel_snb_event_constraints[] __read_mostly = {
-       FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
-       FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
-       FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
-       INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
-       INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
-       INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
+       FIXED_EVENT_CONSTRAINT(0x00c0, 0),      /* INST_RETIRED.ANY */
+       FIXED_EVENT_CONSTRAINT(0x003c, 1),      /* CPU_CLK_UNHALTED.CORE */
+       FIXED_EVENT_CONSTRAINT(0x0300, 2),      /* CPU_CLK_UNHALTED.REF */
+       INTEL_EVENT_CONSTRAINT(0x48, 0x4),      /* L1D_PEND_MISS.PENDING */
+       INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2),   /* INST_RETIRED.PREC_DIST */
+       INTEL_EVENT_CONSTRAINT(0xcd, 0x8),      /* MEM_TRANS_RETIRED.LOAD_LATENCY */
+       INTEL_UEVENT_CONSTRAINT(0x01b7, 0x1),   /* OFFCORE_RSP_0 */
+       INTEL_UEVENT_CONSTRAINT(0x01bb, 0x8),   /* OFFCORE_RSP_1 */ EVENT_CONSTRAINT_END
 };

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#2 lore raw
In reply to tip-bot for Peter Zijlstra
Quoted 7 lines · tip-bot for Peter Zijlstra
Commit-ID:  c370117c978adba861fad467427a9301c2c7082b
Gitweb:     http://git.kernel.org/tip/c370117c978adba861fad467427a9301c2c7082b
Author:     Peter Zijlstra <[email protected]>
AuthorDate: Thu, 22 Mar 2012 11:41:23 +0100
Committer:  Ingo Molnar <[email protected]>
CommitDate: Tue, 27 Mar 2012 14:53:46 +0200
Quoted 5 lines

perf/x86: Add SNB offcore event constraints

As found in the Intel SDM (March 2012 edition) in Volume 3 section 18.8.5, the offcore response events are constrained to PMC0 and PMC3 resp..

Ingo, Stephane talked to some Intel folks and the SDM was wrong, can you make this here patch go away?