perf tools: Move powerpc barrier.h stuff to tools /arch/powerpc/include/asm/barrier.h

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2015-05-10 07:06 UTC #0 lore raw

Commit-ID:  e43a19c9c2c30cf88ffafb8390a4c53400b2467e
Gitweb:     http://git.kernel.org/tip/e43a19c9c2c30cf88ffafb8390a4c53400b2467e
Author:     Arnaldo Carvalho de Melo <[email protected]>
AuthorDate: Wed, 6 May 2015 18:35:20 -0300
Committer:  Arnaldo Carvalho de Melo <[email protected]>
CommitDate: Fri, 8 May 2015 16:05:03 -0300

perf tools: Move powerpc barrier.h stuff to tools/arch/powerpc/include/asm/barrier.h

We will need it for atomic.h, so move it from the ad-hoc tools/perf/ place to a tools/ subset of the kernel arch/ hierarchy.

Cc Adrian Hunter <[email protected]>

Cc Borislav Petkov <[email protected]>

Cc David Ahern <[email protected]>

Cc Don Zickus <[email protected]>

Cc Frederic Weisbecker <[email protected]>

Cc Jiri Olsa <[email protected]>

Cc Namhyung Kim <[email protected]>

Cc Stephane Eranian <[email protected]>

Link http://lkml.kernel.org/n/[email protected] open here

Signed-off-by Arnaldo Carvalho de Melo <[email protected]>

---
 tools/arch/powerpc/include/asm/barrier.h | 29 +++++++++++++++++++++++++++++
 tools/include/asm/barrier.h              |  2 ++
 tools/perf/MANIFEST                      |  1 +
 tools/perf/perf-sys.h                    |  3 ---
 4 files changed, 32 insertions(+), 3 deletions(-)

tools/arch/powerpc/include/asm/barrier.h new file +29 -0

new file mode 100644
index 0000000..b23aee8
@@ -0,0 +1,29 @@
+/*
+ * Copied from the kernel sources:
+ *
+ * Copyright (C) 1999 Cort Dougan <[email protected]>
+ */
+#ifndef _TOOLS_LINUX_ASM_POWERPC_BARRIER_H
+#define _TOOLS_LINUX_ASM_POWERPC_BARRIER_H
+
+/*
+ * Memory barrier.
+ * The sync instruction guarantees that all memory accesses initiated
+ * by this processor have been performed (with respect to all other
+ * mechanisms that access memory).  The eieio instruction is a barrier
+ * providing an ordering (separately) for (a) cacheable stores and (b)
+ * loads and stores to non-cacheable memory (e.g. I/O devices).
+ *
+ * mb() prevents loads and stores being reordered across this point.
+ * rmb() prevents loads being reordered across this point.
+ * wmb() prevents stores being reordered across this point.
+ *
+ * *mb() variants without smp_ prefix must order all types of memory
+ * operations with one another. sync is the only instruction sufficient
+ * to do this.
+ */
+#define mb()   __asm__ __volatile__ ("sync" : : : "memory")
+#define rmb()  __asm__ __volatile__ ("sync" : : : "memory")
+#define wmb()  __asm__ __volatile__ ("sync" : : : "memory")
+
+#endif /* _TOOLS_LINUX_ASM_POWERPC_BARRIER_H */

tools/include/asm/barrier.h +2 -0

index 9a55c12..249f672 100644
@@ -1,3 +1,5 @@
 #if defined(__i386__) || defined(__x86_64__)
 #include "../../arch/x86/include/asm/barrier.h"
+#elif defined(__powerpc__)
+#include "../../arch/powerpc/include/asm/barrier.h"
 #endif

tools/perf/MANIFEST +1 -0

index 594737a..4b3346e 100644
@@ -1,4 +1,5 @@
 tools/perf
+tools/arch/powerpc/include/asm/barrier.h
 tools/arch/x86/include/asm/barrier.h
 tools/scripts
 tools/build

tools/perf/perf-sys.h +0 -3

index 781d441..01c0695 100644
@@ -38,9 +38,6 @@
 
 #ifdef __powerpc__
 #include "../../arch/powerpc/include/uapi/asm/unistd.h"
-#define mb()		asm volatile ("sync" ::: "memory")
-#define wmb()		asm volatile ("sync" ::: "memory")
-#define rmb()		asm volatile ("sync" ::: "memory")
 #define CPUINFO_PROC	{"cpu"}
 #endif