arm64: KVM: Implement 4 levels of translation tables for HYP and stage2
Subsystems (4)
PATCH v6 7/7 arm64: KVM: Implement 4 levels of translation tables for HYP and stage2
This patch adds 4 levels of translation tables implementation for both HYP and stage2.
Both symmetric and asymmetric configurations for page size and translation levels are are validated on Fast Models:
1) 4KB + 3 levels guest on 4KB + 4 levels host 2) 4KB + 4 levels guest on 4KB + 4 levels host 3) 64KB + 2 levels guest on 4KB + 4 levels host
4) 4KB + 3 levels guest on 64KB + 2 levels host
5) 4KB + 4 levels guest on 64KB + 2 levels host
6) 64KB + 2 levels guest on 64KB + 2 levels host
Cc Marc Zyngier <[email protected]>
Cc Christoffer Dall <[email protected]>
Signed-off-by Jungseok Lee <[email protected]>
Reviewed-by Sungjinn Chung <[email protected]>
Acked-by Kukjin Kim <[email protected]>
--- arch/arm/include/asm/kvm_mmu.h | 10 +++++ arch/arm/kvm/arm.c | 8 ++++ arch/arm/kvm/mmu.c | 77 ++++++++++++++++++++++++++++++++------ arch/arm64/include/asm/kvm_arm.h | 12 ++++++ arch/arm64/include/asm/kvm_mmu.h | 12 ++++++ 5 files changed, 108 insertions(+), 11 deletions(-)
arch/arm/include/asm/kvm_mmu.h +10 -0
@@ -37,6 +37,11 @@*/ #define TRAMPOLINE_VA UL(CONFIG_VECTORS_BASE) +/* +* KVM_MMU_CACHE_MIN_PAGES is the number of stage2 page table translation levels. +*/ +#define MMU_CACHE_MIN_PAGES 2 +#ifndef __ASSEMBLY__#include <asm/cacheflush.h>
@@ -94,6 +99,11 @@ static inline void kvm_clean_pgd(pgd_t *pgd)clean_dcache_area (pgd,PTRS_PER_S2_PGD *sizeof (pgd_t)); } +static inline void kvm_clean_pmd (pmd_t *pmd) +{ +clean_dcache_area (pmd,PTRS_PER_PMD *sizeof (pmd_t)); +} +static inline void kvm_clean_pmd_entry (pmd_t *pmd) {clean_pmd_entry (pmd);
arch/arm/kvm/arm.c +8 -0
@@ -473,11 +473,19 @@ static int set_vttbr_baddr_mask(void)* 21 <= T0SZ <= 30 is valid under 3 level of translation tables * 30 <= T0SZ <= 39 is valid under 2 level of translation tables */ +#ifdef CONFIG_ARM64_3_LEVELS if (t0sz <=20 ) {kvm_err ("Cannot support %d-bit address space\n" ,64 - t0sz);return -EINVAL ; } vttbr_x =37 - t0sz; +#else +if (t0sz <=15 ) { +kvm_err ("Cannot support %d-bit address space\n" ,64 - t0sz); +return -EINVAL ; + } + vttbr_x =28 - t0sz; +#endif #endif vttbr_baddr_mask = (((1LLU << (48 - vttbr_x)) -1 ) << (vttbr_x -1 ));#endif
arch/arm/kvm/mmu.c +66 -11
123 lines not on this page · raw message
arch/arm64/include/asm/kvm_arm.h +12 -0
@@ -114,6 +114,7 @@#define VTCR_EL2_IRGN0_MASK (3 << 8)#define VTCR_EL2_IRGN0_WBWA (1 << 8)#define VTCR_EL2_SL0_MASK (3 << 6) +#define VTCR_EL2_SL0_LVL0 (2 << 6)#define VTCR_EL2_SL0_LVL1 (1 << 6)#define VTCR_EL2_T0SZ_MASK 0x3f#define VTCR_EL2_T0SZ (bits) (64 - (bits))
@@ -128,6 +129,7 @@ VTCR_EL2_ORGN0_WBWA | VTCR_EL2_IRGN0_WBWA | \ VTCR_EL2_SL0_LVL1)#else +#ifdef CONFIG_ARM64_3_LEVELS /* * Stage2 translation configuration: * 4kB pages (TG0 = 0)
@@ -136,6 +138,16 @@#define VTCR_EL2_FLAGS (VTCR_EL2_TG0_4K | VTCR_EL2_SH0_INNER | \ VTCR_EL2_ORGN0_WBWA | VTCR_EL2_IRGN0_WBWA | \ VTCR_EL2_SL0_LVL1) +#else +/* +* Stage2 translation configuration: +* 4kB pages (TG0 = 0) +* 4 level page tables (SL = 2) +*/ +#define VTCR_EL2_FLAGS (VTCR_EL2_TG0_4K | VTCR_EL2_SH0_INNER | \ + VTCR_EL2_ORGN0_WBWA | VTCR_EL2_IRGN0_WBWA | \ + VTCR_EL2_SL0_LVL0) +#endif #endif #define VTTBR_VMID_SHIFT (48LLU)
arch/arm64/include/asm/kvm_mmu.h +12 -0
@@ -41,6 +41,17 @@*/ #define TRAMPOLINE_VA (HYP_PAGE_OFFSET_MASK & PAGE_MASK) +/* +* KVM_MMU_CACHE_MIN_PAGES is the number of stage2 page table translation levels. +*/ +#ifdef CONFIG_ARM64_2_LEVELS +#define KVM_MMU_CACHE_MIN_PAGES 1 +#elif defined(CONFIG_ARM64_3_LEVELS ) +#define KVM_MMU_CACHE_MIN_PAGES 2 +#else +#define KVM_MMU_CACHE_MIN_PAGES 3 +#endif +#ifdef __ASSEMBLY__/*
@@ -107,6 +118,7 @@ static inline bool kvm_is_write_fault(unsigned long esr) }static inline void kvm_clean_pgd (pgd_t *pgd) {} +static inline void kvm_clean_pmd (pmd_t *pmd) {}static inline void kvm_clean_pmd_entry (pmd_t *pmd) {}static inline void kvm_clean_pte (pte_t *pte) {}static inline void kvm_clean_pte_entry (pte_t *pte) {}
Signature · 1 line
1.7.10.4