enable L2-cache for ALPR, Katmai, Ocotea, and Taishan
PATCH 2/2 enable L2-cache for ALPR, Katmai, Ocotea, and Taishan
This patch introduces the L2_CACHE configuration option available
for the ppc44x-based boards with L2-cache enabled.
--
arch/ppc/platforms/4xx/Kconfig +8 -0
@@ -396,4 +396,12 @@ config SERIAL_SICC_CONSOLE bool depends on SERIAL_SICC && UART0_TTYS1 default y + +config L2_CACHE + bool "Enable Level-2 Cache" + depends on NOT_COHERENT_CACHE && (KATMAI || TAISHAN || OCOTEA || ALPR) + default y + help + This option enables L2-cache on ppc44x controllers. + If unsure, say Y. endmenu
arch/ppc/platforms/4xx/alpr.c +4 -0
@@ -537,10 +537,12 @@ static void __init alpr_setup_arch(void)printk ("Prodrive ALPR port (DENX Software Engineering <[email protected]>)\n" ); } +#ifdef CONFIG_L2_CACHE static void __init alpr_init (void ) {ibm440gx_l2c_setup (&clocks); } +#endif static void alpr_progress (char *buf,unsigned short val) {
@@ -567,7 +569,9 @@ void __init platform_init(unsigned long r3, unsigned long r4,#ifdef CONFIG_KGDB ppc_md.early_serial_map = alpr_early_serial_map;#endif +#ifdef CONFIG_L2_CACHE ppc_md.init = alpr_init; +#endif ppc_md.restart = alpr_restart; }
arch/ppc/platforms/4xx/katmai.c +11 -0
@@ -219,6 +219,7 @@ katmai_show_cpuinfo(struct seq_file *m) {seq_printf (m,"vendor\t\t: AMCC\n" );seq_printf (m,"machine\t\t: PPC440SPe EVB (Katmai)\n" ); +ibm440gx_show_cpuinfo (m);return 0 ; }
@@ -584,6 +585,13 @@ static void katmai_restart(char *cmd)mtspr (SPRN_DBCR0 ,DBCR0_RST_CHIP ); } +#ifdef CONFIG_L2_CACHE +static void __init katmai_init (void ) +{ +ibm440gx_l2c_setup (&clocks); +} +#endif +void __init platform_init (unsigned long r3,unsigned long r4,unsigned long r5,unsigned long r6,unsigned long r7) {
@@ -599,4 +607,7 @@ void __init platform_init(unsigned long r3, unsigned long r4, ppc_md.early_serial_map = katmai_early_serial_map;#endif ppc_md.restart = katmai_restart; +#ifdef CONFIG_L2_CACHE + ppc_md.init = katmai_init; +#endif }
arch/ppc/platforms/4xx/ocotea.c +4 -0
@@ -321,10 +321,12 @@ ocotea_setup_arch(void)printk ("IBM Ocotea port (MontaVista Software, Inc. <[email protected]>)\n" ); } +#ifdef CONFIG_L2_CACHE static void __init ocotea_init (void ) {ibm440gx_l2c_setup (&clocks); } +#endif void __init platform_init (unsigned long r3,unsigned long r4,unsigned long r5,unsigned long r6,unsigned long r7)
@@ -345,5 +347,7 @@ void __init platform_init(unsigned long r3, unsigned long r4,#ifdef CONFIG_KGDB ppc_md.early_serial_map = ocotea_early_serial_map;#endif +#ifdef CONFIG_L2_CACHE ppc_md.init = ocotea_init; +#endif }
arch/ppc/platforms/4xx/taishan.c +4 -0
@@ -370,10 +370,12 @@ taishan_setup_arch(void)printk ("AMCC PowerPC 440GX Taishan Platform\n" ); } +#ifdef CONFIG_L2_CACHE static void __init taishan_init (void ) {ibm440gx_l2c_setup (&clocks); } +#endif void __init platform_init (unsigned long r3,unsigned long r4,unsigned long r5,unsigned long r6,unsigned long r7)
@@ -389,6 +391,8 @@ void __init platform_init(unsigned long r3, unsigned long r4,#ifdef CONFIG_KGDB ppc_md.early_serial_map = taishan_early_serial_map;#endif +#ifdef CONFIG_L2_CACHE ppc_md.init = taishan_init; +#endif }
Hi,
See comments below.
-Olof
Quoted 13 lines · Yuri Tikhonov
This patch introduces the
L2_CACHEconfiguration option available
for the ppc44x-based boards with L2-cache enabled.Signed-off-by Yuri Tikhonov <[email protected]>Signed-off-by Pavel Kolesnikov <[email protected]>--
arch/ppc/platforms/4xx/Kconfig +0
-0@@ -396,4 +396,12 @@ config SERIAL_SICC_CONSOLE bool
arch/ppc/platforms/4xx/Kconfig config SERIAL_SICC_CONSOLE · line 406
Quoted 10 lines
arch/ppc/platforms/4xx/Kconfig +8
-0depends on SERIAL_SICC && UART0_TTYS1 default y + +config L2_CACHE + bool "Enable Level-2 Cache" + depends on NOT_COHERENT_CACHE && (KATMAI || TAISHAN || OCOTEA || ALPR) + default y + help + This option enables L2-cache on ppc44x controllers. + If unsure, say Y.
That's a very generic config name. Maybe something like PPC_4XX_L2_CACHE?
Is there ever a case where a user would NOT want l2 cache enabled (and disabled permanently enough to rebuild the kernel instead of giving a kernel command line option?)
Quoted 19 lines
arch/ppc/platforms/4xx/Kconfig +0
-0endmenuarch/ppc/platforms/4xx/alpr.c +2
-0@@ -537,10 +537,12 @@ static void __init alpr_setup_arch(void)printk ("Prodrive ALPR port (DENX Software Engineering <[email protected]>)\n" ); } +#ifdef CONFIG_L2_CACHE static void __init alpr_init (void ) {ibm440gx_l2c_setup (&clocks); } +#endif static void alpr_progress (char *buf,unsigned short val) {
arch/ppc/platforms/4xx/alpr.c void __init platform_init(unsigned long r3, unsigned long r4, · line 574
Quoted 6 lines
arch/ppc/platforms/4xx/alpr.c +2
-0@@ -567,7 +569,9 @@ void __init platform_init(unsigned long r3, unsigned long r4,#ifdef CONFIG_KGDB ppc_md.early_serial_map = alpr_early_serial_map;#endif +#ifdef CONFIG_L2_CACHE ppc_md.init = alpr_init; +#endif
Why do you take out the above calls if the new option is selected? Seems odd to remove something that worked(?) before.
arch/ppc/platforms/4xx/katmai.c katmai_show_cpuinfo(struct seq_file *m) · line 222
Quoted 12 lines
arch/ppc/platforms/4xx/alpr.c +0
-0ppc_md.restart = alpr_restart; }arch/ppc/platforms/4xx/katmai.c +1
-0@@ -219,6 +219,7 @@ katmai_show_cpuinfo(struct seq_file *m) {seq_printf (m,"vendor\t\t: AMCC\n" );seq_printf (m,"machine\t\t: PPC440SPe EVB (Katmai)\n" ); +ibm440gx_show_cpuinfo (m);
This seems unrelated to this patch.
Quoted 17 lines
arch/ppc/platforms/4xx/katmai.c +7
-0return 0 ; }@@ -584,6 +585,13 @@ static void katmai_restart(char *cmd)mtspr (SPRN_DBCR0 ,DBCR0_RST_CHIP ); } +#ifdef CONFIG_L2_CACHE +static void __init katmai_init (void ) +{ +ibm440gx_l2c_setup (&clocks); +} +#endif +void __init platform_init (unsigned long r3,unsigned long r4,unsigned long r5,unsigned long r6,unsigned long r7) {
arch/ppc/platforms/4xx/katmai.c void __init platform_init(unsigned long r3, unsigned long r4, · line 612
Quoted 6 lines
arch/ppc/platforms/4xx/katmai.c +3
-0@@ -599,4 +607,7 @@ void __init platform_init(unsigned long r3, unsigned long r4, ppc_md.early_serial_map = katmai_early_serial_map;#endif ppc_md.restart = katmai_restart; +#ifdef CONFIG_L2_CACHE + ppc_md.init = katmai_init; +#endif
See comment above. Should the above init be called for all configs, not just when L2_CACHE is enabled?
Also, it looks like the init function is the same on every board. It would be better to make a common function instead of duplicating it everywhere.
Quoted 57 lines
arch/ppc/platforms/4xx/katmai.c +0
-0}arch/ppc/platforms/4xx/ocotea.c +4
-0@@ -321,10 +321,12 @@ ocotea_setup_arch(void)printk ("IBM Ocotea port (MontaVista Software, Inc. <[email protected]>)\n" ); } +#ifdef CONFIG_L2_CACHE static void __init ocotea_init (void ) {ibm440gx_l2c_setup (&clocks); } +#endif void __init platform_init (unsigned long r3,unsigned long r4,unsigned long r5,unsigned long r6,unsigned long r7)@@ -345,5 +347,7 @@ void __init platform_init(unsigned long r3, unsigned long r4,#ifdef CONFIG_KGDB ppc_md.early_serial_map = ocotea_early_serial_map;#endif +#ifdef CONFIG_L2_CACHE ppc_md.init = ocotea_init; +#endif }arch/ppc/platforms/4xx/taishan.c +4
-0@@ -370,10 +370,12 @@ taishan_setup_arch(void)printk ("AMCC PowerPC 440GX Taishan Platform\n" ); } +#ifdef CONFIG_L2_CACHE static void __init taishan_init (void ) {ibm440gx_l2c_setup (&clocks); } +#endif void __init platform_init (unsigned long r3,unsigned long r4,unsigned long r5,unsigned long r6,unsigned long r7)@@ -389,6 +391,8 @@ void __init platform_init(unsigned long r3, unsigned long r4,#ifdef CONFIG_KGDB ppc_md.early_serial_map = taishan_early_serial_map;#endif +#ifdef CONFIG_L2_CACHE ppc_md.init = taishan_init; +#endif }_______________________________________________
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Hi Olof,
On 07.11.2007, 7:06:08 you wrote:
...
Quoted 10 lines
arch/ppc/platforms/4xx/Kconfig config SERIAL_SICC_CONSOLE · line 406
Quoted 8 lines
arch/ppc/platforms/4xx/Kconfig +8
-0+ +config L2_CACHE + bool "Enable Level-2 Cache" + depends on NOT_COHERENT_CACHE && (KATMAI || TAISHAN || OCOTEA || ALPR) + default y + help + This option enables L2-cache on ppc44x controllers. + If unsure, say Y.That's a very generic config name. Maybe something like
PPC_4XX_L2_CACHE?
Having the ppc_machdep for invalidating L2-cache lines we can avoid introducing the new configuration options at all. See below.
Quoted 3 lines
Is there ever a case where a user would NOT want l2 cache enabled (and disabled permanently enough to rebuild the kernel instead of giving a kernel command line option?)
Theoretically - yes. Internal SRAM of ppc44x may be used for something else than L2 cache.
Admittedly, the configuration option was necessary for me to enable or disable my L2-cache synchronization routine in the generic dma_sync() function. Per your suggestion, now, instead of introducing the new kernel option I initialize the L2-cache sync ppc_machdep right in the L2-cache enable routine: thus if the user will not enable L2-cache (will not want internal SRAM to act as L2-cache and will not call the L2-cache enabling routine) then my new ppc_machdep will remain set to zero and will not affect on SRAM used for some specific purposes.
...
Quoted 10 lines
arch/ppc/platforms/4xx/alpr.c void __init platform_init(unsigned long r3, unsigned long r4, · line 574
Quoted 7 lines
arch/ppc/platforms/4xx/alpr.c +2
-0@@ -567,7 +569,9 @@ void __init platform_init(unsigned long r3, unsigned long r4,#ifdef CONFIG_KGDB ppc_md.early_serial_map = alpr_early_serial_map;#endif +#ifdef CONFIG_L2_CACHE ppc_md.init = alpr_init; +#endif Why do you take out the above calls if the new option is selected? Seems odd to remove something that worked(?) before.
Umm.. Quite the contrary, the option selected made these calls avaiable. Though it doesn't matter anymore since there is no CONFIG_L2_CACHE option anymore (i.e. all the four boards dealt with in this patch-set now have L2-cache enabled regardless of configuration, as it was initially).
Quoted 3 lines
Quoted 3 lines
arch/ppc/platforms/4xx/alpr.c +0
-0ppc_md.restart = alpr_restart; }
...
Quoted 21 lines
Quoted 11 lines
arch/ppc/platforms/4xx/katmai.c +7
-0+#ifdef CONFIG_L2_CACHE +static void __init katmai_init (void ) +{ +ibm440gx_l2c_setup (&clocks); +} +#endif +void __init platform_init (unsigned long r3,unsigned long r4,unsigned long r5,unsigned long r6,unsigned long r7) {arch/ppc/platforms/4xx/katmai.c void __init platform_init(unsigned long r3, unsigned long r4, · line 612
Quoted 6 lines
arch/ppc/platforms/4xx/katmai.c +3
-0@@ -599,4 +607,7 @@ void __init platform_init(unsigned long r3, unsigned long r4, ppc_md.early_serial_map = katmai_early_serial_map;#endif ppc_md.restart = katmai_restart; +#ifdef CONFIG_L2_CACHE + ppc_md.init = katmai_init; +#endif See comment above. Should the above init be called for all configs, not just when
L2_CACHEis enabled?
Quoted 2 lines
Also, it looks like the init function is the same on every board. It would be better to make a common function instead of duplicating it everywhere.
Agree, but perhaps it's not the case for the ppc branch. Will do this in the powerpc branch as soon as support for these boards will be ported there.. by someone :)
Regards,
Yuri
Signature · 2 lines
Yuri Tikhonov, Senior Software Engineer Emcraft Systems, www.emcraft.com
BTW... Do you know why we can't just enable HW snoop ? The 440SPe documentation seems to indicate that this is supported by the L2 cache via snooping on the PLB.
Cheers,
Ben.
Quoted 3 lines · Benjamin Herrenschmidt
BTW... Do you know why we can't just enable HW snoop ? The 440SPe documentation seems to indicate that this is supported by the L2 cache via snooping on the PLB.
Unless something has been changed significantly in the 44x port, but L2 cache code I wrote for 440GX did exactly this - we never needed any manual L2 cache management at all.
Signature · 1 line
Eugene
Quoted 8 lines · Eugene Surovegin
Quoted 3 lines · Benjamin Herrenschmidt
BTW... Do you know why we can't just enable HW snoop ? The 440SPe documentation seems to indicate that this is supported by the L2 cache via snooping on the PLB.
Unless something has been changed significantly in the 44x port, but L2 cache code I wrote for 440GX did exactly this - we never needed any manual L2 cache management at all.
Ah good. So we should port that code over instead.
Thanks !
Ben.