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Add support for Freescale QUICCEngine UART

PATCH New Timur Tabi 2 participants 7 messages Jan 9, 2008 – Jan 18, 2008

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Timur Tabi

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#0 lore raw

cover Add support for Freescale QUICCEngine UART

This patchset creates a new serial device driver for the Freescale QE.

Part 1 of this patch set contains all the PowerPC-specific changes.

Part 2 contains all the actual driver and changes for Kconfig and Makefile.

The PowerPC portions of this patchset have already been reviewed and approved. I'd like someone from linux-serial to review the actual driver itself.

author
#1 lore raw

PATCH 1/1 qe: add support for Freescale QUICCEngine UART

Add support for UART serial ports using a Freescale QUICCEngine. Update booting-without-of.txt to define new properties for a QE UART node. Update the MPC8323E-MDS device tree to add UCC5 as a UART. Update the QE library to support slow UCC devices and modules.

---
 Documentation/powerpc/booting-without-of.txt |    9 ++++-
 arch/powerpc/boot/dts/mpc832x_mds.dts        |   50 ++++++++++++++++++++++++++
 arch/powerpc/sysdev/qe_lib/Kconfig           |    2 +-
 arch/powerpc/sysdev/qe_lib/ucc_slow.c        |   10 +++++-
 4 files changed, 68 insertions(+), 3 deletions(-)
Documentation/powerpc/booting-without-of.txt +8 -1
index 53c2295..7ad221f 100644
@@ -1619,7 +1619,7 @@ platforms are moved over to use the flattened-device-tree model.
 
    Required properties:
    - device_type : should be "network", "hldc", "uart", "transparent"
-    "bisync" or "atm".
+     "bisync", "atm", or "serial".
    - compatible : could be "ucc_geth" or "fsl_atm" and so on.
    - model : should be "UCC".
    - device-id : the ucc number(1-8), corresponding to UCCx in UM.
@@ -1632,6 +1632,13 @@ platforms are moved over to use the flattened-device-tree model.
    - interrupt-parent : the phandle for the interrupt controller that
      services interrupts for this device.
    - pio-handle : The phandle for the Parallel I/O port configuration.
+   - port-number : for UART drivers, the port number to use, between 0 and 3.
+     This usually corresponds to the /dev/ttyQE device, e.g. <0> = /dev/ttyQE0.
+     The port number is added to the minor number of the device.  Unlike the
+     CPM UART driver, the port-number is required for the QE UART driver.
+   - soft-uart : for UART drivers, if specified this means the QE UART device
+     driver should use "Soft-UART" mode, which is needed on some SOCs that have
+     broken UART hardware.  Soft-UART is provided via a microcode upload.
    - rx-clock-name: the UCC receive clock source
      "none": clock source is disabled
      "brg1" through "brg16": clock source is BRG1-BRG16, respectively
arch/powerpc/boot/dts/mpc832x_mds.dts +50 -0

74 lines not on this page · raw message

arch/powerpc/sysdev/qe_lib/Kconfig +1 -1
index f611d34..adc6621 100644
@@ -4,7 +4,7 @@
 
 config UCC_SLOW
 	bool
-	default n
+	default y if SERIAL_QE
 	help
 	  This option provides qe_lib support to UCC slow
 	  protocols: UART, BISYNC, QMC
arch/powerpc/sysdev/qe_lib/ucc_slow.c +9 -1
index 0174b3a..b2870b2 100644
@@ -19,6 +19,7 @@
 #include <linux/stddef.h>
 #include <linux/interrupt.h>
 #include <linux/err.h>
+#include <linux/module.h>
 
 #include <asm/io.h>
 #include <asm/immap_qe.h>
@@ -41,6 +42,7 @@ u32 ucc_slow_get_qe_cr_subblock(int uccs_num)
 	default: return QE_CR_SUBBLOCK_INVALID;
 	}
 }
+EXPORT_SYMBOL(ucc_slow_get_qe_cr_subblock);
 
 void ucc_slow_poll_transmitter_now(struct ucc_slow_private * uccs)
 {
@@ -56,6 +58,7 @@ void ucc_slow_graceful_stop_tx(struct ucc_slow_private * uccs)
 	qe_issue_cmd(QE_GRACEFUL_STOP_TX, id,
 			 QE_CR_PROTOCOL_UNSPECIFIED, 0);
 }
+EXPORT_SYMBOL(ucc_slow_graceful_stop_tx);
 
 void ucc_slow_stop_tx(struct ucc_slow_private * uccs)
 {
@@ -65,6 +68,7 @@ void ucc_slow_stop_tx(struct ucc_slow_private * uccs)
 	id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num);
 	qe_issue_cmd(QE_STOP_TX, id, QE_CR_PROTOCOL_UNSPECIFIED, 0);
 }
+EXPORT_SYMBOL(ucc_slow_stop_tx);
 
 void ucc_slow_restart_tx(struct ucc_slow_private * uccs)
 {
@@ -74,6 +78,7 @@ void ucc_slow_restart_tx(struct ucc_slow_private * uccs)
 	id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num);
 	qe_issue_cmd(QE_RESTART_TX, id, QE_CR_PROTOCOL_UNSPECIFIED, 0);
 }
+EXPORT_SYMBOL(ucc_slow_restart_tx);
 
 void ucc_slow_enable(struct ucc_slow_private * uccs, enum comm_dir mode)
 {
@@ -94,6 +99,7 @@ void ucc_slow_enable(struct ucc_slow_private * uccs, enum comm_dir mode)
 	}
 	out_be32(&us_regs->gumr_l, gumr_l);
 }
+EXPORT_SYMBOL(ucc_slow_enable);
 
 void ucc_slow_disable(struct ucc_slow_private * uccs, enum comm_dir mode)
 {
@@ -114,6 +120,7 @@ void ucc_slow_disable(struct ucc_slow_private * uccs, enum comm_dir mode)
 	}
 	out_be32(&us_regs->gumr_l, gumr_l);
 }
+EXPORT_SYMBOL(ucc_slow_disable);
 
 /* Initialize the UCC for Slow operations
  *
@@ -347,6 +354,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
 	*uccs_ret = uccs;
 	return 0;
 }
+EXPORT_SYMBOL(ucc_slow_init);
 
 void ucc_slow_free(struct ucc_slow_private * uccs)
 {
@@ -366,5 +374,5 @@ void ucc_slow_free(struct ucc_slow_private * uccs)
 
 	kfree(uccs);
 }
-
+EXPORT_SYMBOL(ucc_slow_free);
 
Signature · 1 line
1.5.2.4
author
#2 lore raw

PATCH 1/1 qe-uart: add support for Freescale QUICCEngine UART

Add file ucc_uart.c, a serial device driver for the Freescale QUICCEngine. Update the Kconfig and Makefile accordingly.

---
 drivers/serial/Kconfig    |   10 +
 drivers/serial/Makefile   |    1 +
 drivers/serial/ucc_uart.c | 1507 +++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 1518 insertions(+), 0 deletions(-)
 create mode 100644 drivers/serial/ucc_uart.c
drivers/serial/Kconfig +10 -0
index d7e1996..d962b74 100644
@@ -1284,4 +1284,14 @@ config SERIAL_OF_PLATFORM
 	  Currently, only 8250 compatible ports are supported, but
 	  others can easily be added.
 
+config SERIAL_QE
+	tristate "Freescale QUICC Engine serial port support"
+	depends on QUICC_ENGINE
+	select SERIAL_CORE
+	select FW_LOADER
+	default n
+	help
+	  This driver supports the QE serial ports on Freescale embedded
+	  PowerPC that contain a QUICC Engine.
+
 endmenu
drivers/serial/Makefile +1 -0
index af6377d..7eb4553 100644
@@ -64,3 +64,4 @@ obj-$(CONFIG_SERIAL_UARTLITE) += uartlite.o
 obj-$(CONFIG_SERIAL_NETX) += netx-serial.o
 obj-$(CONFIG_SERIAL_OF_PLATFORM) += of_serial.o
 obj-$(CONFIG_SERIAL_KS8695) += serial_ks8695.o
+obj-$(CONFIG_SERIAL_QE) += ucc_uart.o
drivers/serial/ucc_uart.c new file +1507 -0

1,507 lines not on this page · raw message

Signature · 1 line
1.5.2.4
#3 lore raw

Re: [PATCH] [SERIAL] qe-uart: add support for Freescale QUICCEngine UART

Quoted 40 lines · Timur Tabi

Add file ucc_uart.c, a serial device driver for the Freescale QUICCEngine. Update the Kconfig and Makefile accordingly.

---

drivers/serial/Kconfig    |   10 +
drivers/serial/Makefile   |    1 +
drivers/serial/ucc_uart.c | 1507 ++++++++++++++++++++++++++++++++++++ 
+++++++++
3 files changed, 1518 insertions(+), 0 deletions(-)

create mode 100644 drivers/serial/ucc_uart.c

drivers/serial/ucc_uart.c new file +6 -0
new file mode 100644
index 0000000..6fe4cfc
@@ -0,0 +1,1507 @@
+/*
+ * Freescale QUICC Engine UART device driver
+ *
+ * Author: Timur Tabi <[email protected]>
+ *
+ * Copyright 2007 Freescale Semiconductor, Inc.  This file is  

licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ * This driver adds support for UART devices via Freescale's QUICC Engine
+ * found on some Freescale SOCs.
+ *
+ * If Soft-UART support is needed but not already present, then this driver

Quoted 8 lines

+ * will request and upload the "Soft-UART" microcode upon probe. The
+ * filename of the microcode should be fsl_qe_ucode_uart_X_YZ.bin, where "X"
+ * is the name of the SOC (e.g. 8323), and YZ is the revision of the SOC,
+ * (e.g. "11" for 1.1).
+ */
+

what is the define for? you commented all the others :)

Quoted 37 lines
drivers/serial/ucc_uart.c new file +36 -0
+#define UCC_WAIT_CLOSING 100
+
+struct ucc_uart_pram {
+	struct ucc_slow_pram common;
+	u8 res1[8];     	/* reserved */
+	__be16 maxidl;  	/* Maximum idle chars */
+	__be16 idlc;    	/* temp idle counter */
+	__be16 brkcr;   	/* Break count register */
+	__be16 parec;   	/* receive parity error counter */
+	__be16 frmec;   	/* receive framing error counter */
+	__be16 nosec;   	/* receive noise counter */
+	__be16 brkec;   	/* receive break condition counter */
+	__be16 brkln;   	/* last received break length */
+	__be16 uaddr[2];	/* UART address character 1 & 2 */
+	__be16 rtemp;   	/* Temp storage */
+	__be16 toseq;   	/* Transmit out of sequence char */
+	__be16 cchars[8];       /* control characters 1-8 */
+	__be16 rccm;    	/* receive control character mask */
+	__be16 rccr;    	/* receive control character register */
+	__be16 rlbc;    	/* receive last break character */
+	__be16 res2;    	/* reserved */
+	__be32 res3;    	/* reserved, should be cleared */
+	u8 res4;		/* reserved, should be cleared */
+	u8 res5[3];     	/* reserved, should be cleared */
+	__be32 res6;    	/* reserved, should be cleared */
+	__be32 res7;    	/* reserved, should be cleared */
+	__be32 res8;    	/* reserved, should be cleared */
+	__be32 res9;    	/* reserved, should be cleared */
+	__be32 res10;   	/* reserved, should be cleared */
+	__be32 res11;   	/* reserved, should be cleared */
+	__be32 res12;   	/* reserved, should be cleared */
+	__be32 res13;   	/* reserved, should be cleared */
+/* The rest is for Soft-UART only */
+	__be16 supsmr;  	/* 0x90, Shadow UPSMR */
+	__be16 res92;   	/* 0x92, reserved, initialize to 0 */
+	__be32 rx_state;	/* 0x94, RX state, initialize to 0 */

drivers/serial/ucc_uart.c line 123

Quoted 10 lines
drivers/serial/ucc_uart.c new file +10 -0
+	__be32 rx_cnt;  	/* 0x98, RX count, initialize to 0 */
+	u8 rx_length;   	/* 0x9C, Char length, set to 1+CL+PEN+1+SL */
+	u8 rx_bitmark;  	/* 0x9D, reserved, initialize to 0 */
+	u8 rx_temp_dlst_qe;     /* 0x9E, reserved, initialize to 0 */
+	u8 res14[0xBC - 0x9F];  /* reserved */
+	__be32 dump_ptr;	/* 0xBC, Dump pointer */
+	__be32 rx_frame_rem;    /* 0xC0, reserved, initialize to 0 */
+	u8 rx_frame_rem_size;   /* 0xC4, reserved, initialize to 0 */
+	u8 tx_mode;     	/* 0xC5, mode, 0=AHDLC, 1=UART */
+	u16 tx_state;   	/* 0xC6, TX state */

__be16?

Quoted 18 lines
drivers/serial/ucc_uart.c new file +10 -0
+	u8 res15[0xD0 - 0xC8];  /* reserved */
+	__be32 resD0;   	/* 0xD0, reserved, initialize to 0 */
+	u8 resD4;       	/* 0xD4, reserved, initialize to 0 */
+	__be16 resD5;   	/* 0xD5, reserved, initialize to 0 */
+} __attribute__ ((packed));
+
 
 
 
 
+/*
+ * Set the modem control lines
+ *
+ * We currently don't support setting modem control lines, but this  

function
+ * needs to exist, otherwise the kernel will panic.
+ */

drivers/serial/ucc_uart.c line 275

Quoted 3 lines
drivers/serial/ucc_uart.c new file +3 -0
+void qe_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
+{
+}

What's the issue w/support of this? (maybe a comment related to why its not supported -- if not here in the git commit message)

drivers/serial/ucc_uart.c

Quoted 9 lines

+/*
+ * Enable status change interrupts
+ *
+ * We don't support status change interrupts, but we need to define this
+ * function otherwise the kernel will panic.
+ */

drivers/serial/ucc_uart.c new file +2 -0
+static void qe_uart_enable_ms(struct uart_port *port)
+{

same question as above.

- k

author
#4 lore raw

Re: [PATCH] [SERIAL] qe-uart: add support for Freescale QUICCEngine UART

Quoted 1 line · Kumar Gala

what is the define for? you commented all the others :)

I thought you said there were no more issues? :-)

Quoted 1 line
Quoted 1 line

+#define UCC_WAIT_CLOSING 100

This is how long to wait after receiving a close request for characters to be sent out before actually closing the device. I just used the same value as the CPM serial driver.

Quoted 3 lines
Quoted 1 line

+ u16 tx_state; /* 0xC6, TX state */

__be16?

Oops.

Quoted 4 lines
Quoted 4 lines

+/*
+ * Set the modem control lines
+ *
+ * We currently don't support setting modem control lines, but this

Quoted 8 lines

drivers/serial/ucc_uart.c line 275

Quoted 6 lines

function
+ * needs to exist, otherwise the kernel will panic.
+ */

drivers/serial/ucc_uart.c new file +3 -0
+void qe_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
+{
+}

What's the issue w/support of this? (maybe a comment related to why its not supported -- if not here in the git commit message)

I didn't want to add any serial functionality that wasn't in the CPM serial driver, mostly because I don't really understand the technical details of serial communication at this level. I figured if it's okay for the CPM driver not to handle modem control, then the QE driver doesn't have to do it either.

Quoted 4 lines

Review

Quoted 2 lines
(quoted diff) +2 -0
+static void qe_uart_enable_ms(struct uart_port *port)
+{

same question as above.

Same answer!

I suppose you want me to post another version of this patch?

Signature · 2 lines
Timur Tabi
Linux kernel developer at Freescale
#5 lore raw

Re: [PATCH] [SERIAL] qe-uart: add support for Freescale QUICCEngine UART

Quoted 5 lines · Timur Tabi
Quoted 1 line · Kumar Gala

what is the define for? you commented all the others :)

I thought you said there were no more issues? :-)

I lied, get use to it ;)

(I was going to apply the patch and thus scanned over it).

Quoted 5 lines
Quoted 3 lines
Quoted 3 lines

+#define UCC_WAIT_CLOSING 100

This is how long to wait after receiving a close request for characters to be sent out before actually closing the device. I just used the same value as the CPM serial driver.

Yeah, I just meant a comment to this fact would be nice.

Quoted 20 lines
Quoted 5 lines
Quoted 4 lines

+ u16 tx_state; /* 0xC6, TX state */

__be16?

Oops.

Quoted 11 lines

drivers/serial/ucc_uart.c line 275

Quoted 10 lines

+/*
+ * Set the modem control lines
+ *
+ * We currently don't support setting modem control lines, but this function
+ * needs to exist, otherwise the kernel will panic.
+ */

drivers/serial/ucc_uart.c new file +3 -0
+void qe_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
+{
+}

What's the issue w/support of this? (maybe a comment related to why its not supported -- if not here in the git commit message)

Quoted 1 line

I didn't want to add any serial functionality that wasn't in the CPM serial driver, mostly because I don't really understand the technical details of serial communication at this level. I figured if it's okay for the CPM driver not to handle modem control, then the QE driver doesn't have to do it either.

This is fine, can we make it clear that we aren't implementing them because we didn't need them not because of some board issue. (Looking at the 8250.c driver it looks like this has to do with CTS support -- which the QE UCC supports, we just aren't using).

Quoted 7 lines
Quoted 3 lines

Review

Quoted 2 lines
(quoted diff) +2 -0
+static void qe_uart_enable_ms(struct uart_port *port)
+{

same question as above.

Same answer!

I suppose you want me to post another version of this patch?

yes.

- k

Applied
#6 lore raw

Re: [PATCH] [POWERPC] qe: add support for Freescale QUICCEngine UART

In reply to Timur Tabi
Quoted 5 lines · Timur Tabi

Add support for UART serial ports using a Freescale QUICCEngine. Update booting-without-of.txt to define new properties for a QE UART node. Update the MPC8323E-MDS device tree to add UCC5 as a UART. Update the QE library to support slow UCC devices and modules.

Quoted 8 lines
---
 Documentation/powerpc/booting-without-of.txt |    9 ++++-
 arch/powerpc/boot/dts/mpc832x_mds.dts        |   50 ++++++++++++++++++++++++++
 arch/powerpc/sysdev/qe_lib/Kconfig           |    2 +-
 arch/powerpc/sysdev/qe_lib/ucc_slow.c        |   10 +++++-
 4 files changed, 68 insertions(+), 3 deletions(-)

applied.

- k