Add Tegra238 and Tegra264 pinctrl support

new file mode 100644
index 000000000000..0521ba4d55f0
@@ -0,0 +1,78 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra238-pinmux-aon.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra238 AON Pinmux Controller
+
+maintainers:
+  - Thierry Reding <[email protected]>
+  - Jon Hunter <[email protected]>
+
+properties:
+  compatible:
+    const: nvidia,tegra238-pinmux-aon
+
+  reg:
+    maxItems: 1
+
+patternProperties:
+  "^pinmux(-[a-z0-9-]+)?$":
+    type: object
+
+    # pin groups
+    additionalProperties:
+      $ref: nvidia,tegra238-pinmux-common.yaml
+
+      properties:
+        nvidia,pins:
+          items:
+            enum: [ bootv_ctl_n_paa0, soc_gpio00_paa1, vcomp_alert_paa2,
+                    pwm1_paa3, batt_oc_paa4, soc_gpio04_paa5,
+                    soc_gpio25_paa6, soc_gpio26_paa7,
+                    hdmi_cec_pbb0,
+                    spi2_sck_pcc0, spi2_miso_pcc1, spi2_mosi_pcc2,
+                    spi2_cs0_pcc3, spi2_cs1_pcc4, uart3_tx_pcc5,
+                    uart3_rx_pcc6, gen2_i2c_scl_pcc7,
+                    gen2_i2c_sda_pdd0, gen8_i2c_scl_pdd1,
+                    gen8_i2c_sda_pdd2, touch_clk_pdd3, dmic1_clk_pdd4,
+                    dmic1_dat_pdd5, soc_gpio19_pdd6, pwm2_pdd7,
+                    pwm3_pee0, pwm7_pee1,
+                    # drive groups (ordered PAA, PBB, PCC, PDD, PEE)
+                    drive_bootv_ctl_n_paa0, drive_soc_gpio00_paa1,
+                    drive_vcomp_alert_paa2, drive_pwm1_paa3,
+                    drive_batt_oc_paa4, drive_soc_gpio04_paa5,
+                    drive_soc_gpio25_paa6, drive_soc_gpio26_paa7,
+                    drive_hdmi_cec_pbb0,
+                    drive_spi2_sck_pcc0, drive_spi2_miso_pcc1,
+                    drive_spi2_mosi_pcc2, drive_spi2_cs0_pcc3,
+                    drive_spi2_cs1_pcc4, drive_uart3_tx_pcc5,
+                    drive_uart3_rx_pcc6, drive_gen2_i2c_scl_pcc7,
+                    drive_gen2_i2c_sda_pdd0, drive_gen8_i2c_scl_pdd1,
+                    drive_gen8_i2c_sda_pdd2, drive_touch_clk_pdd3,
+                    drive_dmic1_clk_pdd4, drive_dmic1_dat_pdd5,
+                    drive_soc_gpio19_pdd6, drive_pwm2_pdd7,
+                    drive_pwm3_pee0, drive_pwm7_pee1 ]
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/pinctrl/pinctrl-tegra.h>
+
+    pinmux@c300000 {
+      compatible = "nvidia,tegra238-pinmux-aon";
+      reg = <0x0c300000 0x4000>;
+
+      pinctrl-names = "cec";
+      pinctrl-0 = <&cec_state>;
+
+      cec_state: pinmux-cec {
+        cec {
+          nvidia,pins = "hdmi_cec_pbb0";
+          nvidia,function = "hdmi_cec";
+        };
+      };
+    };
+...

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index 660d101ea367..ccb8c337b4ee 100644
@@ -36,6 +36,15 @@ config PINCTRL_TEGRA234
 	bool
 	select PINCTRL_TEGRA
 
+config PINCTRL_TEGRA238
+	tristate "NVIDIA Tegra238 pinctrl driver"
+	select PINCTRL_TEGRA
+	help
+	  Say Y or M here to enable support for the pinctrl driver for
+	  NVIDIA Tegra238 SoC. This driver controls the pin multiplexing
+	  and configuration for the MAIN and AON pin controllers found
+	  on Tegra238.
+
 config PINCTRL_TEGRA_XUSB
 	def_bool y if ARCH_TEGRA
 	select GENERIC_PHY

index 82176526549e..ce700bbcbf6e 100644
@@ -8,4 +8,5 @@ obj-$(CONFIG_PINCTRL_TEGRA210)		+= pinctrl-tegra210.o
 obj-$(CONFIG_PINCTRL_TEGRA186)		+= pinctrl-tegra186.o
 obj-$(CONFIG_PINCTRL_TEGRA194)		+= pinctrl-tegra194.o
 obj-$(CONFIG_PINCTRL_TEGRA234)		+= pinctrl-tegra234.o
+obj-$(CONFIG_PINCTRL_TEGRA238)		+= pinctrl-tegra238.o
 obj-$(CONFIG_PINCTRL_TEGRA_XUSB)	+= pinctrl-tegra-xusb.o

new file mode 100644
index 000000000000..321a187dbe4a
@@ -0,0 +1,76 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra264-pinmux-aon.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra264 AON Pinmux Controller
+
+maintainers:
+  - Thierry Reding <[email protected]>
+  - Jon Hunter <[email protected]>
+
+properties:
+  compatible:
+    const: nvidia,tegra264-pinmux-aon
+
+  reg:
+    maxItems: 1
+
+patternProperties:
+  "^pinmux(-[a-z0-9-]+)?$":
+    type: object
+
+    # pin groups
+    additionalProperties:
+      $ref: nvidia,tegra264-pinmux-common.yaml
+
+      properties:
+        nvidia,pins:
+          items:
+            enum: [ soc_gpio00_paa0, vcomp_alert_paa1, ao_retention_n_paa2,
+                    batt_oc_paa3, bootv_ctl_n_paa4, power_on_paa5,
+                    hdmi_cec_paa6, soc_gpio07_paa7, soc_gpio08_pbb0,
+                    soc_gpio09_pbb1, gen2_i2c_scl_pcc0, gen2_i2c_sda_pcc1,
+                    gen3_i2c_scl_pcc2, gen3_i2c_sda_pcc3, gp_pwm4_pcc4,
+                    uart0_tx_pcc5, uart0_rx_pcc6, spi2_sck_pcc7,
+                    spi2_miso_pdd0, spi2_mosi_pdd1, spi2_cs0_n_pdd2,
+                    soc_gpio21_pdd3, soc_gpio22_pdd4, soc_gpio23_pdd5,
+                    soc_gpio24_pdd6, soc_gpio25_pdd7, soc_gpio26_pee0,
+                    soc_gpio27_pee1, soc_gpio28_pee2, soc_gpio29_pee3,
+                    drive_ao_retention_n_paa2, drive_batt_oc_paa3,
+                    drive_power_on_paa5, drive_vcomp_alert_paa1,
+                    drive_bootv_ctl_n_paa4, drive_soc_gpio00_paa0,
+                    drive_soc_gpio07_paa7, drive_soc_gpio08_pbb0,
+                    drive_soc_gpio09_pbb1, drive_hdmi_cec_paa6,
+                    drive_gen2_i2c_scl_pcc0, drive_gen2_i2c_sda_pcc1,
+                    drive_gen3_i2c_scl_pcc2, drive_gen3_i2c_sda_pcc3,
+                    drive_gp_pwm4_pcc4, drive_uart0_tx_pcc5,
+                    drive_uart0_rx_pcc6, drive_spi2_sck_pcc7,
+                    drive_spi2_miso_pdd0, drive_spi2_mosi_pdd1,
+                    drive_spi2_cs0_n_pdd2, drive_soc_gpio21_pdd3,
+                    drive_soc_gpio22_pdd4, drive_soc_gpio23_pdd5,
+                    drive_soc_gpio24_pdd6, drive_soc_gpio25_pdd7,
+                    drive_soc_gpio26_pee0, drive_soc_gpio27_pee1,
+                    drive_soc_gpio28_pee2, drive_soc_gpio29_pee3 ]
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/pinctrl/pinctrl-tegra.h>
+
+    pinmux@c7a2000 {
+        compatible = "nvidia,tegra264-pinmux-aon";
+        reg = <0xc7a2000 0x2000>;
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&state_default>;
+
+        state_default: pinmux-default {
+            uart0 {
+                nvidia,pins = "uart0_tx_pcc5";
+                nvidia,function = "uarta_txd";
+            };
+        };
+    };

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index ccb8c337b4ee..d26202895997 100644
@@ -45,6 +45,15 @@ config PINCTRL_TEGRA238
 	  and configuration for the MAIN and AON pin controllers found
 	  on Tegra238.
 
+config PINCTRL_TEGRA264
+	tristate "NVIDIA Tegra264 pinctrl driver"
+	select PINCTRL_TEGRA
+	help
+	  Say Y or M here to enable support for the pinctrl driver for
+	  NVIDIA Tegra264 SoC. This driver controls the pin multiplexing
+	  and configuration for the MAIN, AON and UPHY pin controllers found
+	  on Tegra264.
+
 config PINCTRL_TEGRA_XUSB
 	def_bool y if ARCH_TEGRA
 	select GENERIC_PHY

index ce700bbcbf6e..71ade768bf9c 100644
@@ -9,4 +9,5 @@ obj-$(CONFIG_PINCTRL_TEGRA186)		+= pinctrl-tegra186.o
 obj-$(CONFIG_PINCTRL_TEGRA194)		+= pinctrl-tegra194.o
 obj-$(CONFIG_PINCTRL_TEGRA234)		+= pinctrl-tegra234.o
 obj-$(CONFIG_PINCTRL_TEGRA238)		+= pinctrl-tegra238.o
+obj-$(CONFIG_PINCTRL_TEGRA264)		+= pinctrl-tegra264.o
 obj-$(CONFIG_PINCTRL_TEGRA_XUSB)	+= pinctrl-tegra-xusb.o

index dd1ac01ee29b..f525670d3b84 100644
@@ -711,6 +711,8 @@ CONFIG_PINCTRL_SC8280XP_LPASS_LPI=m
 CONFIG_PINCTRL_SM8550_LPASS_LPI=m
 CONFIG_PINCTRL_SM8650_LPASS_LPI=m
 CONFIG_PINCTRL_SOPHGO_SG2000=y
+CONFIG_PINCTRL_TEGRA238=m
+CONFIG_PINCTRL_TEGRA264=m
 CONFIG_GPIO_ALTERA=m
 CONFIG_GPIO_CADENCE=m
 CONFIG_GPIO_DAVINCI=y

new file mode 100644
index 000000000000..ab9264d87c88
@@ -0,0 +1,82 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra238-pinmux-aon.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra238 AON Pinmux Controller
+
+maintainers:
+  - Thierry Reding <[email protected]>
+  - Jon Hunter <[email protected]>
+
+properties:
+  compatible:
+    const: nvidia,tegra238-pinmux-aon
+
+  reg:
+    maxItems: 1
+
+patternProperties:
+  "^pinmux(-[a-z0-9-]+)?$":
+    type: object
+
+    # pin groups
+    additionalProperties:
+      $ref: nvidia,tegra238-pinmux-common.yaml
+
+      properties:
+        nvidia,pins:
+          items:
+            enum: [ bootv_ctl_n_paa0, soc_gpio00_paa1, vcomp_alert_paa2,
+                    pwm1_paa3, batt_oc_paa4, soc_gpio04_paa5,
+                    soc_gpio25_paa6, soc_gpio26_paa7,
+                    hdmi_cec_pbb0,
+                    spi2_sck_pcc0, spi2_miso_pcc1, spi2_mosi_pcc2,
+                    spi2_cs0_pcc3, spi2_cs1_pcc4, uart3_tx_pcc5,
+                    uart3_rx_pcc6, gen2_i2c_scl_pcc7,
+                    gen2_i2c_sda_pdd0, gen8_i2c_scl_pdd1,
+                    gen8_i2c_sda_pdd2, touch_clk_pdd3, dmic1_clk_pdd4,
+                    dmic1_dat_pdd5, soc_gpio19_pdd6, pwm2_pdd7,
+                    pwm3_pee0, pwm7_pee1,
+                    # drive groups (ordered PAA, PBB, PCC, PDD, PEE)
+                    drive_bootv_ctl_n_paa0, drive_soc_gpio00_paa1,
+                    drive_vcomp_alert_paa2, drive_pwm1_paa3,
+                    drive_batt_oc_paa4, drive_soc_gpio04_paa5,
+                    drive_soc_gpio25_paa6, drive_soc_gpio26_paa7,
+                    drive_hdmi_cec_pbb0,
+                    drive_spi2_sck_pcc0, drive_spi2_miso_pcc1,
+                    drive_spi2_mosi_pcc2, drive_spi2_cs0_pcc3,
+                    drive_spi2_cs1_pcc4, drive_uart3_tx_pcc5,
+                    drive_uart3_rx_pcc6, drive_gen2_i2c_scl_pcc7,
+                    drive_gen2_i2c_sda_pdd0, drive_gen8_i2c_scl_pdd1,
+                    drive_gen8_i2c_sda_pdd2, drive_touch_clk_pdd3,
+                    drive_dmic1_clk_pdd4, drive_dmic1_dat_pdd5,
+                    drive_soc_gpio19_pdd6, drive_pwm2_pdd7,
+                    drive_pwm3_pee0, drive_pwm7_pee1 ]
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/pinctrl/pinctrl-tegra.h>
+
+    pinmux@c300000 {
+      compatible = "nvidia,tegra238-pinmux-aon";
+      reg = <0x0c300000 0x4000>;
+
+      pinctrl-names = "cec";
+      pinctrl-0 = <&cec_state>;
+
+      cec_state: pinmux-cec {
+        cec {
+          nvidia,pins = "hdmi_cec_pbb0";
+          nvidia,function = "hdmi_cec";
+        };
+      };
+    };
+...

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index 660d101ea367..cb3a7ab02e72 100644
@@ -36,6 +36,16 @@ config PINCTRL_TEGRA234
 	bool
 	select PINCTRL_TEGRA
 
+config PINCTRL_TEGRA238
+	tristate "NVIDIA Tegra238 pinctrl driver"
+	default m if ARCH_TEGRA_238_SOC
+	select PINCTRL_TEGRA
+	help
+	  Say Y or M here to enable support for the pinctrl driver for
+	  NVIDIA Tegra238 SoC. This driver controls the pin multiplexing
+	  and configuration for the MAIN and AON pin controllers found
+	  on Tegra238.
+
 config PINCTRL_TEGRA_XUSB
 	def_bool y if ARCH_TEGRA
 	select GENERIC_PHY

index 82176526549e..ce700bbcbf6e 100644
@@ -8,4 +8,5 @@ obj-$(CONFIG_PINCTRL_TEGRA210)		+= pinctrl-tegra210.o
 obj-$(CONFIG_PINCTRL_TEGRA186)		+= pinctrl-tegra186.o
 obj-$(CONFIG_PINCTRL_TEGRA194)		+= pinctrl-tegra194.o
 obj-$(CONFIG_PINCTRL_TEGRA234)		+= pinctrl-tegra234.o
+obj-$(CONFIG_PINCTRL_TEGRA238)		+= pinctrl-tegra238.o
 obj-$(CONFIG_PINCTRL_TEGRA_XUSB)	+= pinctrl-tegra-xusb.o

new file mode 100644
index 000000000000..682e6510ed45
@@ -0,0 +1,80 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra264-pinmux-aon.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra264 AON Pinmux Controller
+
+maintainers:
+  - Thierry Reding <[email protected]>
+  - Jon Hunter <[email protected]>
+
+properties:
+  compatible:
+    const: nvidia,tegra264-pinmux-aon
+
+  reg:
+    maxItems: 1
+
+patternProperties:
+  "^pinmux(-[a-z0-9-]+)?$":
+    type: object
+
+    # pin groups
+    additionalProperties:
+      $ref: nvidia,tegra264-pinmux-common.yaml
+
+      properties:
+        nvidia,pins:
+          items:
+            enum: [ soc_gpio00_paa0, vcomp_alert_paa1, ao_retention_n_paa2,
+                    batt_oc_paa3, bootv_ctl_n_paa4, power_on_paa5,
+                    hdmi_cec_paa6, soc_gpio07_paa7, soc_gpio08_pbb0,
+                    soc_gpio09_pbb1, gen2_i2c_scl_pcc0, gen2_i2c_sda_pcc1,
+                    gen3_i2c_scl_pcc2, gen3_i2c_sda_pcc3, gp_pwm4_pcc4,
+                    uart0_tx_pcc5, uart0_rx_pcc6, spi2_sck_pcc7,
+                    spi2_miso_pdd0, spi2_mosi_pdd1, spi2_cs0_n_pdd2,
+                    soc_gpio21_pdd3, soc_gpio22_pdd4, soc_gpio23_pdd5,
+                    soc_gpio24_pdd6, soc_gpio25_pdd7, soc_gpio26_pee0,
+                    soc_gpio27_pee1, soc_gpio28_pee2, soc_gpio29_pee3,
+                    drive_ao_retention_n_paa2, drive_batt_oc_paa3,
+                    drive_power_on_paa5, drive_vcomp_alert_paa1,
+                    drive_bootv_ctl_n_paa4, drive_soc_gpio00_paa0,
+                    drive_soc_gpio07_paa7, drive_soc_gpio08_pbb0,
+                    drive_soc_gpio09_pbb1, drive_hdmi_cec_paa6,
+                    drive_gen2_i2c_scl_pcc0, drive_gen2_i2c_sda_pcc1,
+                    drive_gen3_i2c_scl_pcc2, drive_gen3_i2c_sda_pcc3,
+                    drive_gp_pwm4_pcc4, drive_uart0_tx_pcc5,
+                    drive_uart0_rx_pcc6, drive_spi2_sck_pcc7,
+                    drive_spi2_miso_pdd0, drive_spi2_mosi_pdd1,
+                    drive_spi2_cs0_n_pdd2, drive_soc_gpio21_pdd3,
+                    drive_soc_gpio22_pdd4, drive_soc_gpio23_pdd5,
+                    drive_soc_gpio24_pdd6, drive_soc_gpio25_pdd7,
+                    drive_soc_gpio26_pee0, drive_soc_gpio27_pee1,
+                    drive_soc_gpio28_pee2, drive_soc_gpio29_pee3 ]
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/pinctrl/pinctrl-tegra.h>
+
+    pinmux@c7a2000 {
+        compatible = "nvidia,tegra264-pinmux-aon";
+        reg = <0xc7a2000 0x2000>;
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&state_default>;
+
+        state_default: pinmux-default {
+            uart0 {
+                nvidia,pins = "uart0_tx_pcc5";
+                nvidia,function = "uarta_txd";
+            };
+        };
+    };

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index 06d8357bdf52..dc7793088d2e 100644
@@ -3380,6 +3380,11 @@ i2c3: i2c@c610000 {
 			status = "disabled";
 		};
 
+		pinmux_aon: pinmux@c7a2000 {
+			compatible = "nvidia,tegra264-pinmux-aon";
+			reg = <0x0 0x0c7a2000 0x0 0x2000>;
+		};
+
 		pmc: pmc@c800000 {
 			compatible = "nvidia,tegra264-pmc";
 			reg = <0x0 0x0c800000 0x0 0x100000>,

@@ -3586,6 +3591,11 @@ pci@c000000 {
 			status = "disabled";
 		};
 
+		pinmux_main: pinmux@c281000 {
+			compatible = "nvidia,tegra264-pinmux-main";
+			reg = <0x00 0x0c281000 0x0 0xc000>;
+		};
+
 		i2c14: i2c@c410000 {
 			compatible = "nvidia,tegra264-i2c";
 			reg = <0x00 0x0c410000 0x0 0x10000>;

@@ -3862,6 +3872,11 @@ bus@a800000000 {
 			 <0x00 0x20000000 0x00 0x20000000 0x00 0x60000000>, /* non-prefetchable memory (32-bit, 1536 GiB) */
 			 <0xa8 0x80000000 0xa8 0x80000000 0x57 0x80000000>; /* I/O, ECAM, prefetchable memory (64-bit) */
 
+		pinmux_uphy: pinmux@82e0000 {
+			compatible = "nvidia,tegra264-pinmux-uphy";
+			reg = <0x00 0x082e0000 0x0 0x4000>;
+		};
+
 		gpio_uphy: gpio@8300000 {
 			compatible = "nvidia,tegra264-gpio-uphy";
 			reg = <0x00 0x08300000 0x0 0x2000>,

index cb3a7ab02e72..54263b4554c0 100644
@@ -46,6 +46,16 @@ config PINCTRL_TEGRA238
 	  and configuration for the MAIN and AON pin controllers found
 	  on Tegra238.
 
+config PINCTRL_TEGRA264
+	tristate "NVIDIA Tegra264 pinctrl driver"
+	default m if ARCH_TEGRA_264_SOC
+	select PINCTRL_TEGRA
+	help
+	  Say Y or M here to enable support for the pinctrl driver for
+	  NVIDIA Tegra264 SoC. This driver controls the pin multiplexing
+	  and configuration for the MAIN, AON and UPHY pin controllers found
+	  on Tegra264.
+
 config PINCTRL_TEGRA_XUSB
 	def_bool y if ARCH_TEGRA
 	select GENERIC_PHY

index ce700bbcbf6e..71ade768bf9c 100644
@@ -9,4 +9,5 @@ obj-$(CONFIG_PINCTRL_TEGRA186)		+= pinctrl-tegra186.o
 obj-$(CONFIG_PINCTRL_TEGRA194)		+= pinctrl-tegra194.o
 obj-$(CONFIG_PINCTRL_TEGRA234)		+= pinctrl-tegra234.o
 obj-$(CONFIG_PINCTRL_TEGRA238)		+= pinctrl-tegra238.o
+obj-$(CONFIG_PINCTRL_TEGRA264)		+= pinctrl-tegra264.o
 obj-$(CONFIG_PINCTRL_TEGRA_XUSB)	+= pinctrl-tegra-xusb.o