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Add Tegra238 and Tegra264 pinctrl support

PATCH Superseded [email protected] 4 participants 28 messages Apr 9 – Apr 21

Subsystems (4)
Device tree bindings GPIO Tegra architecture support Pin control

v1 of 3 Superseded Latest is v3 →

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#0 lore raw

cover Add Tegra238 and Tegra264 pinctrl support

From: Prathamesh Shete <[email protected]>

Add pinctrl driver support for Tegra238 and Tegra264 along with the corresponding device tree binding documentation. Additionally, export tegra_pinctrl_probe() to allow the drivers to be built as loadable modules.

Prathamesh Shete (6):
pinctrl: tegra: Export tegra_pinctrl_probe()
dt-bindings: pinctrl: Document Tegra238 pin controllers
pinctrl: tegra: Add Tegra238 pinmux driver
dt-bindings: pinctrl: Document Tegra264 pin controllers
pinctrl: tegra: Add Tegra264 pinmux driver
arm64: defconfig: make Tegra 238 and Tegra264 Pinctrl a loadable
module

 .../pinctrl/nvidia,tegra238-pinmux-aon.yaml   |   78 +
 .../nvidia,tegra238-pinmux-common.yaml        |   73 +
 .../pinctrl/nvidia,tegra238-pinmux.yaml       |  215 ++
 .../pinctrl/nvidia,tegra264-pinmux-aon.yaml   |   76 +
 .../nvidia,tegra264-pinmux-common.yaml        |   84 +
 .../pinctrl/nvidia,tegra264-pinmux-main.yaml  |  163 ++
 .../pinctrl/nvidia,tegra264-pinmux-uphy.yaml  |   74 +
 arch/arm64/configs/defconfig                  |    2 +
 drivers/pinctrl/tegra/Kconfig                 |   18 +
 drivers/pinctrl/tegra/Makefile                |    2 +
 drivers/pinctrl/tegra/pinctrl-tegra.c         |    2 +
 drivers/pinctrl/tegra/pinctrl-tegra238.c      | 2056 +++++++++++++++
 drivers/pinctrl/tegra/pinctrl-tegra264.c      | 2216 +++++++++++++++++
 13 files changed, 5059 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-aon.yaml
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-common.yaml
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux.yaml
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-aon.yaml
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-common.yaml
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-main.yaml
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-uphy.yaml
 create mode 100644 drivers/pinctrl/tegra/pinctrl-tegra238.c
 create mode 100644 drivers/pinctrl/tegra/pinctrl-tegra264.c
Signature · 1 line
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#1 lore raw

PATCH 1/6 pinctrl: tegra: Export tegra_pinctrl_probe()

From: Prathamesh Shete <[email protected]>

Export tegra_pinctrl_probe() to allow SoC-specific Tegra pinctrl drivers built as modules to use the common probe path.

Signed-off-by Prathamesh Shete <[email protected]>
---
 drivers/pinctrl/tegra/pinctrl-tegra.c | 2 ++
 1 file changed, 2 insertions(+)
drivers/pinctrl/tegra/pinctrl-tegra.c +2 -0
index bac2adeb5c63..3f58f7db525f 100644
@@ -13,6 +13,7 @@
 #include <linux/err.h>
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/module.h>
 #include <linux/of.h>
 #include <linux/platform_device.h>
 #include <linux/seq_file.h>

@@ -936,3 +937,4 @@ int tegra_pinctrl_probe(struct platform_device *pdev,
 
 	return 0;
 }
+EXPORT_SYMBOL_GPL(tegra_pinctrl_probe);
Signature · 1 line
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#2 lore raw

PATCH 2/6 dt-bindings: pinctrl: Document Tegra238 pin controllers

In reply to [email protected]

From: Prathamesh Shete <[email protected]>

Tegra238 contains two pin controllers. Document their compatible strings and describe the list of pins and functions that they provide.

Signed-off-by Prathamesh Shete <[email protected]>
---
 .../pinctrl/nvidia,tegra238-pinmux-aon.yaml   |  78 +++++++
 .../nvidia,tegra238-pinmux-common.yaml        |  73 ++++++
 .../pinctrl/nvidia,tegra238-pinmux.yaml       | 215 ++++++++++++++++++
 3 files changed, 366 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-aon.yaml
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-common.yaml
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux.yaml
Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-aon.yaml new file +78 -0
new file mode 100644
index 000000000000..0521ba4d55f0
@@ -0,0 +1,78 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra238-pinmux-aon.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra238 AON Pinmux Controller
+
+maintainers:
+  - Thierry Reding <[email protected]>
+  - Jon Hunter <[email protected]>
+
+properties:
+  compatible:
+    const: nvidia,tegra238-pinmux-aon
+
+  reg:
+    maxItems: 1
+
+patternProperties:
+  "^pinmux(-[a-z0-9-]+)?$":
+    type: object
+
+    # pin groups
+    additionalProperties:
+      $ref: nvidia,tegra238-pinmux-common.yaml
+
+      properties:
+        nvidia,pins:
+          items:
+            enum: [ bootv_ctl_n_paa0, soc_gpio00_paa1, vcomp_alert_paa2,
+                    pwm1_paa3, batt_oc_paa4, soc_gpio04_paa5,
+                    soc_gpio25_paa6, soc_gpio26_paa7,
+                    hdmi_cec_pbb0,
+                    spi2_sck_pcc0, spi2_miso_pcc1, spi2_mosi_pcc2,
+                    spi2_cs0_pcc3, spi2_cs1_pcc4, uart3_tx_pcc5,
+                    uart3_rx_pcc6, gen2_i2c_scl_pcc7,
+                    gen2_i2c_sda_pdd0, gen8_i2c_scl_pdd1,
+                    gen8_i2c_sda_pdd2, touch_clk_pdd3, dmic1_clk_pdd4,
+                    dmic1_dat_pdd5, soc_gpio19_pdd6, pwm2_pdd7,
+                    pwm3_pee0, pwm7_pee1,
+                    # drive groups (ordered PAA, PBB, PCC, PDD, PEE)
+                    drive_bootv_ctl_n_paa0, drive_soc_gpio00_paa1,
+                    drive_vcomp_alert_paa2, drive_pwm1_paa3,
+                    drive_batt_oc_paa4, drive_soc_gpio04_paa5,
+                    drive_soc_gpio25_paa6, drive_soc_gpio26_paa7,
+                    drive_hdmi_cec_pbb0,
+                    drive_spi2_sck_pcc0, drive_spi2_miso_pcc1,
+                    drive_spi2_mosi_pcc2, drive_spi2_cs0_pcc3,
+                    drive_spi2_cs1_pcc4, drive_uart3_tx_pcc5,
+                    drive_uart3_rx_pcc6, drive_gen2_i2c_scl_pcc7,
+                    drive_gen2_i2c_sda_pdd0, drive_gen8_i2c_scl_pdd1,
+                    drive_gen8_i2c_sda_pdd2, drive_touch_clk_pdd3,
+                    drive_dmic1_clk_pdd4, drive_dmic1_dat_pdd5,
+                    drive_soc_gpio19_pdd6, drive_pwm2_pdd7,
+                    drive_pwm3_pee0, drive_pwm7_pee1 ]
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/pinctrl/pinctrl-tegra.h>
+
+    pinmux@c300000 {
+      compatible = "nvidia,tegra238-pinmux-aon";
+      reg = <0x0c300000 0x4000>;
+
+      pinctrl-names = "cec";
+      pinctrl-0 = <&cec_state>;
+
+      cec_state: pinmux-cec {
+        cec {
+          nvidia,pins = "hdmi_cec_pbb0";
+          nvidia,function = "hdmi_cec";
+        };
+      };
+    };
+...
Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-common.yaml new file +73 -0

73 lines not on this page · raw message

Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux.yaml new file +215 -0

215 lines not on this page · raw message

Signature · 1 line
2.43.0
#3 lore raw

Re: [PATCH 2/6] dt-bindings: pinctrl: Document Tegra238 pin controllers

Quoted 29 lines · On Thu, Apr 09, 2026 at 01:13:36PM +0000, [email protected] wrote:
Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-aon.yaml new file +29 -0
+patternProperties:
+  "^pinmux(-[a-z0-9-]+)?$":
+    type: object
+
+    # pin groups
+    additionalProperties:
+      $ref: nvidia,tegra238-pinmux-common.yaml
+
+      properties:
+        nvidia,pins:
+          items:
+            enum: [ bootv_ctl_n_paa0, soc_gpio00_paa1, vcomp_alert_paa2,
+                    pwm1_paa3, batt_oc_paa4, soc_gpio04_paa5,
+                    soc_gpio25_paa6, soc_gpio26_paa7,
+                    hdmi_cec_pbb0,
+                    spi2_sck_pcc0, spi2_miso_pcc1, spi2_mosi_pcc2,
+                    spi2_cs0_pcc3, spi2_cs1_pcc4, uart3_tx_pcc5,
+                    uart3_rx_pcc6, gen2_i2c_scl_pcc7,
+                    gen2_i2c_sda_pdd0, gen8_i2c_scl_pdd1,
+                    gen8_i2c_sda_pdd2, touch_clk_pdd3, dmic1_clk_pdd4,
+                    dmic1_dat_pdd5, soc_gpio19_pdd6, pwm2_pdd7,
+                    pwm3_pee0, pwm7_pee1,
+                    # drive groups (ordered PAA, PBB, PCC, PDD, PEE)
+                    drive_bootv_ctl_n_paa0, drive_soc_gpio00_paa1,
+                    drive_vcomp_alert_paa2, drive_pwm1_paa3,
+                    drive_batt_oc_paa4, drive_soc_gpio04_paa5,
+                    drive_soc_gpio25_paa6, drive_soc_gpio26_paa7,
+                    drive_hdmi_cec_pbb0,
+                    drive_spi2_sck_pcc0, drive_spi2_miso_pcc1,

Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-aon.yaml line 58

Quoted 10 lines
Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-aon.yaml new file +10 -0
+                    drive_spi2_mosi_pcc2, drive_spi2_cs0_pcc3,
+                    drive_spi2_cs1_pcc4, drive_uart3_tx_pcc5,
+                    drive_uart3_rx_pcc6, drive_gen2_i2c_scl_pcc7,
+                    drive_gen2_i2c_sda_pdd0, drive_gen8_i2c_scl_pdd1,
+                    drive_gen8_i2c_sda_pdd2, drive_touch_clk_pdd3,
+                    drive_dmic1_clk_pdd4, drive_dmic1_dat_pdd5,
+                    drive_soc_gpio19_pdd6, drive_pwm2_pdd7,
+                    drive_pwm3_pee0, drive_pwm7_pee1 ]
+
+unevaluatedProperties: false

additionalProperties. I'll fix existing files.

Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-aon.yaml line 61

Quoted 3 lines
Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-aon.yaml new file +3 -0
+
+examples:
+  - |

Best regards,
Krzysztof

#4 lore raw

Re: [PATCH 2/6] dt-bindings: pinctrl: Document Tegra238 pin controllers

In reply to [email protected]
Quoted 20 lines · On Thu, Apr 09, 2026 at 01:13:36PM +0000, [email protected] wrote:
Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-aon.yaml new file +20 -0
+      properties:
+        nvidia,pins:
+          items:
+            enum: [ bootv_ctl_n_paa0, soc_gpio00_paa1, vcomp_alert_paa2,
+                    pwm1_paa3, batt_oc_paa4, soc_gpio04_paa5,
+                    soc_gpio25_paa6, soc_gpio26_paa7,
+                    hdmi_cec_pbb0,
+                    spi2_sck_pcc0, spi2_miso_pcc1, spi2_mosi_pcc2,
+                    spi2_cs0_pcc3, spi2_cs1_pcc4, uart3_tx_pcc5,
+                    uart3_rx_pcc6, gen2_i2c_scl_pcc7,
+                    gen2_i2c_sda_pdd0, gen8_i2c_scl_pdd1,
+                    gen8_i2c_sda_pdd2, touch_clk_pdd3, dmic1_clk_pdd4,
+                    dmic1_dat_pdd5, soc_gpio19_pdd6, pwm2_pdd7,
+                    pwm3_pee0, pwm7_pee1,
+                    # drive groups (ordered PAA, PBB, PCC, PDD, PEE)
+                    drive_bootv_ctl_n_paa0, drive_soc_gpio00_paa1,
+                    drive_vcomp_alert_paa2, drive_pwm1_paa3,
+                    drive_batt_oc_paa4, drive_soc_gpio04_paa5,
+                    drive_soc_gpio25_paa6, drive_soc_gpio26_paa7,
+                    drive_hdmi_cec_pbb0,

Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-aon.yaml line 57

Quoted 10 lines
Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-aon.yaml new file +10 -0
+                    drive_spi2_sck_pcc0, drive_spi2_miso_pcc1,
+                    drive_spi2_mosi_pcc2, drive_spi2_cs0_pcc3,
+                    drive_spi2_cs1_pcc4, drive_uart3_tx_pcc5,
+                    drive_uart3_rx_pcc6, drive_gen2_i2c_scl_pcc7,
+                    drive_gen2_i2c_sda_pdd0, drive_gen8_i2c_scl_pdd1,
+                    drive_gen8_i2c_sda_pdd2, drive_touch_clk_pdd3,
+                    drive_dmic1_clk_pdd4, drive_dmic1_dat_pdd5,
+                    drive_soc_gpio19_pdd6, drive_pwm2_pdd7,
+                    drive_pwm3_pee0, drive_pwm7_pee1 ]
+

And missing required. I'll also fix existing ones.

Quoted 1 line

+unevaluatedProperties: false

Best regards,
Krzysztof

author
#5 lore raw

PATCH 3/6 pinctrl: tegra: Add Tegra238 pinmux driver

In reply to [email protected]

From: Prathamesh Shete <[email protected]>

This change adds support for the two pin controllers (MAIN and AON) found on Tegra238.

Signed-off-by Prathamesh Shete <[email protected]>
---
 drivers/pinctrl/tegra/Kconfig            |    9 +
 drivers/pinctrl/tegra/Makefile           |    1 +
 drivers/pinctrl/tegra/pinctrl-tegra238.c | 2056 ++++++++++++++++++++++
 3 files changed, 2066 insertions(+)
 create mode 100644 drivers/pinctrl/tegra/pinctrl-tegra238.c
drivers/pinctrl/tegra/Kconfig +9 -0
index 660d101ea367..ccb8c337b4ee 100644
@@ -36,6 +36,15 @@ config PINCTRL_TEGRA234
 	bool
 	select PINCTRL_TEGRA
 
+config PINCTRL_TEGRA238
+	tristate "NVIDIA Tegra238 pinctrl driver"
+	select PINCTRL_TEGRA
+	help
+	  Say Y or M here to enable support for the pinctrl driver for
+	  NVIDIA Tegra238 SoC. This driver controls the pin multiplexing
+	  and configuration for the MAIN and AON pin controllers found
+	  on Tegra238.
+
 config PINCTRL_TEGRA_XUSB
 	def_bool y if ARCH_TEGRA
 	select GENERIC_PHY
drivers/pinctrl/tegra/Makefile +1 -0
index 82176526549e..ce700bbcbf6e 100644
@@ -8,4 +8,5 @@ obj-$(CONFIG_PINCTRL_TEGRA210)		+= pinctrl-tegra210.o
 obj-$(CONFIG_PINCTRL_TEGRA186)		+= pinctrl-tegra186.o
 obj-$(CONFIG_PINCTRL_TEGRA194)		+= pinctrl-tegra194.o
 obj-$(CONFIG_PINCTRL_TEGRA234)		+= pinctrl-tegra234.o
+obj-$(CONFIG_PINCTRL_TEGRA238)		+= pinctrl-tegra238.o
 obj-$(CONFIG_PINCTRL_TEGRA_XUSB)	+= pinctrl-tegra-xusb.o
drivers/pinctrl/tegra/pinctrl-tegra238.c new file +2056 -0

2,056 lines not on this page · raw message

Signature · 1 line
2.43.0
#6 lore raw

Re: [PATCH 3/6] pinctrl: tegra: Add Tegra238 pinmux driver

Quoted 3 lines · On 09/04/2026 15:13, [email protected] wrote:

From: Prathamesh Shete <[email protected]>

This change adds support for the two pin controllers

Please do not use "This commit/patch/change", but imperative mood. See longer explanation here:
https://elixir.bootlin.com/linux/v6.16/source/Documentation/process/submitting-patches.rst#L94

Quoted 16 lines

(MAIN and AON) found on Tegra238.

Signed-off-by Prathamesh Shete <[email protected]>
---
 drivers/pinctrl/tegra/Kconfig            |    9 +
 drivers/pinctrl/tegra/Makefile           |    1 +
 drivers/pinctrl/tegra/pinctrl-tegra238.c | 2056 ++++++++++++++++++++++
 3 files changed, 2066 insertions(+)
 create mode 100644 drivers/pinctrl/tegra/pinctrl-tegra238.c
drivers/pinctrl/tegra/Kconfig +0 -0
index 660d101ea367..ccb8c337b4ee 100644
@@ -36,6 +36,15 @@ config PINCTRL_TEGRA234
 	bool

drivers/pinctrl/tegra/Kconfig config PINCTRL_TEGRA234 · line 46

Quoted 10 lines
drivers/pinctrl/tegra/Kconfig +8 -0
 	select PINCTRL_TEGRA
 
+config PINCTRL_TEGRA238
+	tristate "NVIDIA Tegra238 pinctrl driver"
+	select PINCTRL_TEGRA
+	help
+	  Say Y or M here to enable support for the pinctrl driver for
+	  NVIDIA Tegra238 SoC. This driver controls the pin multiplexing
+	  and configuration for the MAIN and AON pin controllers found
+	  on Tegra238.

All other Tegra drivers are non-selectable, so you are introducing completely different style. This needs explanation WHY in the commit msg.

Also, since you are changing things around, then I suggest to finally enable proper COMPILE_TEST for all tegra pinctrl. Unless I mistaken, it's impossible to compile test currently anything from Tegra pinctrl... Actually let me take a look, maybe I will do it for several platforms.

...

Quoted 9 lines
drivers/pinctrl/tegra/Kconfig +9 -0
+static struct platform_driver tegra238_pinctrl_driver = {
+	.driver = {
+		.name = "tegra238-pinctrl",
+		.of_match_table = tegra238_pinctrl_of_match,
+	},
+	.probe = tegra238_pinctrl_probe,
+};
+
+static int __init tegra238_pinctrl_init(void)

drivers/pinctrl/tegra/Kconfig config PINCTRL_TEGRA234

Quoted 10 lines
drivers/pinctrl/tegra/Kconfig +10 -0
+{
+	return platform_driver_register(&tegra238_pinctrl_driver);
+}
+module_init(tegra238_pinctrl_init);
+
+static void __exit tegra238_pinctrl_exit(void)
+{
+	platform_driver_unregister(&tegra238_pinctrl_driver);
+}
+module_exit(tegra238_pinctrl_exit);

Why this cannot be module_platform_driver()?

Best regards,
Krzysztof

author
#7 lore raw

PATCH 4/6 dt-bindings: pinctrl: Document Tegra264 pin controllers

In reply to [email protected]

From: Prathamesh Shete <[email protected]>

Tegra264 contains three pin controllers. Document their compatible strings and describe the list of pins and functions that they provide.

Signed-off-by Prathamesh Shete <[email protected]>
---
 .../pinctrl/nvidia,tegra264-pinmux-aon.yaml   |  76 ++++++++
 .../nvidia,tegra264-pinmux-common.yaml        |  84 +++++++++
 .../pinctrl/nvidia,tegra264-pinmux-main.yaml  | 163 ++++++++++++++++++
 .../pinctrl/nvidia,tegra264-pinmux-uphy.yaml  |  74 ++++++++
 4 files changed, 397 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-aon.yaml
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-common.yaml
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-main.yaml
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-uphy.yaml
Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-aon.yaml new file +76 -0
new file mode 100644
index 000000000000..321a187dbe4a
@@ -0,0 +1,76 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra264-pinmux-aon.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra264 AON Pinmux Controller
+
+maintainers:
+  - Thierry Reding <[email protected]>
+  - Jon Hunter <[email protected]>
+
+properties:
+  compatible:
+    const: nvidia,tegra264-pinmux-aon
+
+  reg:
+    maxItems: 1
+
+patternProperties:
+  "^pinmux(-[a-z0-9-]+)?$":
+    type: object
+
+    # pin groups
+    additionalProperties:
+      $ref: nvidia,tegra264-pinmux-common.yaml
+
+      properties:
+        nvidia,pins:
+          items:
+            enum: [ soc_gpio00_paa0, vcomp_alert_paa1, ao_retention_n_paa2,
+                    batt_oc_paa3, bootv_ctl_n_paa4, power_on_paa5,
+                    hdmi_cec_paa6, soc_gpio07_paa7, soc_gpio08_pbb0,
+                    soc_gpio09_pbb1, gen2_i2c_scl_pcc0, gen2_i2c_sda_pcc1,
+                    gen3_i2c_scl_pcc2, gen3_i2c_sda_pcc3, gp_pwm4_pcc4,
+                    uart0_tx_pcc5, uart0_rx_pcc6, spi2_sck_pcc7,
+                    spi2_miso_pdd0, spi2_mosi_pdd1, spi2_cs0_n_pdd2,
+                    soc_gpio21_pdd3, soc_gpio22_pdd4, soc_gpio23_pdd5,
+                    soc_gpio24_pdd6, soc_gpio25_pdd7, soc_gpio26_pee0,
+                    soc_gpio27_pee1, soc_gpio28_pee2, soc_gpio29_pee3,
+                    drive_ao_retention_n_paa2, drive_batt_oc_paa3,
+                    drive_power_on_paa5, drive_vcomp_alert_paa1,
+                    drive_bootv_ctl_n_paa4, drive_soc_gpio00_paa0,
+                    drive_soc_gpio07_paa7, drive_soc_gpio08_pbb0,
+                    drive_soc_gpio09_pbb1, drive_hdmi_cec_paa6,
+                    drive_gen2_i2c_scl_pcc0, drive_gen2_i2c_sda_pcc1,
+                    drive_gen3_i2c_scl_pcc2, drive_gen3_i2c_sda_pcc3,
+                    drive_gp_pwm4_pcc4, drive_uart0_tx_pcc5,
+                    drive_uart0_rx_pcc6, drive_spi2_sck_pcc7,
+                    drive_spi2_miso_pdd0, drive_spi2_mosi_pdd1,
+                    drive_spi2_cs0_n_pdd2, drive_soc_gpio21_pdd3,
+                    drive_soc_gpio22_pdd4, drive_soc_gpio23_pdd5,
+                    drive_soc_gpio24_pdd6, drive_soc_gpio25_pdd7,
+                    drive_soc_gpio26_pee0, drive_soc_gpio27_pee1,
+                    drive_soc_gpio28_pee2, drive_soc_gpio29_pee3 ]
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/pinctrl/pinctrl-tegra.h>
+
+    pinmux@c7a2000 {
+        compatible = "nvidia,tegra264-pinmux-aon";
+        reg = <0xc7a2000 0x2000>;
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&state_default>;
+
+        state_default: pinmux-default {
+            uart0 {
+                nvidia,pins = "uart0_tx_pcc5";
+                nvidia,function = "uarta_txd";
+            };
+        };
+    };
Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-common.yaml new file +84 -0

84 lines not on this page · raw message

Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-main.yaml new file +163 -0

163 lines not on this page · raw message

Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-uphy.yaml new file +74 -0

74 lines not on this page · raw message

Signature · 1 line
2.43.0
author
#8 lore raw

PATCH 5/6 pinctrl: tegra: Add Tegra264 pinmux driver

In reply to [email protected]

From: Prathamesh Shete <[email protected]>

Add support for the three pin controllers
(MAIN, UPHY and AON) found on Tegra264.

Signed-off-by Prathamesh Shete <[email protected]>
---
 drivers/pinctrl/tegra/Kconfig            |    9 +
 drivers/pinctrl/tegra/Makefile           |    1 +
 drivers/pinctrl/tegra/pinctrl-tegra264.c | 2216 ++++++++++++++++++++++
 3 files changed, 2226 insertions(+)
 create mode 100644 drivers/pinctrl/tegra/pinctrl-tegra264.c
drivers/pinctrl/tegra/Kconfig +9 -0
index ccb8c337b4ee..d26202895997 100644
@@ -45,6 +45,15 @@ config PINCTRL_TEGRA238
 	  and configuration for the MAIN and AON pin controllers found
 	  on Tegra238.
 
+config PINCTRL_TEGRA264
+	tristate "NVIDIA Tegra264 pinctrl driver"
+	select PINCTRL_TEGRA
+	help
+	  Say Y or M here to enable support for the pinctrl driver for
+	  NVIDIA Tegra264 SoC. This driver controls the pin multiplexing
+	  and configuration for the MAIN, AON and UPHY pin controllers found
+	  on Tegra264.
+
 config PINCTRL_TEGRA_XUSB
 	def_bool y if ARCH_TEGRA
 	select GENERIC_PHY
drivers/pinctrl/tegra/Makefile +1 -0
index ce700bbcbf6e..71ade768bf9c 100644
@@ -9,4 +9,5 @@ obj-$(CONFIG_PINCTRL_TEGRA186)		+= pinctrl-tegra186.o
 obj-$(CONFIG_PINCTRL_TEGRA194)		+= pinctrl-tegra194.o
 obj-$(CONFIG_PINCTRL_TEGRA234)		+= pinctrl-tegra234.o
 obj-$(CONFIG_PINCTRL_TEGRA238)		+= pinctrl-tegra238.o
+obj-$(CONFIG_PINCTRL_TEGRA264)		+= pinctrl-tegra264.o
 obj-$(CONFIG_PINCTRL_TEGRA_XUSB)	+= pinctrl-tegra-xusb.o
drivers/pinctrl/tegra/pinctrl-tegra264.c new file +2216 -0

2,216 lines not on this page · raw message

Signature · 1 line
2.43.0
author
#9 lore raw

PATCH 6/6 arm64: defconfig: make Tegra238 and Tegra264 Pinctrl a loadable module

In reply to [email protected]

From: Prathamesh Shete <[email protected]>

Building the Pinctrl driver into the kernel image increases its size. These drivers are not required during early boot, build them as a loadable module instead to reduce the kernel image size.

Signed-off-by Prathamesh Shete <[email protected]>
---
 arch/arm64/configs/defconfig | 2 ++
 1 file changed, 2 insertions(+)
arch/arm64/configs/defconfig +2 -0
index dd1ac01ee29b..f525670d3b84 100644
@@ -711,6 +711,8 @@ CONFIG_PINCTRL_SC8280XP_LPASS_LPI=m
 CONFIG_PINCTRL_SM8550_LPASS_LPI=m
 CONFIG_PINCTRL_SM8650_LPASS_LPI=m
 CONFIG_PINCTRL_SOPHGO_SG2000=y
+CONFIG_PINCTRL_TEGRA238=m
+CONFIG_PINCTRL_TEGRA264=m
 CONFIG_GPIO_ALTERA=m
 CONFIG_GPIO_CADENCE=m
 CONFIG_GPIO_DAVINCI=y
Signature · 1 line
2.43.0
#10 lore raw

Re: [PATCH 6/6] arm64: defconfig: make Tegra238 and Tegra264 Pinctrl a loadable module

Quoted 3 lines · On 09/04/2026 15:13, [email protected] wrote:

From: Prathamesh Shete <[email protected]>

Building the Pinctrl driver into the kernel image increases its size.

That's obvious.

Quoted 2 lines

These drivers are not required during early boot, build them as a loadable module instead to reduce the kernel image size.

So you replace built-in into module?

Quoted 11 lines
Signed-off-by Prathamesh Shete <[email protected]>
---
 arch/arm64/configs/defconfig | 2 ++
 1 file changed, 2 insertions(+)
arch/arm64/configs/defconfig +0 -0
index dd1ac01ee29b..f525670d3b84 100644

arch/arm64/configs/defconfig CONFIG_PINCTRL_SC8280XP_LPASS_LPI=m · line 715

Quoted 5 lines
arch/arm64/configs/defconfig +2 -0
@@ -711,6 +711,8 @@ CONFIG_PINCTRL_SC8280XP_LPASS_LPI=m
 CONFIG_PINCTRL_SM8550_LPASS_LPI=m
 CONFIG_PINCTRL_SM8650_LPASS_LPI=m
 CONFIG_PINCTRL_SOPHGO_SG2000=y
+CONFIG_PINCTRL_TEGRA238=m
+CONFIG_PINCTRL_TEGRA264=m

No, you just added as module. Why do we want them in upstream defconfig?

Standard question, already asked Nvidia more than once.

Best regards,
Krzysztof

maintainer
#11 lore raw

Re: [PATCH 6/6] arm64: defconfig: make Tegra238 and Tegra264 Pinctrl a loadable module

Quoted 30 lines · Krzysztof Kozlowski
Quoted 3 lines · On 09/04/2026 15:13, [email protected] wrote:

From: Prathamesh Shete <[email protected]>

Building the Pinctrl driver into the kernel image increases its size.

That's obvious.

Quoted 2 lines

These drivers are not required during early boot, build them as a loadable module instead to reduce the kernel image size.

So you replace built-in into module?

Quoted 11 lines
Signed-off-by Prathamesh Shete <[email protected]>
---
  arch/arm64/configs/defconfig | 2 ++
  1 file changed, 2 insertions(+)
arch/arm64/configs/defconfig +0 -0
index dd1ac01ee29b..f525670d3b84 100644

arch/arm64/configs/defconfig CONFIG_PINCTRL_SC8280XP_LPASS_LPI=m · line 715

Quoted 5 lines
arch/arm64/configs/defconfig +2 -0
@@ -711,6 +711,8 @@ CONFIG_PINCTRL_SC8280XP_LPASS_LPI=m
  CONFIG_PINCTRL_SM8550_LPASS_LPI=m
  CONFIG_PINCTRL_SM8650_LPASS_LPI=m
  CONFIG_PINCTRL_SOPHGO_SG2000=y
+CONFIG_PINCTRL_TEGRA238=m
+CONFIG_PINCTRL_TEGRA264=m

No, you just added as module. Why do we want them in upstream defconfig?

Quoted 1 line

Standard question, already asked Nvidia more than once.

Yes :-)

Prathamesh, what we need to do is ...

1. Add a patch to populate the pinctrl DT nodes for Tegra264 device.
2. In this patch, only enable pinctrl for Tegra264 because we are lacking an upstream board for Tegra238 for that moment. In the commit message we should add a comment to indicate with Tegra264 platform is using this.

We can still merge the DT binding-doc changes and driver for Tegra238, but no point to enable in the defconfig yet.

Jon

Signature · 1 line
nvpublic
maintainer
#12 lore raw

Re: [PATCH 6/6] arm64: defconfig: make Tegra238 and Tegra264 Pinctrl a loadable module

Quoted 37 lines · Jon Hunter
Quoted 30 lines · Krzysztof Kozlowski
Quoted 3 lines · On 09/04/2026 15:13, [email protected] wrote:

From: Prathamesh Shete <[email protected]>

Building the Pinctrl driver into the kernel image increases its size.

That's obvious.

Quoted 2 lines

These drivers are not required during early boot, build them as a loadable module instead to reduce the kernel image size.

So you replace built-in into module?

Quoted 14 lines
Signed-off-by Prathamesh Shete <[email protected]>

---
  arch/arm64/configs/defconfig | 2 ++

  1 file changed, 2 insertions(+)
arch/arm64/configs/defconfig +0 -0
index dd1ac01ee29b..f525670d3b84 100644
@@ -711,6 +711,8 @@ CONFIG_PINCTRL_SC8280XP_LPASS_LPI=m

  CONFIG_PINCTRL_SM8550_LPASS_LPI=m
  CONFIG_PINCTRL_SM8650_LPASS_LPI=m
  CONFIG_PINCTRL_SOPHGO_SG2000=y

arch/arm64/configs/defconfig CONFIG_PINCTRL_SC8280XP_LPASS_LPI=m · line 715

Quoted 2 lines
arch/arm64/configs/defconfig +2 -0
+CONFIG_PINCTRL_TEGRA238=m
+CONFIG_PINCTRL_TEGRA264=m

No, you just added as module. Why do we want them in upstream defconfig?

Quoted 1 line

Standard question, already asked Nvidia more than once.

Yes :-)

Quoted 7 lines

Prathamesh, what we need to do is ...

1. Add a patch to populate the pinctrl DT nodes for Tegra264 device.
2. In this patch, only enable pinctrl for Tegra264 because we are lacking an upstream board for Tegra238 for that moment. In the commit message we should add a comment to indicate with Tegra264 platform is using this.

Thinking about this some more, I think I would prefer that we skip the defconfig patch and just add ...

default m if ARCH_TEGRA_238_SOC

default m if ARCH_TEGRA_264_SOC

... in the respective Kconfig files for the drivers.

Jon

Signature · 1 line
nvpublic
#13 lore raw

Re: [PATCH 6/6] arm64: defconfig: make Tegra238 and Tegra264 Pinctrl a loadable module

Quoted 48 lines · Jon Hunter
Quoted 38 lines · Jon Hunter
Quoted 31 lines · Krzysztof Kozlowski
Quoted 3 lines · On 09/04/2026 15:13, [email protected] wrote:

From: Prathamesh Shete <[email protected]>

Building the Pinctrl driver into the kernel image increases its size.

That's obvious.

Quoted 3 lines

These drivers are not required during early boot, build them as a loadable
module instead to reduce the kernel image size.

So you replace built-in into module?

Quoted 14 lines
Signed-off-by Prathamesh Shete <[email protected]>

---
  arch/arm64/configs/defconfig | 2 ++

  1 file changed, 2 insertions(+)
arch/arm64/configs/defconfig +0 -0
index dd1ac01ee29b..f525670d3b84 100644
@@ -711,6 +711,8 @@ CONFIG_PINCTRL_SC8280XP_LPASS_LPI=m

  CONFIG_PINCTRL_SM8550_LPASS_LPI=m
  CONFIG_PINCTRL_SM8650_LPASS_LPI=m
  CONFIG_PINCTRL_SOPHGO_SG2000=y

arch/arm64/configs/defconfig CONFIG_PINCTRL_SC8280XP_LPASS_LPI=m · line 715

Quoted 2 lines
arch/arm64/configs/defconfig +2 -0
+CONFIG_PINCTRL_TEGRA238=m
+CONFIG_PINCTRL_TEGRA264=m

No, you just added as module. Why do we want them in upstream defconfig?

Quoted 1 line

Standard question, already asked Nvidia more than once.

Yes :-)

Quoted 7 lines

Prathamesh, what we need to do is ...

1. Add a patch to populate the pinctrl DT nodes for Tegra264 device.
2. In this patch, only enable pinctrl for Tegra264 because we are lacking an upstream board for Tegra238 for that moment. In the commit message we should add a comment to indicate with Tegra264 platform is using this.

Quoted 8 lines

Thinking about this some more, I think I would prefer that we skip the defconfig patch and just add ...

default m if ARCH_TEGRA_238_SOC

default m if ARCH_TEGRA_264_SOC

... in the respective Kconfig files for the drivers.

I know some people have objected to this type of construct in the past because it means that you automatically enable these drivers in configs where it previously wasn't, bloating people's test builds, etc.

I also know that people don't like it when we add seemingly random options to defconfig.

For this particular case, given that the options are dependent on the per-SoC Kconfig symbols I think the "default m" above is a fair compromise.

Thierry

#14 lore raw

Re: [PATCH 6/6] arm64: defconfig: make Tegra238 and Tegra264 Pinctrl a loadable module

In reply to Jon Hunter
Quoted 24 lines · Jon Hunter
Quoted 16 lines
Quoted 12 lines

arch/arm64/configs/defconfig CONFIG_PINCTRL_SC8280XP_LPASS_LPI=m · line 715

Quoted 9 lines

index dd1ac01ee29b..f525670d3b84 100644

arch/arm64/configs/defconfig +0 -0
@@ -711,6 +711,8 @@ CONFIG_PINCTRL_SC8280XP_LPASS_LPI=m

  CONFIG_PINCTRL_SM8550_LPASS_LPI=m
  CONFIG_PINCTRL_SM8650_LPASS_LPI=m
  CONFIG_PINCTRL_SOPHGO_SG2000=y

arch/arm64/configs/defconfig +2 -0
+CONFIG_PINCTRL_TEGRA238=m
+CONFIG_PINCTRL_TEGRA264=m

No, you just added as module. Why do we want them in upstream defconfig?

Quoted 1 line

Standard question, already asked Nvidia more than once.

Yes :-)

Quoted 7 lines

Prathamesh, what we need to do is ...

1. Add a patch to populate the pinctrl DT nodes for Tegra264 device.
2. In this patch, only enable pinctrl for Tegra264 because we are lacking an upstream board for Tegra238 for that moment. In the commit message we should add a comment to indicate with Tegra264 platform is using this.

Quoted 8 lines

Thinking about this some more, I think I would prefer that we skip the defconfig patch and just add ...

default m if ARCH_TEGRA_238_SOC

default m if ARCH_TEGRA_264_SOC

... in the respective Kconfig files for the drivers.

I support this, I am trying to do something similar to Qualcomm. None of core SoC drivers should become a question to the user. We want one multiplatform image in general, so whoever chooses ARCH_TEGRA or ARCH_QCOM should get everything (while still being able to disable if needed).

Best regards,
Krzysztof

author
#15 lore raw

v2 cover Add Tegra238 and Tegra264 pinctrl support

In reply to [email protected]

From: Prathamesh Shete <[email protected]>

Add pinctrl driver support for Tegra238 and Tegra264 along with the corresponding device tree binding documentation. Additionally, export tegra_pinctrl_probe() to allow the drivers to be built as loadable modules.

Changes in v2:
- Drop the "arm64: defconfig: make Tegra238 and Tegra264 Pinctrl ..." patch and instead add 'default m if ARCH_TEGRA_{238,264}_SOC' to the PINCTRL_TEGRA238 / PINCTRL_TEGRA264 Kconfig entries so the drivers are auto-enabled as modules.
- New patch "arm64: tegra: Add pinctrl nodes for Tegra264" that describes the three Tegra264 pin controllers (pinmux_main, pinmux_aon, pinmux_uphy) in tegra264.dtsi.
- dt-bindings (Tegra238 and Tegra264 pinmux):
* Add 'required: compatible, reg' to the top-level schemas.
* Switch 'unevaluatedProperties: false' to 'additionalProperties: false' on the top-level schemas.
- Reword commit messages to use imperative mood

Link to v1:
https://lore.kernel.org/linux-tegra/[email protected]/

Prathamesh Shete (6):
pinctrl: tegra: Export tegra_pinctrl_probe()
dt-bindings: pinctrl: Document Tegra238 pin controllers
pinctrl: tegra: Add Tegra238 pinmux driver
dt-bindings: pinctrl: Document Tegra264 pin controllers
pinctrl: tegra: Add Tegra264 pinmux driver
arm64: tegra: Add pinctrl nodes for Tegra264

 .../pinctrl/nvidia,tegra238-pinmux-aon.yaml   |   82 +
 .../nvidia,tegra238-pinmux-common.yaml        |   73 +
 .../pinctrl/nvidia,tegra238-pinmux.yaml       |  219 ++
 .../pinctrl/nvidia,tegra264-pinmux-aon.yaml   |   80 +
 .../nvidia,tegra264-pinmux-common.yaml        |   84 +
 .../pinctrl/nvidia,tegra264-pinmux-main.yaml  |  167 ++
 .../pinctrl/nvidia,tegra264-pinmux-uphy.yaml  |   78 +
 arch/arm64/boot/dts/nvidia/tegra264.dtsi      |   15 +
 drivers/pinctrl/tegra/Kconfig                 |   20 +
 drivers/pinctrl/tegra/Makefile                |    2 +
 drivers/pinctrl/tegra/pinctrl-tegra.c         |    2 +
 drivers/pinctrl/tegra/pinctrl-tegra238.c      | 2056 +++++++++++++++
 drivers/pinctrl/tegra/pinctrl-tegra264.c      | 2216 +++++++++++++++++
 13 files changed, 5094 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-aon.yaml
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-common.yaml
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux.yaml
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-aon.yaml
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-common.yaml
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-main.yaml
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-uphy.yaml
 create mode 100644 drivers/pinctrl/tegra/pinctrl-tegra238.c
 create mode 100644 drivers/pinctrl/tegra/pinctrl-tegra264.c
Signature · 1 line
2.43.0
author
#16 lore raw

PATCH v2 1/6 pinctrl: tegra: Export tegra_pinctrl_probe()

From: Prathamesh Shete <[email protected]>

Export tegra_pinctrl_probe() to allow SoC-specific Tegra pinctrl drivers built as modules to use the common probe path.

Signed-off-by Prathamesh Shete <[email protected]>

---
Changes in v2:
No Change

---
 drivers/pinctrl/tegra/pinctrl-tegra.c | 2 ++
 1 file changed, 2 insertions(+)
drivers/pinctrl/tegra/pinctrl-tegra.c +2 -0
index bac2adeb5c63..3f58f7db525f 100644
@@ -13,6 +13,7 @@
 #include <linux/err.h>
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/module.h>
 #include <linux/of.h>
 #include <linux/platform_device.h>
 #include <linux/seq_file.h>

@@ -936,3 +937,4 @@ int tegra_pinctrl_probe(struct platform_device *pdev,
 
 	return 0;
 }
+EXPORT_SYMBOL_GPL(tegra_pinctrl_probe);
Signature · 1 line
2.43.0
author
#17 lore raw

PATCH v2 2/6 dt-bindings: pinctrl: Document Tegra238 pin controllers

In reply to [email protected]

From: Prathamesh Shete <[email protected]>

Tegra238 contains two pin controllers. Document their compatible strings and describe the list of pins and functions that they provide.

Signed-off-by Prathamesh Shete <[email protected]>

---
Changes in v2:
- Add a 'required:' block listing 'compatible' and 'reg'.
- Switch top-level 'unevaluatedProperties: false' to 'additionalProperties: false'.

---
 .../pinctrl/nvidia,tegra238-pinmux-aon.yaml   |  82 +++++++
 .../nvidia,tegra238-pinmux-common.yaml        |  73 ++++++
 .../pinctrl/nvidia,tegra238-pinmux.yaml       | 219 ++++++++++++++++++
 3 files changed, 374 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-aon.yaml
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-common.yaml
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux.yaml
Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-aon.yaml new file +82 -0
new file mode 100644
index 000000000000..ab9264d87c88
@@ -0,0 +1,82 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra238-pinmux-aon.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra238 AON Pinmux Controller
+
+maintainers:
+  - Thierry Reding <[email protected]>
+  - Jon Hunter <[email protected]>
+
+properties:
+  compatible:
+    const: nvidia,tegra238-pinmux-aon
+
+  reg:
+    maxItems: 1
+
+patternProperties:
+  "^pinmux(-[a-z0-9-]+)?$":
+    type: object
+
+    # pin groups
+    additionalProperties:
+      $ref: nvidia,tegra238-pinmux-common.yaml
+
+      properties:
+        nvidia,pins:
+          items:
+            enum: [ bootv_ctl_n_paa0, soc_gpio00_paa1, vcomp_alert_paa2,
+                    pwm1_paa3, batt_oc_paa4, soc_gpio04_paa5,
+                    soc_gpio25_paa6, soc_gpio26_paa7,
+                    hdmi_cec_pbb0,
+                    spi2_sck_pcc0, spi2_miso_pcc1, spi2_mosi_pcc2,
+                    spi2_cs0_pcc3, spi2_cs1_pcc4, uart3_tx_pcc5,
+                    uart3_rx_pcc6, gen2_i2c_scl_pcc7,
+                    gen2_i2c_sda_pdd0, gen8_i2c_scl_pdd1,
+                    gen8_i2c_sda_pdd2, touch_clk_pdd3, dmic1_clk_pdd4,
+                    dmic1_dat_pdd5, soc_gpio19_pdd6, pwm2_pdd7,
+                    pwm3_pee0, pwm7_pee1,
+                    # drive groups (ordered PAA, PBB, PCC, PDD, PEE)
+                    drive_bootv_ctl_n_paa0, drive_soc_gpio00_paa1,
+                    drive_vcomp_alert_paa2, drive_pwm1_paa3,
+                    drive_batt_oc_paa4, drive_soc_gpio04_paa5,
+                    drive_soc_gpio25_paa6, drive_soc_gpio26_paa7,
+                    drive_hdmi_cec_pbb0,
+                    drive_spi2_sck_pcc0, drive_spi2_miso_pcc1,
+                    drive_spi2_mosi_pcc2, drive_spi2_cs0_pcc3,
+                    drive_spi2_cs1_pcc4, drive_uart3_tx_pcc5,
+                    drive_uart3_rx_pcc6, drive_gen2_i2c_scl_pcc7,
+                    drive_gen2_i2c_sda_pdd0, drive_gen8_i2c_scl_pdd1,
+                    drive_gen8_i2c_sda_pdd2, drive_touch_clk_pdd3,
+                    drive_dmic1_clk_pdd4, drive_dmic1_dat_pdd5,
+                    drive_soc_gpio19_pdd6, drive_pwm2_pdd7,
+                    drive_pwm3_pee0, drive_pwm7_pee1 ]
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/pinctrl/pinctrl-tegra.h>
+
+    pinmux@c300000 {
+      compatible = "nvidia,tegra238-pinmux-aon";
+      reg = <0x0c300000 0x4000>;
+
+      pinctrl-names = "cec";
+      pinctrl-0 = <&cec_state>;
+
+      cec_state: pinmux-cec {
+        cec {
+          nvidia,pins = "hdmi_cec_pbb0";
+          nvidia,function = "hdmi_cec";
+        };
+      };
+    };
+...
Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-common.yaml new file +73 -0

73 lines not on this page · raw message

Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux.yaml new file +219 -0

219 lines not on this page · raw message

Signature · 1 line
2.43.0
#18 lore raw

Re: [PATCH v2 2/6] dt-bindings: pinctrl: Document Tegra238 pin controllers

Quoted 5 lines · On Mon, Apr 20, 2026 at 10:05:57AM +0000, [email protected] wrote:

From: Prathamesh Shete <[email protected]>

Tegra238 contains two pin controllers. Document their compatible strings and describe the list of pins and functions that they provide.

Please wrap code according to the preferred limit expressed in Kernel coding style (checkpatch is not a coding style description, but only a tool). However don't wrap blindly (see Kernel coding style).

Do not attach (thread) your patchsets to some other threads (unrelated or older versions). This buries them deep in the mailbox and might interfere with applying entire sets. See also:
https://elixir.bootlin.com/linux/v6.16-rc2/source/Documentation/process/submitting-patches.rst#L830

Really, just try yourself:

b4 diff '[email protected]'
Looking up https://lore.kernel.org/all/[email protected]/
Checking for older revisions
Grabbing search results from lore.kernel.org
---
Analyzing 22 messages in the thread
WARNING: duplicate messages found at index 1
Subject 1: pinctrl: tegra: Export tegra_pinctrl_probe()
Subject 2: arm64: tegra: Add pinctrl nodes for Tegra264
2 is a reply... replacing existing: arm64: tegra: Add pinctrl nodes for Tegra264
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Preparing fake-am for v1: Add Tegra238 and Tegra264 pinctrl support
range: 59c488f24a80..90c14406cf64
Preparing fake-am for v2: pinctrl: tegra: Export tegra_pinctrl_probe()
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Could not create fake-am range for upper series v2

Can nvidia finally start using normal/expected process? There are tools for that for a few years...

Entire Qualcomm, which upstreams magnitude more patches than Nvidia, uses b4 (basically "must" use otherwise we will complain). Why it cannot happen here?

Best regards,
Krzysztof

#19 lore raw

Re: [PATCH v2 2/6] dt-bindings: pinctrl: Document Tegra238 pin controllers

Quoted 10 lines · Krzysztof Kozlowski
Quoted 5 lines · On Mon, Apr 20, 2026 at 10:05:57AM +0000, [email protected] wrote:

From: Prathamesh Shete <[email protected]>

Tegra238 contains two pin controllers. Document their compatible strings and describe the list of pins and functions that they provide.

Please wrap code according to the preferred limit expressed in Kernel coding style (checkpatch is not a coding style description, but only a tool). However don't wrap blindly (see Kernel coding style).

Heh,
wrong
template :(.
Should
be:

Please wrap commit message according to Linux coding style / submission process (neither too early nor over the limit):
https://elixir.bootlin.com/linux/v6.4-rc1/source/Documentation/process/submitting-patches.rst#L597

Best regards,
Krzysztof

#20 lore raw

Re: [PATCH v2 2/6] dt-bindings: pinctrl: Document Tegra238 pin controllers

Quoted 8 lines · Krzysztof Kozlowski
Quoted 7 lines · Krzysztof Kozlowski
Quoted 5 lines · On Mon, Apr 20, 2026 at 10:05:57AM +0000, [email protected] wrote:

From: Prathamesh Shete <[email protected]>

Tegra238 contains two pin controllers. Document their compatible strings and describe the list of pins and functions that they provide.

Quoted 7 lines
Quoted 3 lines

Please wrap code according to the preferred limit expressed in Kernel coding style (checkpatch is not a coding style description, but only a tool). However don't wrap blindly (see Kernel coding style).

Heh,
wrong
template :(.

No worries. We all make mistakes. =P

Thierry

author
#21 lore raw

PATCH v2 3/6 pinctrl: tegra: Add Tegra238 pinmux driver

In reply to [email protected]

From: Prathamesh Shete <[email protected]>

Add support for the two pin controllers (MAIN and AON) found on Tegra238.

Signed-off-by Prathamesh Shete <[email protected]>

---
Changes in v2:
- Add 'default m if ARCH_TEGRA_238_SOC' to the PINCTRL_TEGRA238 Kconfig.
- Reword commit message to use imperative mood.

---
 drivers/pinctrl/tegra/Kconfig            |   10 +
 drivers/pinctrl/tegra/Makefile           |    1 +
 drivers/pinctrl/tegra/pinctrl-tegra238.c | 2056 ++++++++++++++++++++++
 3 files changed, 2067 insertions(+)
 create mode 100644 drivers/pinctrl/tegra/pinctrl-tegra238.c
drivers/pinctrl/tegra/Kconfig +10 -0
index 660d101ea367..cb3a7ab02e72 100644
@@ -36,6 +36,16 @@ config PINCTRL_TEGRA234
 	bool
 	select PINCTRL_TEGRA
 
+config PINCTRL_TEGRA238
+	tristate "NVIDIA Tegra238 pinctrl driver"
+	default m if ARCH_TEGRA_238_SOC
+	select PINCTRL_TEGRA
+	help
+	  Say Y or M here to enable support for the pinctrl driver for
+	  NVIDIA Tegra238 SoC. This driver controls the pin multiplexing
+	  and configuration for the MAIN and AON pin controllers found
+	  on Tegra238.
+
 config PINCTRL_TEGRA_XUSB
 	def_bool y if ARCH_TEGRA
 	select GENERIC_PHY
drivers/pinctrl/tegra/Makefile +1 -0
index 82176526549e..ce700bbcbf6e 100644
@@ -8,4 +8,5 @@ obj-$(CONFIG_PINCTRL_TEGRA210)		+= pinctrl-tegra210.o
 obj-$(CONFIG_PINCTRL_TEGRA186)		+= pinctrl-tegra186.o
 obj-$(CONFIG_PINCTRL_TEGRA194)		+= pinctrl-tegra194.o
 obj-$(CONFIG_PINCTRL_TEGRA234)		+= pinctrl-tegra234.o
+obj-$(CONFIG_PINCTRL_TEGRA238)		+= pinctrl-tegra238.o
 obj-$(CONFIG_PINCTRL_TEGRA_XUSB)	+= pinctrl-tegra-xusb.o
drivers/pinctrl/tegra/pinctrl-tegra238.c new file +2056 -0

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author
#22 lore raw

PATCH v2 4/6 dt-bindings: pinctrl: Document Tegra264 pin controllers

In reply to [email protected]

From: Prathamesh Shete <[email protected]>

Tegra264 contains three pin controllers. Document their compatible strings and describe the list of pins and functions that they provide.

Signed-off-by Prathamesh Shete <[email protected]>

---
Changes in v2:
- Add a 'required:' block listing 'compatible' and 'reg'.
- Switch top-level 'unevaluatedProperties: false' to 'additionalProperties: false'.

---
 .../pinctrl/nvidia,tegra264-pinmux-aon.yaml   |  80 +++++++++
 .../nvidia,tegra264-pinmux-common.yaml        |  84 +++++++++
 .../pinctrl/nvidia,tegra264-pinmux-main.yaml  | 167 ++++++++++++++++++
 .../pinctrl/nvidia,tegra264-pinmux-uphy.yaml  |  78 ++++++++
 4 files changed, 409 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-aon.yaml
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-common.yaml
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-main.yaml
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-uphy.yaml
Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-aon.yaml new file +80 -0
new file mode 100644
index 000000000000..682e6510ed45
@@ -0,0 +1,80 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra264-pinmux-aon.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra264 AON Pinmux Controller
+
+maintainers:
+  - Thierry Reding <[email protected]>
+  - Jon Hunter <[email protected]>
+
+properties:
+  compatible:
+    const: nvidia,tegra264-pinmux-aon
+
+  reg:
+    maxItems: 1
+
+patternProperties:
+  "^pinmux(-[a-z0-9-]+)?$":
+    type: object
+
+    # pin groups
+    additionalProperties:
+      $ref: nvidia,tegra264-pinmux-common.yaml
+
+      properties:
+        nvidia,pins:
+          items:
+            enum: [ soc_gpio00_paa0, vcomp_alert_paa1, ao_retention_n_paa2,
+                    batt_oc_paa3, bootv_ctl_n_paa4, power_on_paa5,
+                    hdmi_cec_paa6, soc_gpio07_paa7, soc_gpio08_pbb0,
+                    soc_gpio09_pbb1, gen2_i2c_scl_pcc0, gen2_i2c_sda_pcc1,
+                    gen3_i2c_scl_pcc2, gen3_i2c_sda_pcc3, gp_pwm4_pcc4,
+                    uart0_tx_pcc5, uart0_rx_pcc6, spi2_sck_pcc7,
+                    spi2_miso_pdd0, spi2_mosi_pdd1, spi2_cs0_n_pdd2,
+                    soc_gpio21_pdd3, soc_gpio22_pdd4, soc_gpio23_pdd5,
+                    soc_gpio24_pdd6, soc_gpio25_pdd7, soc_gpio26_pee0,
+                    soc_gpio27_pee1, soc_gpio28_pee2, soc_gpio29_pee3,
+                    drive_ao_retention_n_paa2, drive_batt_oc_paa3,
+                    drive_power_on_paa5, drive_vcomp_alert_paa1,
+                    drive_bootv_ctl_n_paa4, drive_soc_gpio00_paa0,
+                    drive_soc_gpio07_paa7, drive_soc_gpio08_pbb0,
+                    drive_soc_gpio09_pbb1, drive_hdmi_cec_paa6,
+                    drive_gen2_i2c_scl_pcc0, drive_gen2_i2c_sda_pcc1,
+                    drive_gen3_i2c_scl_pcc2, drive_gen3_i2c_sda_pcc3,
+                    drive_gp_pwm4_pcc4, drive_uart0_tx_pcc5,
+                    drive_uart0_rx_pcc6, drive_spi2_sck_pcc7,
+                    drive_spi2_miso_pdd0, drive_spi2_mosi_pdd1,
+                    drive_spi2_cs0_n_pdd2, drive_soc_gpio21_pdd3,
+                    drive_soc_gpio22_pdd4, drive_soc_gpio23_pdd5,
+                    drive_soc_gpio24_pdd6, drive_soc_gpio25_pdd7,
+                    drive_soc_gpio26_pee0, drive_soc_gpio27_pee1,
+                    drive_soc_gpio28_pee2, drive_soc_gpio29_pee3 ]
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/pinctrl/pinctrl-tegra.h>
+
+    pinmux@c7a2000 {
+        compatible = "nvidia,tegra264-pinmux-aon";
+        reg = <0xc7a2000 0x2000>;
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&state_default>;
+
+        state_default: pinmux-default {
+            uart0 {
+                nvidia,pins = "uart0_tx_pcc5";
+                nvidia,function = "uarta_txd";
+            };
+        };
+    };
Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-common.yaml new file +84 -0

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Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-main.yaml new file +167 -0

167 lines not on this page · raw message

Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-uphy.yaml new file +78 -0

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Reviewed-by on v2 4/6
#23 lore raw

Re: [PATCH v2 4/6] dt-bindings: pinctrl: Document Tegra264 pin controllers

Quoted 5 lines · On 20/04/2026 12:05, [email protected] wrote:

From: Prathamesh Shete <[email protected]>

Tegra264 contains three pin controllers. Document their compatible strings and describe the list of pins and functions that they provide.

Same comment about commit msg.

I cannot compare with previous version, because you broke it with this style of posting. Please do not use non-standard way of posting things. b4 is there for you on purpose, so when you do not know how to do it, the tool does it for you.

With commit msg fixed:

Reviewed-by Krzysztof Kozlowski <[email protected]>

Best regards,
Krzysztof

author
#24 lore raw

PATCH 1/1 arm64: tegra: Add pinctrl nodes for Tegra264

In reply to [email protected]

From: Prathamesh Shete <[email protected]>

Add the three pin controller (MAIN, UPHY, AON) device tree nodes found on Tegra264.

Signed-off-by Prathamesh Shete <[email protected]>

---
Changes in v2:
- Replaces the v1 "arm64: defconfig: make Tegra238 and Tegra264 Pinctrl ..." patch (now unnecessary thanks to the 'default m if ARCH_TEGRA_{238,264}_SOC' Kconfig change) by adding the three pin controller nodes (pinmux, pinmux_aon, pinmux_uphy) to tegra264.dtsi.

---
 arch/arm64/boot/dts/nvidia/tegra264.dtsi | 15 +++++++++++++++
 1 file changed, 15 insertions(+)
arch/arm64/boot/dts/nvidia/tegra264.dtsi +15 -0
index 06d8357bdf52..dc7793088d2e 100644
@@ -3380,6 +3380,11 @@ i2c3: i2c@c610000 {
 			status = "disabled";
 		};
 
+		pinmux_aon: pinmux@c7a2000 {
+			compatible = "nvidia,tegra264-pinmux-aon";
+			reg = <0x0 0x0c7a2000 0x0 0x2000>;
+		};
+
 		pmc: pmc@c800000 {
 			compatible = "nvidia,tegra264-pmc";
 			reg = <0x0 0x0c800000 0x0 0x100000>,

@@ -3586,6 +3591,11 @@ pci@c000000 {
 			status = "disabled";
 		};
 
+		pinmux_main: pinmux@c281000 {
+			compatible = "nvidia,tegra264-pinmux-main";
+			reg = <0x00 0x0c281000 0x0 0xc000>;
+		};
+
 		i2c14: i2c@c410000 {
 			compatible = "nvidia,tegra264-i2c";
 			reg = <0x00 0x0c410000 0x0 0x10000>;

@@ -3862,6 +3872,11 @@ bus@a800000000 {
 			 <0x00 0x20000000 0x00 0x20000000 0x00 0x60000000>, /* non-prefetchable memory (32-bit, 1536 GiB) */
 			 <0xa8 0x80000000 0xa8 0x80000000 0x57 0x80000000>; /* I/O, ECAM, prefetchable memory (64-bit) */
 
+		pinmux_uphy: pinmux@82e0000 {
+			compatible = "nvidia,tegra264-pinmux-uphy";
+			reg = <0x00 0x082e0000 0x0 0x4000>;
+		};
+
 		gpio_uphy: gpio@8300000 {
 			compatible = "nvidia,tegra264-gpio-uphy";
 			reg = <0x00 0x08300000 0x0 0x2000>,
Signature · 1 line
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#25 lore raw

Re: [PATCH] arm64: tegra: Add pinctrl nodes for Tegra264

Quoted 5 lines · On Mon, Apr 20, 2026 at 10:06:01AM +0000, [email protected] wrote:

From: Prathamesh Shete <[email protected]>

Add the three pin controller (MAIN, UPHY, AON) device tree nodes found on Tegra264.

Quoted 8 lines
Signed-off-by Prathamesh Shete <[email protected]>

---
Changes in v2:
- Replaces the v1 "arm64: defconfig: make Tegra238 and Tegra264 Pinctrl ..." patch (now unnecessary thanks to the 'default m if ARCH_TEGRA_{238,264}_SOC' Kconfig change) by adding the three pin controller nodes (pinmux, pinmux_aon, pinmux_uphy) to tegra264.dtsi.

What is this doing in the middle of other v2 patchset?

Best regards,
Krzysztof

maintainer
#26 lore raw

Re: [PATCH] arm64: tegra: Add pinctrl nodes for Tegra264

In reply to [email protected]
Quoted 5 lines · On 20/04/2026 11:06, [email protected] wrote:

From: Prathamesh Shete <[email protected]>

Add the three pin controller (MAIN, UPHY, AON) device tree nodes found on Tegra264.

Quoted 8 lines
Signed-off-by Prathamesh Shete <[email protected]>

---
Changes in v2:
- Replaces the v1 "arm64: defconfig: make Tegra238 and Tegra264 Pinctrl ..." patch (now unnecessary thanks to the 'default m if ARCH_TEGRA_{238,264}_SOC' Kconfig change) by adding the three pin controller nodes (pinmux, pinmux_aon, pinmux_uphy) to tegra264.dtsi.

This patch does not replace the defconfig patch. The defconfig patch was dropped which is unrelated to this patch. This patch was added for V2 for completeness. So all we need to say here is that this was added for V2 and that's all.

Obviously something went completely wrong with the patch series generation and is not properly added to the series. Please fix up for V3.

Jon

Signature · 1 line
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author
#27 lore raw

PATCH v2 5/6 pinctrl: tegra: Add Tegra264 pinmux driver

In reply to [email protected]

From: Prathamesh Shete <[email protected]>

Add support for the three pin controllers
(MAIN, UPHY and AON) found on Tegra264.

Signed-off-by Prathamesh Shete <[email protected]>

---
Changes in v2:
- Add 'default m if ARCH_TEGRA_264_SOC' to the PINCTRL_TEGRA264 Kconfig.

---
 drivers/pinctrl/tegra/Kconfig            |   10 +
 drivers/pinctrl/tegra/Makefile           |    1 +
 drivers/pinctrl/tegra/pinctrl-tegra264.c | 2216 ++++++++++++++++++++++
 3 files changed, 2227 insertions(+)
 create mode 100644 drivers/pinctrl/tegra/pinctrl-tegra264.c
drivers/pinctrl/tegra/Kconfig +10 -0
index cb3a7ab02e72..54263b4554c0 100644
@@ -46,6 +46,16 @@ config PINCTRL_TEGRA238
 	  and configuration for the MAIN and AON pin controllers found
 	  on Tegra238.
 
+config PINCTRL_TEGRA264
+	tristate "NVIDIA Tegra264 pinctrl driver"
+	default m if ARCH_TEGRA_264_SOC
+	select PINCTRL_TEGRA
+	help
+	  Say Y or M here to enable support for the pinctrl driver for
+	  NVIDIA Tegra264 SoC. This driver controls the pin multiplexing
+	  and configuration for the MAIN, AON and UPHY pin controllers found
+	  on Tegra264.
+
 config PINCTRL_TEGRA_XUSB
 	def_bool y if ARCH_TEGRA
 	select GENERIC_PHY
drivers/pinctrl/tegra/Makefile +1 -0
index ce700bbcbf6e..71ade768bf9c 100644
@@ -9,4 +9,5 @@ obj-$(CONFIG_PINCTRL_TEGRA186)		+= pinctrl-tegra186.o
 obj-$(CONFIG_PINCTRL_TEGRA194)		+= pinctrl-tegra194.o
 obj-$(CONFIG_PINCTRL_TEGRA234)		+= pinctrl-tegra234.o
 obj-$(CONFIG_PINCTRL_TEGRA238)		+= pinctrl-tegra238.o
+obj-$(CONFIG_PINCTRL_TEGRA264)		+= pinctrl-tegra264.o
 obj-$(CONFIG_PINCTRL_TEGRA_XUSB)	+= pinctrl-tegra-xusb.o
drivers/pinctrl/tegra/pinctrl-tegra264.c new file +2216 -0

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