Boot IRQ quirks for Broadcom and AMD/ATI
Subsystems (3)
cover Boot IRQ quirks for Broadcom and AMD/ATI
This is against linux-2.6-tip, branch pci-ioapic-boot-irq-quirks.
The corrected versions of the Broadcom and AMD/ATI boot IRQ quirks, and a patch that uses DECLARE_PCI_FIXUP_FINAL instead of *_EARLY, and adds *_RESUME.
The AMD/ATI SB700S does not need a quirk. The boot IRQs here are active even when the IO-APIC lines are not masked. So even for traditional IRQ handling that does not use masking, the boot IRQs need to be disabled by the BIOS. If there are actual cases of BIOSes that do not disable these boot IRQs in APIC mode, we could consider including an SB700S patch. But I doubt this will be needed, as this problem would quickly surface during testing with any general-purpose OS.
The quirk for the AMD 8131 and AMD 8132 takes identical action as an existing quirk for the AMD 8131 rev. A0 and B0. The existing quirk is due to an AMD erratum to fix IO-APIC mode. Our patch now deletes the older quirk and adds a comment to the new one that describes the two purposes of the quirk.
PATCH 1/3 Add quirk to disable boot interrupt generation on broadcom HT1000
From: Olaf Dabrunz <[email protected]>
--- drivers/pci/quirks.c | 32 ++++++++++++++++++++++++++++++++ 1 files changed, 32 insertions(+), 0 deletions(-)
drivers/pci/quirks.c +32 -0
@@ -1417,6 +1417,38 @@ static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev) dev->vendor, dev->device); }DECLARE_PCI_FIXUP_EARLY (PCI_VENDOR_ID_INTEL ,PCI_DEVICE_ID_INTEL_ESB_10 , quirk_disable_intel_boot_interrupt); + +/* +* disable boot interrupts on HT-1000 +*/ +#define BC_HT1000_FEATURE_REG 0x64 +#define BC_HT1000_PIC_REGS_ENABLE (1<<0) +#define BC_HT1000_MAP_IDX 0xC00 +#define BC_HT1000_MAP_DATA 0xC01 + +static void quirk_disable_broadcom_boot_interrupt (struct pci_dev *dev) +{ +u32 pci_config_dword; +u8 irq; + +if (noioapicquirk) +return ; + +pci_read_config_dword (dev,BC_HT1000_FEATURE_REG , &pci_config_dword); +pci_write_config_dword (dev,BC_HT1000_FEATURE_REG , pci_config_dword | +BC_HT1000_PIC_REGS_ENABLE ); + +for (irq =0x10 ; irq <0x10 +32 ; irq++) { +outb (irq,BC_HT1000_MAP_IDX ); +outb (0x00 ,BC_HT1000_MAP_DATA ); + } + +pci_write_config_dword (dev,BC_HT1000_FEATURE_REG , pci_config_dword); + +printk (KERN_INFO "disabled boot interrupts on PCI device" +"0x%04x:0x%04x\n" , dev->vendor, dev->device); +} +DECLARE_PCI_FIXUP_EARLY (PCI_VENDOR_ID_SERVERWORKS ,PCI_DEVICE_ID_SERVERWORKS_HT1000SB , quirk_disable_broadcom_boot_interrupt);#endif /* CONFIG_X86_IO_APIC */ /*
Signature · 1 line
1.5.2.4
PATCH 2/3 disable AMD/ATI legacy boot interrupt generation
In reply to Olaf DabrunzFrom: Olaf Dabrunz <[email protected]>
Add quirks for several AMD/ATI chipsets to prevent generation of legacy boot interrupts.
Integrates a separate older quirk to make IO-APIC mode work on AMD 8131 rev. A0 and B0, which was due to an AMD erratum.
--- drivers/pci/quirks.c | 71 +++++++++++++++++++++++++++++++++++--------------- 1 files changed, 50 insertions(+), 21 deletions(-)
drivers/pci/quirks.c +50 -21
@@ -602,27 +602,6 @@ static void __init quirk_ioapic_rmw(struct pci_dev *dev) sis_apic_bug = 1; }DECLARE_PCI_FIXUP_FINAL (PCI_VENDOR_ID_SI ,PCI_ANY_ID , quirk_ioapic_rmw); - -#define AMD8131_revA0 0x01 -#define AMD8131_revB0 0x11 -#define AMD8131_MISC 0x40 -#define AMD8131_NIOAMODE_BIT 0 -static void quirk_amd_8131_ioapic (struct pci_dev *dev) -{ -unsigned char tmp; - -if (nr_ioapics ==0 ) -return ; - -if (dev->revision == AMD8131_revA0 || dev->revision == AMD8131_revB0) { -dev_info (&dev->dev,"Fixing up AMD8131 IOAPIC mode\n" ); -pci_read_config_byte ( dev,AMD8131_MISC , &tmp); - tmp &= ~(1 <<AMD8131_NIOAMODE_BIT ); -pci_write_config_byte ( dev,AMD8131_MISC , tmp); - } -} -DECLARE_PCI_FIXUP_FINAL (PCI_VENDOR_ID_AMD ,PCI_DEVICE_ID_AMD_8131_BRIDGE , quirk_amd_8131_ioapic); -DECLARE_PCI_FIXUP_RESUME (PCI_VENDOR_ID_AMD ,PCI_DEVICE_ID_AMD_8131_BRIDGE , quirk_amd_8131_ioapic);#endif /* CONFIG_X86_IO_APIC */ /*
@@ -1449,6 +1428,56 @@ static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev) "0x%04x:0x%04x\n", dev->vendor, dev->device); }DECLARE_PCI_FIXUP_EARLY (PCI_VENDOR_ID_SERVERWORKS ,PCI_DEVICE_ID_SERVERWORKS_HT1000SB , quirk_disable_broadcom_boot_interrupt); + +/* +* disable boot interrupts on AMD and ATI chipsets +*/ +/* +* NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131 +* rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode +* (due to an erratum). +*/ +#define AMD_813X_MISC 0x40 +#define AMD_813X_NOIOAMODE (1<<0) + +static void quirk_disable_amd_813x_boot_interrupt (struct pci_dev *dev) +{ +u32 pci_config_dword; + +if (noioapicquirk) +return ; + +pci_read_config_dword (dev,AMD_813X_MISC , &pci_config_dword); + pci_config_dword &= ~AMD_813X_NOIOAMODE ; +pci_write_config_dword (dev,AMD_813X_MISC , pci_config_dword); + +printk (KERN_INFO "disabled boot interrupts on PCI device " +"0x%04x:0x%04x\n" , dev->vendor, dev->device); +} +DECLARE_PCI_FIXUP_EARLY (PCI_VENDOR_ID_AMD ,PCI_DEVICE_ID_AMD_8131_BRIDGE , quirk_disable_amd_813x_boot_interrupt); +DECLARE_PCI_FIXUP_EARLY (PCI_VENDOR_ID_AMD ,PCI_DEVICE_ID_AMD_8132_BRIDGE , quirk_disable_amd_813x_boot_interrupt); + +#define AMD_8111_PCI_IRQ_ROUTING 0x56 + +static void quirk_disable_amd_8111_boot_interrupt (struct pci_dev *dev) +{ +u16 pci_config_word; + +if (noioapicquirk) +return ; + +pci_read_config_word (dev,AMD_8111_PCI_IRQ_ROUTING , &pci_config_word); +if (!pci_config_word) { +printk (KERN_INFO "boot interrupts on PCI device 0x%04x:0x%04x " +"already disabled\n" , + dev->vendor, dev->device); +return ; + } +pci_write_config_word (dev,AMD_8111_PCI_IRQ_ROUTING ,0 ); +printk (KERN_INFO "disabled boot interrupts on PCI device " +"0x%04x:0x%04x\n" , dev->vendor, dev->device); +} +DECLARE_PCI_FIXUP_EARLY (PCI_VENDOR_ID_AMD ,PCI_DEVICE_ID_AMD_8111_SMBUS , quirk_disable_amd_8111_boot_interrupt);#endif /* CONFIG_X86_IO_APIC */ /*
Signature · 1 line
1.5.2.4
PATCH 3/3 call boot IRQ quirks at end of device init and during resume
In reply to Olaf DabrunzFrom: Olaf Dabrunz <[email protected]>
It is not necessary to call boot IRQ quirks before the BARs of the bridges are probed. The normal case is to use DECLARE_PCI_FIXUP_FINAL, so we use this instead now.
After a resume, we need to call the quirks again.
--- drivers/pci/quirks.c | 37 ++++++++++++++++++++++++------------- 1 file changed, 24 insertions(+), 13 deletions(-)
drivers/pci/quirks.c +24 -13
@@ -1360,14 +1360,22 @@ static void quirk_reroute_to_boot_interr dev->vendor, dev->device);return ; } -DECLARE_PCI_FIXUP_EARLY (PCI_VENDOR_ID_INTEL ,PCI_DEVICE_ID_INTEL_80333_0 , quirk_reroute_to_boot_interrupts_intel); -DECLARE_PCI_FIXUP_EARLY (PCI_VENDOR_ID_INTEL ,PCI_DEVICE_ID_INTEL_80333_1 , quirk_reroute_to_boot_interrupts_intel); -DECLARE_PCI_FIXUP_EARLY (PCI_VENDOR_ID_INTEL ,PCI_DEVICE_ID_INTEL_ESB2_0 , quirk_reroute_to_boot_interrupts_intel); -DECLARE_PCI_FIXUP_EARLY (PCI_VENDOR_ID_INTEL ,PCI_DEVICE_ID_INTEL_PXH_0 , quirk_reroute_to_boot_interrupts_intel); -DECLARE_PCI_FIXUP_EARLY (PCI_VENDOR_ID_INTEL ,PCI_DEVICE_ID_INTEL_PXH_1 , quirk_reroute_to_boot_interrupts_intel); -DECLARE_PCI_FIXUP_EARLY (PCI_VENDOR_ID_INTEL ,PCI_DEVICE_ID_INTEL_PXHV , quirk_reroute_to_boot_interrupts_intel); -DECLARE_PCI_FIXUP_EARLY (PCI_VENDOR_ID_INTEL ,PCI_DEVICE_ID_INTEL_80332_0 , quirk_reroute_to_boot_interrupts_intel); -DECLARE_PCI_FIXUP_EARLY (PCI_VENDOR_ID_INTEL ,PCI_DEVICE_ID_INTEL_80332_1 , quirk_reroute_to_boot_interrupts_intel); +DECLARE_PCI_FIXUP_FINAL (PCI_VENDOR_ID_INTEL ,PCI_DEVICE_ID_INTEL_80333_0 , quirk_reroute_to_boot_interrupts_intel); +DECLARE_PCI_FIXUP_FINAL (PCI_VENDOR_ID_INTEL ,PCI_DEVICE_ID_INTEL_80333_1 , quirk_reroute_to_boot_interrupts_intel); +DECLARE_PCI_FIXUP_FINAL (PCI_VENDOR_ID_INTEL ,PCI_DEVICE_ID_INTEL_ESB2_0 , quirk_reroute_to_boot_interrupts_intel); +DECLARE_PCI_FIXUP_FINAL (PCI_VENDOR_ID_INTEL ,PCI_DEVICE_ID_INTEL_PXH_0 , quirk_reroute_to_boot_interrupts_intel); +DECLARE_PCI_FIXUP_FINAL (PCI_VENDOR_ID_INTEL ,PCI_DEVICE_ID_INTEL_PXH_1 , quirk_reroute_to_boot_interrupts_intel); +DECLARE_PCI_FIXUP_FINAL (PCI_VENDOR_ID_INTEL ,PCI_DEVICE_ID_INTEL_PXHV , quirk_reroute_to_boot_interrupts_intel); +DECLARE_PCI_FIXUP_FINAL (PCI_VENDOR_ID_INTEL ,PCI_DEVICE_ID_INTEL_80332_0 , quirk_reroute_to_boot_interrupts_intel); +DECLARE_PCI_FIXUP_FINAL (PCI_VENDOR_ID_INTEL ,PCI_DEVICE_ID_INTEL_80332_1 , quirk_reroute_to_boot_interrupts_intel); +DECLARE_PCI_FIXUP_RESUME (PCI_VENDOR_ID_INTEL ,PCI_DEVICE_ID_INTEL_80333_0 , quirk_reroute_to_boot_interrupts_intel); +DECLARE_PCI_FIXUP_RESUME (PCI_VENDOR_ID_INTEL ,PCI_DEVICE_ID_INTEL_80333_1 , quirk_reroute_to_boot_interrupts_intel); +DECLARE_PCI_FIXUP_RESUME (PCI_VENDOR_ID_INTEL ,PCI_DEVICE_ID_INTEL_ESB2_0 , quirk_reroute_to_boot_interrupts_intel); +DECLARE_PCI_FIXUP_RESUME (PCI_VENDOR_ID_INTEL ,PCI_DEVICE_ID_INTEL_PXH_0 , quirk_reroute_to_boot_interrupts_intel); +DECLARE_PCI_FIXUP_RESUME (PCI_VENDOR_ID_INTEL ,PCI_DEVICE_ID_INTEL_PXH_1 , quirk_reroute_to_boot_interrupts_intel); +DECLARE_PCI_FIXUP_RESUME (PCI_VENDOR_ID_INTEL ,PCI_DEVICE_ID_INTEL_PXHV , quirk_reroute_to_boot_interrupts_intel); +DECLARE_PCI_FIXUP_RESUME (PCI_VENDOR_ID_INTEL ,PCI_DEVICE_ID_INTEL_80332_0 , quirk_reroute_to_boot_interrupts_intel); +DECLARE_PCI_FIXUP_RESUME (PCI_VENDOR_ID_INTEL ,PCI_DEVICE_ID_INTEL_80332_1 , quirk_reroute_to_boot_interrupts_intel);/* * On some chipsets we can disable the generation of legacy INTx boot
@@ -1395,7 +1403,8 @@ static void quirk_disable_intel_boot_intprintk (KERN_INFO "disabled boot interrupt on device 0x%04x:0x%04x\n" , dev->vendor, dev->device); } -DECLARE_PCI_FIXUP_EARLY (PCI_VENDOR_ID_INTEL ,PCI_DEVICE_ID_INTEL_ESB_10 , quirk_disable_intel_boot_interrupt); +DECLARE_PCI_FIXUP_FINAL (PCI_VENDOR_ID_INTEL ,PCI_DEVICE_ID_INTEL_ESB_10 , quirk_disable_intel_boot_interrupt); +DECLARE_PCI_FIXUP_RESUME (PCI_VENDOR_ID_INTEL ,PCI_DEVICE_ID_INTEL_ESB_10 , quirk_disable_intel_boot_interrupt);/* * disable boot interrupts on HT-1000
@@ -1427,7 +1436,8 @@ static void quirk_disable_broadcom_boot_printk (KERN_INFO "disabled boot interrupts on PCI device" "0x%04x:0x%04x\n" , dev->vendor, dev->device); } -DECLARE_PCI_FIXUP_EARLY (PCI_VENDOR_ID_SERVERWORKS ,PCI_DEVICE_ID_SERVERWORKS_HT1000SB , quirk_disable_broadcom_boot_interrupt); +DECLARE_PCI_FIXUP_FINAL (PCI_VENDOR_ID_SERVERWORKS ,PCI_DEVICE_ID_SERVERWORKS_HT1000SB , quirk_disable_broadcom_boot_interrupt); +DECLARE_PCI_FIXUP_RESUME (PCI_VENDOR_ID_SERVERWORKS ,PCI_DEVICE_ID_SERVERWORKS_HT1000SB , quirk_disable_broadcom_boot_interrupt);/* * disable boot interrupts on AMD and ATI chipsets
@@ -1454,8 +1464,8 @@ static void quirk_disable_amd_813x_boot_printk (KERN_INFO "disabled boot interrupts on PCI device " "0x%04x:0x%04x\n" , dev->vendor, dev->device); } -DECLARE_PCI_FIXUP_EARLY (PCI_VENDOR_ID_AMD ,PCI_DEVICE_ID_AMD_8131_BRIDGE , quirk_disable_amd_813x_boot_interrupt); -DECLARE_PCI_FIXUP_EARLY (PCI_VENDOR_ID_AMD ,PCI_DEVICE_ID_AMD_8132_BRIDGE , quirk_disable_amd_813x_boot_interrupt); +DECLARE_PCI_FIXUP_FINAL (PCI_VENDOR_ID_AMD ,PCI_DEVICE_ID_AMD_8131_BRIDGE , quirk_disable_amd_813x_boot_interrupt); +DECLARE_PCI_FIXUP_RESUME (PCI_VENDOR_ID_AMD ,PCI_DEVICE_ID_AMD_8132_BRIDGE , quirk_disable_amd_813x_boot_interrupt);#define AMD_8111_PCI_IRQ_ROUTING 0x56
@@ -1477,7 +1487,8 @@ static void quirk_disable_amd_8111_boot_printk (KERN_INFO "disabled boot interrupts on PCI device " "0x%04x:0x%04x\n", dev->vendor, dev->device); } -DECLARE_PCI_FIXUP_EARLY (PCI_VENDOR_ID_AMD ,PCI_DEVICE_ID_AMD_8111_SMBUS , quirk_disable_amd_8111_boot_interrupt); +DECLARE_PCI_FIXUP_FINAL (PCI_VENDOR_ID_AMD ,PCI_DEVICE_ID_AMD_8111_SMBUS , quirk_disable_amd_8111_boot_interrupt); +DECLARE_PCI_FIXUP_RESUME (PCI_VENDOR_ID_AMD ,PCI_DEVICE_ID_AMD_8111_SMBUS , quirk_disable_amd_8111_boot_interrupt);#endif /* CONFIG_X86_IO_APIC */ /*
Signature · 1 line
1.5.2.4
Quoted 15 lines · Olaf Dabrunz
This is against linux-2.6-tip, branch pci-ioapic-boot-irq-quirks.
The corrected versions of the Broadcom and AMD/ATI boot IRQ quirks, and a patch that uses
DECLARE_PCI_FIXUP_FINALinstead of*_EARLY, and adds*_RESUME.The AMD/ATI SB700S does not need a quirk. The boot IRQs here are active even when the IO-APIC lines are not masked. So even for traditional IRQ handling that does not use masking, the boot IRQs need to be disabled by the BIOS. If there are actual cases of BIOSes that do not disable these boot IRQs in APIC mode, we could consider including an SB700S patch. But I doubt this will be needed, as this problem would quickly surface during testing with any general-purpose OS.
Quoted 5 lines
The quirk for the AMD 8131 and AMD 8132 takes identical action as an existing quirk for the AMD 8131 rev. A0 and B0. The existing quirk is due to an AMD erratum to fix IO-APIC mode. Our patch now deletes the older quirk and adds a comment to the new one that describes the two purposes of the quirk.
applied to tip/x86/pci-ioapic-boot-irq-quirks, thanks Olaf.
Jesse, what do you think about this topic? We are keeping it separate for the time being. They are not particularly pretty, but being able to mask/unmask irqs (without generating those legacy IRQs and creating an IRQ storm) is essential to -rt.
Ingo
Quoted 22 lines · Ingo Molnar
Quoted 15 lines · Olaf Dabrunz
This is against linux-2.6-tip, branch pci-ioapic-boot-irq-quirks.
The corrected versions of the Broadcom and AMD/ATI boot IRQ quirks, and a patch that uses
DECLARE_PCI_FIXUP_FINALinstead of*_EARLY, and adds*_RESUME.The AMD/ATI SB700S does not need a quirk. The boot IRQs here are active even when the IO-APIC lines are not masked. So even for traditional IRQ handling that does not use masking, the boot IRQs need to be disabled by the BIOS. If there are actual cases of BIOSes that do not disable these boot IRQs in APIC mode, we could consider including an SB700S patch. But I doubt this will be needed, as this problem would quickly surface during testing with any general-purpose OS.
Quoted 5 lines
The quirk for the AMD 8131 and AMD 8132 takes identical action as an existing quirk for the AMD 8131 rev. A0 and B0. The existing quirk is due to an AMD erratum to fix IO-APIC mode. Our patch now deletes the older quirk and adds a comment to the new one that describes the two purposes of the quirk.
Quoted 6 lines
applied to tip/x86/pci-ioapic-boot-irq-quirks, thanks Olaf.
Jesse, what do you think about this topic? We are keeping it separate for the time being. They are not particularly pretty, but being able to mask/unmask irqs (without generating those legacy IRQs and creating an IRQ storm) is essential to -rt.
See my other reply; the branch looks good. I agree that making sure -rt can work is an important feature. My only concern is that this is touching so much hardware specific code that *something* is likely to break. But as long as Olaf & co. can help track down any issues, I'm ok with it.
Thanks,
Jesse
Quoted 7 lines · Jesse Barnes
Quoted 6 lines
applied to tip/x86/pci-ioapic-boot-irq-quirks, thanks Olaf.
Jesse, what do you think about this topic? We are keeping it separate for the time being. They are not particularly pretty, but being able to mask/unmask irqs (without generating those legacy IRQs and creating an IRQ storm) is essential to -rt.
Quoted 5 lines
See my other reply; the branch looks good. I agree that making sure -rt can work is an important feature. My only concern is that this is touching so much hardware specific code that *something* is likely to break. But as long as Olaf & co. can help track down any issues, I'm ok with it.
ok. We'll cook it a bit more in tip/master and then send it over to you once all the dependent changes have gone upstream in the merge window, ok? I think it's v2.6.27 worthy stuff - nicely localized, sufficiently finegrained and any problems with it has to be debugged the hard way by exposing people to them ...
Ingo
Quoted 16 lines · Ingo Molnar
Quoted 7 lines · Jesse Barnes
Quoted 6 lines
applied to tip/x86/pci-ioapic-boot-irq-quirks, thanks Olaf.
Jesse, what do you think about this topic? We are keeping it separate for the time being. They are not particularly pretty, but being able to mask/unmask irqs (without generating those legacy IRQs and creating an IRQ storm) is essential to -rt.
Quoted 5 lines
See my other reply; the branch looks good. I agree that making sure -rt can work is an important feature. My only concern is that this is touching so much hardware specific code that *something* is likely to break. But as long as Olaf & co. can help track down any issues, I'm ok with it.
Quoted 5 lines
ok. We'll cook it a bit more in tip/master and then send it over to you once all the dependent changes have gone upstream in the merge window, ok? I think it's v2.6.27 worthy stuff - nicely localized, sufficiently finegrained and any problems with it has to be debugged the hard way by exposing people to them ...
Ack. :)
Thanks,
Signature · 1 line
Olaf Dabrunz (od/odabrunz), SUSE Linux Products GmbH, Nürnberg
Quoted 15 lines · Olaf Dabrunz
Quoted 14 lines · Ingo Molnar
Quoted 12 lines · Jesse Barnes
Quoted 6 lines
applied to tip/x86/pci-ioapic-boot-irq-quirks, thanks Olaf.
Jesse, what do you think about this topic? We are keeping it separate for the time being. They are not particularly pretty, but being able to mask/unmask irqs (without generating those legacy IRQs and creating an IRQ storm) is essential to -rt.
See my other reply; the branch looks good. I agree that making sure -rt can work is an important feature. My only concern is that this is touching so much hardware specific code that *something* is likely to break. But as long as Olaf & co. can help track down any issues, I'm ok with it.
Quoted 7 lines
Quoted 5 lines
ok. We'll cook it a bit more in tip/master and then send it over to you once all the dependent changes have gone upstream in the merge window, ok? I think it's v2.6.27 worthy stuff - nicely localized, sufficiently finegrained and any problems with it has to be debugged the hard way by exposing people to them ...
Ack. :)
Sounds good, thanks. Now to get my merge bits pulled together & tested...
Jesse
Quoted 17 lines · Olaf Dabrunz
Quoted 16 lines · Ingo Molnar
Quoted 12 lines · Jesse Barnes
Quoted 6 lines
applied to tip/x86/pci-ioapic-boot-irq-quirks, thanks Olaf.
Jesse, what do you think about this topic? We are keeping it separate for the time being. They are not particularly pretty, but being able to mask/unmask irqs (without generating those legacy IRQs and creating an IRQ storm) is essential to -rt.
See my other reply; the branch looks good. I agree that making sure -rt can work is an important feature. My only concern is that this is touching so much hardware specific code that *something* is likely to break. But as long as Olaf & co. can help track down any issues, I'm ok with it.
Quoted 7 lines
Quoted 5 lines
ok. We'll cook it a bit more in tip/master and then send it over to you once all the dependent changes have gone upstream in the merge window, ok? I think it's v2.6.27 worthy stuff - nicely localized, sufficiently finegrained and any problems with it has to be debugged the hard way by exposing people to them ...
Ack. :)
I am working on a consolidated patch set for AKMP. It integrates all fixes and adds a config option CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS (prepared by Stefan Assmann), which can default to off for vanilla and to on for RT / threaded IRQ handling. This means that the whole patchset can (in principle) be applied to vanilla and RT without change. Also CONFIG_PREEMPT_HARDIRQ can "select CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS".
If you don't mind, I will send the full set out today.
Signature · 1 line
Olaf Dabrunz (od/odabrunz), SUSE Linux Products GmbH, Nürnberg
Quoted 8 lines · Olaf Dabrunz
I am working on a consolidated patch set for AKMP. It integrates all fixes and adds a config option
CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS(prepared by Stefan Assmann), which can default to off for vanilla and to on for RT / threaded IRQ handling. This means that the whole patchset can (in principle) be applied to vanilla and RT without change. AlsoCONFIG_PREEMPT_HARDIRQcan "selectCONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS".If you don't mind, I will send the full set out today.
On second thought and after talking to Stefan, as you think the patches can go into 2.6.27 as they are, there is not much benefit in integrating the fixes and the config option patch. Stefan will commit the config option patch to tip tomorrow.
Thanks,
Signature · 1 line
Olaf Dabrunz (od/odabrunz), SUSE Linux Products GmbH, Nürnberg
Quoted 8 lines · Olaf Dabrunz
Quoted 7 lines · Olaf Dabrunz
I am working on a consolidated patch set for AKMP. It integrates all fixes and adds a config option
CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS(prepared by Stefan Assmann), which can default to off for vanilla and to on for RT / threaded IRQ handling. This means that the whole patchset can (in principle) be applied to vanilla and RT without change. AlsoCONFIG_PREEMPT_HARDIRQcan "selectCONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS".
Quoted 6 lines
Quoted 1 line
If you don't mind, I will send the full set out today.
On second thought and after talking to Stefan, as you think the patches can go into 2.6.27 as they are, there is not much benefit in integrating the fixes and the config option patch. Stefan will commit the config option patch to tip tomorrow.
please do not rebase the patchset, that causes us lose the testing status, we lose the sha1's of the commits, etc. Lets keep what we have in tip/x86/pci-ioapic-boot-irq-quirks and do append-only fixlets to it.
Ingo
Quoted 13 lines · Ingo Molnar
Quoted 10 lines · Olaf Dabrunz
Quoted 8 lines · Olaf Dabrunz
I am working on a consolidated patch set for AKMP. It integrates all fixes and adds a config option
CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS(prepared by Stefan Assmann), which can default to off for vanilla and to on for RT / threaded IRQ handling. This means that the whole patchset can (in principle) be applied to vanilla and RT without change. AlsoCONFIG_PREEMPT_HARDIRQcan "selectCONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS".If you don't mind, I will send the full set out today.
Quoted 8 lines
Quoted 4 lines
On second thought and after talking to Stefan, as you think the patches can go into 2.6.27 as they are, there is not much benefit in integrating the fixes and the config option patch. Stefan will commit the config option patch to tip tomorrow.
please do not rebase the patchset, that causes us lose the testing status, we lose the sha1's of the commits, etc. Lets keep what we have in tip/x86/pci-ioapic-boot-irq-quirks and do append-only fixlets to it.
Right.
Thanks,
Signature · 1 line
Olaf Dabrunz (od/odabrunz), SUSE Linux Products GmbH, Nürnberg
PATCH 1/1 Introduce config option for pci reroute quirks (was: [PATCH 0/3] Boot IRQ quirks for Broadcom and AMD/ATI)
In reply to Olaf DabrunzThis is against linux-2.6-tip, branch pci-ioapic-boot-irq-quirks.
From: Stefan Assmann <[email protected]>
Subject: Introduce config option for pci reroute quirks
The config option X86_REROUTE_FOR_BROKEN_BOOT_IRQS is introduced to enable (or disable) the redirection of the interrupt handler to the boot interrupt line by default. Depending on the existence of interrupt masking / threaded interrupt handling in the kernel (vanilla, rt, ...) and the maturity of the rerouting patch, users can enable or disable the redirection by default.
This means that the reroute quirk can be applied to any kernel without changing it.
Interrupt sharing could be increased if this option is enabled. However this option is vital for threaded interrupt handling, as done by the RT kernel. It should simplify the consolidation with the RT kernel.
The option can be overridden by either pci=ioapicreroute or pci=noioapicreroute.
--- Documentation/kernel-parameters.txt | 4 ++++ arch/x86/Kconfig | 24 ++++++++++++++++++++++++ arch/x86/pci/common.c | 8 ++++++++ drivers/pci/quirks.c | 2 +- include/asm-x86/pci.h | 2 +- 5 files changed, 38 insertions(+), 2 deletions(-)
arch/x86/pci/common.c +8 -0
@@ -23,7 +23,11 @@ unsigned int pci_probe = PCI_PROBE_BIOSstatic int pci_bf_sort;int pci_routeirq;int noioapicquirk; +#ifdef CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS +int noioapicreroute =0 ; +#else int noioapicreroute =1 ; +#endif int pcibios_last_bus =-1 ;unsigned long pirq_table_addr;struct pci_bus *pci_root_bus;
@@ -504,6 +508,10 @@ char * __devinit pcibios_setup(char *stif (noioapicreroute !=-1 ) noioapicreroute =0 ;return NULL ; + }else if (!strcmp (str,"noioapicreroute" )) { +if (noioapicreroute !=-1 ) + noioapicreroute =1 ; +return NULL ; }return str; }
include/asm-x86/pci.h +1 -1
@@ -20,7 +20,7 @@ struct pci_sysdata {extern int pci_routeirq;extern int noioapicquirk; -extern int ioapicreroute; +extern int noioapicreroute;/* scan a bus after allocating a pci_sysdata for it */ extern struct pci_bus *pci_scan_bus_on_node(int busno, struct pci_ops *ops,
drivers/pci/quirks.c +1 -1
@@ -1351,7 +1351,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_IN*/ static void quirk_reroute_to_boot_interrupts_intel (struct pci_dev *dev) { -if (noioapicquirk) +if (noioapicquirk || noioapicreroute)return ; dev->irq_reroute_variant =INTEL_IRQ_REROUTE_VARIANT ;
Documentation/kernel-parameters.txt +4 -0
@@ -1525,6 +1525,10 @@ and is between 256 and 4096 characters. primary IO-APIC for bridges that cannot disable boot IRQs. This fixes a source of spurious IRQs when the system masks IRQs. + noioapicreroute [APIC] Disable workaround that uses the + boot IRQ equivalent of an IRQ that connects to + a chipset where boot IRQs cannot be disabled. + The opposite of ioapicreroute. biosirq [X86-32] Use PCI BIOS calls to get the interrupt routing table. These calls are known to be buggy on several machines and they hang the machine
arch/x86/Kconfig +24 -0
@@ -663,6 +663,30 @@ config X86_VISWS_APIC def_bool y depends on X86_32 && X86_VISWS +config X86_REROUTE_FOR_BROKEN_BOOT_IRQS + bool "Reroute for broken boot IRQs" + default n + depends on X86_IO_APIC + help + This option enables a workaround that fixes a source of + spurious interrupts. This is recommended when threaded + interrupt handling is used on systems where the generation of + superfluous "boot interrupts" cannot be disabled. + + Some chipsets generate a legacy INTx "boot IRQ" when the IRQ + entry in the chipset's IO-APIC is masked (as, e.g. the RT + kernel does during interrupt handling). On chipsets where this + boot IRQ generation cannot be disabled, this workaround keeps + the original IRQ line masked so that only the equivalent "boot + IRQ" is delivered to the CPUs. The workaround also tells the + kernel to set up the IRQ handler on the boot IRQ line. In this + way only one interrupt is delivered to the kernel. Otherwise + the spurious second interrupt may cause the kernel to bring + down (vital) interrupt lines. + + Only affects "broken" chipsets. Interrupt sharing may be + increased on these systems. + config X86_MCE bool "Machine Check Exception" depends on !X86_VOYAGER
Signature · 3 lines
Stefan Assmann | SUSE LINUX Products GmbH Software Engineer | Maxfeldstr. 5, D-90409 Nuernberg Mail : [email protected] | GF: Markus Rex, HRB 16746 (AG Nuernberg)
Ingo Molnar
AppliedRe: [PATCH] Introduce config option for pci reroute quirks (was: [PATCH 0/3] Boot IRQ quirks for Broadcom and AMD/ATI)
Quoted 15 lines · Stefan Assmann
This is against linux-2.6-tip, branch pci-ioapic-boot-irq-quirks.
From: Stefan Assmann <[email protected]>
Subject: Introduce config option for pci reroute quirksThe config option
X86_REROUTE_FOR_BROKEN_BOOT_IRQSis introduced to enable (or disable) the redirection of the interrupt handler to the boot interrupt line by default. Depending on the existence of interrupt masking / threaded interrupt handling in the kernel (vanilla, rt, ...) and the maturity of the rerouting patch, users can enable or disable the redirection by default.This means that the reroute quirk can be applied to any kernel without changing it.
Quoted 7 lines
Interrupt sharing could be increased if this option is enabled. However this option is vital for threaded interrupt handling, as done by the RT kernel. It should simplify the consolidation with the RT kernel.
The option can be overridden by either pci=ioapicreroute or pci=noioapicreroute.
applied, thanks Stefan.
Ingo
Quoted 30 lines · Jesse Barnes
Quoted 22 lines · Ingo Molnar
Quoted 15 lines · Olaf Dabrunz
This is against linux-2.6-tip, branch pci-ioapic-boot-irq-quirks.
The corrected versions of the Broadcom and AMD/ATI boot IRQ quirks, and a patch that uses
DECLARE_PCI_FIXUP_FINALinstead of*_EARLY, and adds*_RESUME.The AMD/ATI SB700S does not need a quirk. The boot IRQs here are active even when the IO-APIC lines are not masked. So even for traditional IRQ handling that does not use masking, the boot IRQs need to be disabled by the BIOS. If there are actual cases of BIOSes that do not disable these boot IRQs in APIC mode, we could consider including an SB700S patch. But I doubt this will be needed, as this problem would quickly surface during testing with any general-purpose OS.
Quoted 5 lines
The quirk for the AMD 8131 and AMD 8132 takes identical action as an existing quirk for the AMD 8131 rev. A0 and B0. The existing quirk is due to an AMD erratum to fix IO-APIC mode. Our patch now deletes the older quirk and adds a comment to the new one that describes the two purposes of the quirk.
Quoted 6 lines
applied to tip/x86/pci-ioapic-boot-irq-quirks, thanks Olaf.
Jesse, what do you think about this topic? We are keeping it separate for the time being. They are not particularly pretty, but being able to mask/unmask irqs (without generating those legacy IRQs and creating an IRQ storm) is essential to -rt.
Quoted 4 lines
See my other reply; the branch looks good. I agree that making sure -rt can work is an important feature. My only concern is that this is touching so much hardware specific code that *something* is likely to break. But as long as Olaf & co. can help track down any issues, I'm ok with it.
We should be able to help with issues. We do not think it will be necessary often.
Here is why we are confident:
We believe the patches that disable boot IRQs are safe. In general this is code that should be part of the _PIC method in ACPI BIOSes. Some BIOSes already integrate such code. We basically cover up for BIOSes that are broken or that simply do not care about RT / threaded IRQs.
The chipsets that do not have an option for disabling the boot IRQs are handled by the "reroute" workaround. It may increase interrupt sharing (depending on the IRQ routing of other devices), but makes sure that the boot IRQ mechanism does not generate two separate IRQs.
This workaround is also pretty safe, as we can follow the IRQ routing through the chips. One or two recent/upcoming north bridges have different IRQ handling capabilities, so we need to update the reroute patch for them. This is WIP.
We take much care to only improve the situation:
- By default, the safest setting is used. No actions are taken in PIC mode. In APIC mode: disable boot IRQs whenever we can, "reroute" for RT/threaded IRQ handling, don't reroute for vanilla. (The mechanism for the rerouting defaults is in the upcoming CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS patch. RT should "select" this config option.)
- Kernel command line options can be used to disable the reroute quirks or all quirks.
- Only known chipsets are handled (-- the reroute patch will be updated to also check and handle the north bridge, if necessary).
We are also preparing a paper that should clarify the whole thing, so the information will not "die with us".
Thanks,
Signature · 1 line
Olaf Dabrunz (od/odabrunz), SUSE Linux Products GmbH, Nürnberg