MIPS performance event support initial version

This patch series implemented the low-level logic for the Linux performance counter subsystem on MIPS, which enables the collection of all sorts of HW/SW performance events based on per-CPU or per-task.

An overview of this implementation is as follows:

- Using generic atomic64 operations from lib.
- SMVP/UP kernels are supported (not for SMTC).
- 24K/34K/74K cores are implemented.
- Currently working when Oprofile is _not_ available.
- Minimal software perf events are supported.

Tests were carried on the Malta-R board. The mentioned cores and kernel flavors were tested. For more information, please refer to the particular patches.

Deng-Cheng Zhu (3):
- MIPS: use the generic atomic64 operations for perf counter support
- MIPS: adding support for software perf events
- MIPS: implement hardware perf event support