MIPS performance event support initial version
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Patches in v1
| # | Subject and files | Size | Replies | Applied |
|---|---|---|---|---|
| 1/3 | MIPS: use the generic atomic64 operations for perf counter supportarch/ arch/ | +5 | 3 replies | |
| 2/3 | MIPS: adding support for software perf eventsarch/ arch/ arch/ | +39 | 0 replies | |
| 3/3 | MIPS: implement hardware perf event supportarch/ arch/ arch/ | +1478 | 3 replies |
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Cover letter [PATCH 0/3] MIPS performance event support initial version
This patch series implemented the low-level logic for the Linux performance counter subsystem on MIPS, which enables the collection of all sorts of HW/SW performance events based on per-CPU or per-task.
An overview of this implementation is as follows:
- Using generic atomic64 operations from lib.
- SMVP/UP kernels are supported (not for SMTC).
- 24K/34K/74K cores are implemented.
- Currently working when Oprofile is _not_ available.
- Minimal software perf events are supported.
Tests were carried on the Malta-R board. The mentioned cores and kernel flavors were tested. For more information, please refer to the particular patches.
Deng-Cheng Zhu (3):
- MIPS: use the generic atomic64 operations for perf counter support
- MIPS: adding support for software perf events
- MIPS: implement hardware perf event support