ARM: S3C: Add S3C2416 detection to uncompress code

PATCH New Ben Dooks 3 participants 20 messages May 12, 2010 – Jun 18, 2010

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Arm (32-bit) Arm sub-architectures Arm Samsung Exynos

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Ben Dooks

author

2010-05-12 02:35 UTC #0 lore raw

PATCH 1/15 ARM: S3C: Add S3C2416 detection to uncompress code

From: Yauhen Kharuzhy <[email protected]>

Add S3C2416 serial port setup to uncompress code.

Signed-off-by Yauhen Kharuzhy <[email protected]>

Signed-off-by Ben Dooks <[email protected]>

---
 arch/arm/mach-s3c2410/include/mach/uncompress.h |    4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)

arch/arm/mach-s3c2410/include/mach/uncompress.h +3 -1

index 72f756c..8b283f8 100644
@@ -40,7 +40,9 @@ static void arch_detect_cpu(void)
 	cpuid &= S3C2410_GSTATUS1_IDMASK;
 
 	if (is_arm926() || cpuid == S3C2410_GSTATUS1_2440 ||
-	    cpuid == S3C2410_GSTATUS1_2442) {
+	    cpuid == S3C2410_GSTATUS1_2442 ||
+	    cpuid == S3C2410_GSTATUS1_2416 ||
+	    cpuid == S3C2410_GSTATUS1_2450) {
 		fifo_mask = S3C2440_UFSTAT_TXMASK;
 		fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT;
 	} else {

Signature · 1 line

1.6.3.3

Ben Dooks

author

2010-05-12 02:38 UTC #1 lore raw

PATCH 1/15 ARM: S3C: Add S3C2416 detection to uncompress code

Quoted 3 lines · Ben Dooks

From: Yauhen Kharuzhy <[email protected]>
Add S3C2416 serial port setup to uncompress code.

Yahuen, let me know if you've any objection to this going upstrea.

Forgot to add --compose to send-email, so here's what should have gone into the first email of this series:

S3C2416 support, mainly just processor core and a few peripheral setup patches. Also has basic support for the S3C2450 which is very similar SoC which will be updated later in the series.

Currently based on the s3c24xx gpio series.

Russell, let me know if this is ok for the next merge window, and if so I'll send a pull request.

Quoted 24 lines

Signed-off-by Yauhen Kharuzhy <[email protected]>

Signed-off-by Ben Dooks <[email protected]>

---
 arch/arm/mach-s3c2410/include/mach/uncompress.h |    4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)

arch/arm/mach-s3c2410/include/mach/uncompress.h +3 -1

index 72f756c..8b283f8 100644
@@ -40,7 +40,9 @@ static void arch_detect_cpu(void)
 	cpuid &= S3C2410_GSTATUS1_IDMASK;
 
 	if (is_arm926() || cpuid == S3C2410_GSTATUS1_2440 ||
-	    cpuid == S3C2410_GSTATUS1_2442) {
+	    cpuid == S3C2410_GSTATUS1_2442 ||
+	    cpuid == S3C2410_GSTATUS1_2416 ||
+	    cpuid == S3C2410_GSTATUS1_2450) {
 		fifo_mask = S3C2440_UFSTAT_TXMASK;
 		fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT;
 	} else {

Signature · 1 line

1.6.3.3

Signature · 5 lines

-- 
Ben

Q:      What's a light-year?
A:      One-third less calories than a regular year.

Yauhen Kharuzhy

2010-05-12 07:25 UTC #2 lore raw

PATCH 1/15 ARM: S3C: Add S3C2416 detection to uncompress code

Quoted 6 lines · Ben Dooks

Quoted 3 lines · Ben Dooks
From: Yauhen Kharuzhy <[email protected]>
Add S3C2416 serial port setup to uncompress code.
Yahuen, let me know if you've any objection to this going upstrea.

No, don't have.

Quoted 44 lines

Forgot to add --compose to send-email, so here's what should have gone into the first email of this series:
S3C2416 support, mainly just processor core and a few peripheral setup patches. Also has basic support for the S3C2450 which is very similar SoC which will be updated later in the series.
Currently based on the s3c24xx gpio series.
Russell, let me know if this is ok for the next merge window, and if so I'll send a pull request.
Quoted 24 lines
Signed-off-by Yauhen Kharuzhy <[email protected]>
Signed-off-by Ben Dooks <[email protected]>
---
 arch/arm/mach-s3c2410/include/mach/uncompress.h |    4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)
arch/arm/mach-s3c2410/include/mach/uncompress.h +3 -1
index 72f756c..8b283f8 100644
@@ -40,7 +40,9 @@ static void arch_detect_cpu(void)
 	cpuid &= S3C2410_GSTATUS1_IDMASK;
 
 	if (is_arm926() || cpuid == S3C2410_GSTATUS1_2440 ||
-	    cpuid == S3C2410_GSTATUS1_2442) {
+	    cpuid == S3C2410_GSTATUS1_2442 ||
+	    cpuid == S3C2410_GSTATUS1_2416 ||
+	    cpuid == S3C2410_GSTATUS1_2450) {
 		fifo_mask = S3C2440_UFSTAT_TXMASK;
 		fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT;
 	} else {
Signature · 1 line
1.6.3.3
Signature · 5 lines
-- 
Ben

Q:      What's a light-year?
A:      One-third less calories than a regular year.

Signature · 5 lines

Yauhen Kharuzhy		jekhor _at_ gmail.com
			JID: jek at jabber.ru

A: No
Q: Should I quote below my post?

Ben Dooks

author

2010-05-12 02:35 UTC #3 lore raw

PATCH 2/15 serial: Use s3c2440 driver for S3C2416 SoC

In reply to Ben Dooks

From: Yauhen Kharuzhy <[email protected]>

UARTs in the S3C2416 are almost same as in S3C2443 and can be handled by s3c2440 serial driver.

Signed-off-by Yauhen Kharuzhy <[email protected]>

Signed-off-by Ben Dooks <[email protected]>

---
 drivers/serial/Kconfig |    7 ++++---
 1 files changed, 4 insertions(+), 3 deletions(-)

drivers/serial/Kconfig +4 -3

index f55c494..5f3f03d 100644
@@ -518,12 +518,13 @@ config SERIAL_S3C2412
 	  Serial port support for the Samsung S3C2412 and S3C2413 SoC
 
 config SERIAL_S3C2440
-	tristate "Samsung S3C2440/S3C2442 Serial port support"
-	depends on SERIAL_SAMSUNG && (CPU_S3C2440 || CPU_S3C2442)
+	tristate "Samsung S3C2440/S3C2442/S3C2416 Serial port support"
+	depends on SERIAL_SAMSUNG && (CPU_S3C2440 || CPU_S3C2442 || CPU_S3C2416)
 	default y if CPU_S3C2440
 	default y if CPU_S3C2442
+	select SERIAL_SAMSUNG_UARTS_4 if CPU_S3C2416
 	help
-	  Serial port support for the Samsung S3C2440 and S3C2442 SoC
+	  Serial port support for the Samsung S3C2440, S3C2416 and S3C2442 SoC
 
 config SERIAL_S3C24A0
 	tristate "Samsung S3C24A0 Serial port support"

Signature · 1 line

1.6.3.3

Ben Dooks

author

2010-05-12 02:35 UTC #4 lore raw

PATCH 3/15 ARM: S3C2416: Add S3C2416-specific registers definitions

In reply to Ben Dooks

From: Yauhen Kharuzhy <[email protected]>

Add macros for S3C2416 SoC support.

Signed-off-by Yauhen Kharuzhy <[email protected]>

[ben-linux at fluff.org: removed files that need changing]

[ben-linux at fluff.org: Fix S3C2416_GPH0_TXD0 definition]

Signed-off-by Ben Dooks <[email protected]>

---
 arch/arm/mach-s3c2410/include/mach/dma.h           |    2 +-
 arch/arm/mach-s3c2410/include/mach/irqs.h          |   22 +++++++++++-
 arch/arm/mach-s3c2410/include/mach/regs-dsc.h      |   36 ++++++++++++++++++++
 arch/arm/mach-s3c2410/include/mach/regs-gpio.h     |   28 +++++++++++++++
 arch/arm/mach-s3c2410/include/mach/regs-irq.h      |   10 +++++
 .../mach-s3c2410/include/mach/regs-s3c2416-mem.h   |   30 ++++++++++++++++
 arch/arm/mach-s3c2410/include/mach/regs-s3c2416.h  |   24 +++++++++++++
 7 files changed, 150 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/mach-s3c2410/include/mach/regs-s3c2416-mem.h
 create mode 100644 arch/arm/mach-s3c2410/include/mach/regs-s3c2416.h

arch/arm/mach-s3c2410/include/mach/dma.h +1 -1

index 08ac5f9..cf68136 100644
@@ -54,7 +54,7 @@ enum dma_ch {
 #define DMACH_LOW_LEVEL	(1<<28)	/* use this to specifiy hardware ch no */
 
 /* we have 4 dma channels */
-#ifndef CONFIG_CPU_S3C2443
+#if !defined(CONFIG_CPU_S3C2443) && !defined(CONFIG_CPU_S3C2416)
 #define S3C_DMA_CHANNELS		(4)
 #else
 #define S3C_DMA_CHANNELS		(6)

arch/arm/mach-s3c2410/include/mach/irqs.h +21 -1

index 6c12c63..c1b8ec0 100644
@@ -115,6 +115,26 @@
 #define IRQ_S3C2412_SDI		S3C2410_IRQSUB(13)
 #define IRQ_S3C2412_CF		S3C2410_IRQSUB(14)
 
+
+#define IRQ_S3C2416_EINT8t15	S3C2410_IRQ(5)
+#define IRQ_S3C2416_DMA		S3C2410_IRQ(17)
+#define IRQ_S3C2416_UART3	S3C2410_IRQ(18)
+#define IRQ_S3C2416_SDI1	S3C2410_IRQ(20)
+#define IRQ_S3C2416_SDI0	S3C2410_IRQ(21)
+
+#define IRQ_S3C2416_LCD2	S3C2410_IRQSUB(15)
+#define IRQ_S3C2416_LCD3	S3C2410_IRQSUB(16)
+#define IRQ_S3C2416_LCD4	S3C2410_IRQSUB(17)
+#define IRQ_S3C2416_DMA0	S3C2410_IRQSUB(18)
+#define IRQ_S3C2416_DMA1	S3C2410_IRQSUB(19)
+#define IRQ_S3C2416_DMA2	S3C2410_IRQSUB(20)
+#define IRQ_S3C2416_DMA3	S3C2410_IRQSUB(21)
+#define IRQ_S3C2416_DMA4	S3C2410_IRQSUB(22)
+#define IRQ_S3C2416_DMA5	S3C2410_IRQSUB(23)
+#define IRQ_S32416_WDT		S3C2410_IRQSUB(27)
+#define IRQ_S32416_AC97		S3C2410_IRQSUB(28)
+
+
 /* extra irqs for s3c2440 */
 
 #define IRQ_S3C2440_CAM_C	S3C2410_IRQSUB(11)	/* S3C2443 too */

@@ -152,7 +172,7 @@
 #define IRQ_S3C2443_WDT		S3C2410_IRQSUB(27)
 #define IRQ_S3C2443_AC97	S3C2410_IRQSUB(28)
 
-#ifdef CONFIG_CPU_S3C2443
+#if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416)
 #define NR_IRQS (IRQ_S3C2443_AC97+1)
 #else
 #define NR_IRQS (IRQ_S3C2440_AC97+1)

arch/arm/mach-s3c2410/include/mach/regs-dsc.h +36 -0

index 3c3853c..98fd4a0 100644
@@ -19,6 +19,42 @@
 #define S3C2412_DSC1	   S3C2410_GPIOREG(0xe0)
 #endif
 
+#if defined(CONFIG_CPU_S3C2416)
+#define S3C2416_DSC0	   S3C2410_GPIOREG(0xc0)
+#define S3C2416_DSC1	   S3C2410_GPIOREG(0xc4)
+#define S3C2416_DSC2	   S3C2410_GPIOREG(0xc8)
+#define S3C2416_DSC3	   S3C2410_GPIOREG(0x110)
+
+#define S3C2416_SELECT_DSC0	(0 << 30)
+#define S3C2416_SELECT_DSC1	(1 << 30)
+#define S3C2416_SELECT_DSC2	(2 << 30)
+#define S3C2416_SELECT_DSC3	(3 << 30)
+
+#define S3C2416_DSC_GETSHIFT(x)	(x & 30)
+
+#define S3C2416_DSC0_CF		(S3C2416_SELECT_DSC0 | 28)
+#define	S3C2416_DSC0_CF_5mA	(0 << 28)
+#define	S3C2416_DSC0_CF_10mA	(1 << 28)
+#define	S3C2416_DSC0_CF_15mA	(2 << 28)
+#define	S3C2416_DSC0_CF_21mA	(3 << 28)
+#define	S3C2416_DSC0_CF_MASK	(3 << 28)
+
+#define S3C2416_DSC0_nRBE	(S3C2416_SELECT_DSC0 | 26)
+#define	S3C2416_DSC0_nRBE_5mA	(0 << 26)
+#define	S3C2416_DSC0_nRBE_10mA	(1 << 26)
+#define	S3C2416_DSC0_nRBE_15mA	(2 << 26)
+#define	S3C2416_DSC0_nRBE_21mA	(3 << 26)
+#define	S3C2416_DSC0_nRBE_MASK	(3 << 26)
+
+#define S3C2416_DSC0_nROE	(S3C2416_SELECT_DSC0 | 24)
+#define	S3C2416_DSC0_nROE_5mA	(0 << 24)
+#define	S3C2416_DSC0_nROE_10mA	(1 << 24)
+#define	S3C2416_DSC0_nROE_15mA	(2 << 24)
+#define	S3C2416_DSC0_nROE_21mA	(3 << 24)
+#define	S3C2416_DSC0_nROE_MASK	(3 << 24)
+
+#endif
+
 #if defined(CONFIG_CPU_S3C244X)
 
 #define S3C2440_DSC0	   S3C2410_GPIOREG(0xc4)

arch/arm/mach-s3c2410/include/mach/regs-gpio.h +28 -0

index 821b966..a638423 100644
@@ -610,29 +610,50 @@
 #define S3C2410_GPHUP	   S3C2410_GPIOREG(0x78)
 
 #define S3C2410_GPH0_nCTS0  (0x02 << 0)
+#define S3C2416_GPH0_TXD0  (0x02 << 0)
 
 #define S3C2410_GPH1_nRTS0  (0x02 << 2)
+#define S3C2416_GPH1_RXD0  (0x02 << 2)
 
 #define S3C2410_GPH2_TXD0   (0x02 << 4)
+#define S3C2416_GPH2_TXD1   (0x02 << 4)
 
 #define S3C2410_GPH3_RXD0   (0x02 << 6)
+#define S3C2416_GPH3_RXD1   (0x02 << 6)
 
 #define S3C2410_GPH4_TXD1   (0x02 << 8)
+#define S3C2416_GPH4_TXD2   (0x02 << 8)
 
 #define S3C2410_GPH5_RXD1   (0x02 << 10)
+#define S3C2416_GPH5_RXD2   (0x02 << 10)
 
 #define S3C2410_GPH6_TXD2   (0x02 << 12)
+#define S3C2416_GPH6_TXD3   (0x02 << 12)
 #define S3C2410_GPH6_nRTS1  (0x03 << 12)
+#define S3C2416_GPH6_nRTS2  (0x03 << 12)
 
 #define S3C2410_GPH7_RXD2   (0x02 << 14)
+#define S3C2416_GPH7_RXD3   (0x02 << 14)
 #define S3C2410_GPH7_nCTS1  (0x03 << 14)
+#define S3C2416_GPH7_nCTS2  (0x03 << 14)
 
 #define S3C2410_GPH8_UCLK   (0x02 << 16)
+#define S3C2416_GPH8_nCTS0  (0x02 << 16)
 
 #define S3C2410_GPH9_CLKOUT0  (0x02 << 18)
 #define S3C2442_GPH9_nSPICS0  (0x03 << 18)
+#define S3C2416_GPH9_nRTS0    (0x02 << 18)
 
 #define S3C2410_GPH10_CLKOUT1 (0x02 << 20)
+#define S3C2416_GPH10_nCTS1   (0x02 << 20)
+
+#define S3C2416_GPH11_nRTS1   (0x02 << 22)
+
+#define S3C2416_GPH12_EXTUARTCLK (0x02 << 24)
+
+#define S3C2416_GPH13_CLKOUT0 (0x02 << 26)
+
+#define S3C2416_GPH14_CLKOUT1 (0x02 << 28)
 
 /* The S3C2412 and S3C2413 move the GPJ register set to after
  * GPH, which means all registers after 0x80 are now offset by 0x10

@@ -703,6 +724,7 @@
 #define S3C2412_MISCCR_CLK1_CLKsrc  (0<<8)
 
 #define S3C2410_MISCCR_USBSUSPND0   (1<<12)
+#define S3C2416_MISCCR_SEL_SUSPND   (1<<12)
 #define S3C2410_MISCCR_USBSUSPND1   (1<<13)
 
 #define S3C2410_MISCCR_nRSTCON	    (1<<16)

@@ -712,6 +734,9 @@
 #define S3C2410_MISCCR_nEN_SCLKE    (1<<19)	/* not 2412 */
 #define S3C2410_MISCCR_SDSLEEP	    (7<<17)
 
+#define S3C2416_MISCCR_FLT_I2C      (1<<24)
+#define S3C2416_MISCCR_HSSPI_EN2    (1<<31)
+
 /* external interrupt control... */
 /* S3C2410_EXTINT0 -> irq sense control for EINT0..EINT7
  * S3C2410_EXTINT1 -> irq sense control for EINT8..EINT15

@@ -779,8 +804,11 @@
 #define S3C2410_GSTATUS1_IDMASK	   (0xffff0000)
 #define S3C2410_GSTATUS1_2410	   (0x32410000)
 #define S3C2410_GSTATUS1_2412	   (0x32412001)
+#define S3C2410_GSTATUS1_2416	   (0x32416003)
 #define S3C2410_GSTATUS1_2440	   (0x32440000)
 #define S3C2410_GSTATUS1_2442	   (0x32440aaa)
+/* some 2416 CPUs report this value also */
+#define S3C2410_GSTATUS1_2450	   (0x32450003)
 
 #define S3C2410_GSTATUS2_WTRESET   (1<<2)
 #define S3C2410_GSTATUS2_OFFRESET  (1<<1)

arch/arm/mach-s3c2410/include/mach/regs-irq.h +10 -0

index de86ee8..0f07ba3 100644
@@ -27,6 +27,16 @@
 #define S3C2410_SUBSRCPND      S3C2410_IRQREG(0x018)
 #define S3C2410_INTSUBMSK      S3C2410_IRQREG(0x01C)
 
+#define S3C2416_PRIORITY_MODE1		S3C2410_IRQREG(0x030)
+#define S3C2416_PRIORITY_UPDATE1	S3C2410_IRQREG(0x034)
+#define S3C2416_SRCPND2			S3C2410_IRQREG(0x040)
+#define S3C2416_INTMOD2			S3C2410_IRQREG(0x044)
+#define S3C2416_INTMSK2			S3C2410_IRQREG(0x048)
+#define S3C2416_INTPND2			S3C2410_IRQREG(0x050)
+#define S3C2416_INTOFFSET2		S3C2410_IRQREG(0x054)
+#define S3C2416_PRIORITY_MODE2		S3C2410_IRQREG(0x070)
+#define S3C2416_PRIORITY_UPDATE2	S3C2410_IRQREG(0x074)
+
 /* mask: 0=enable, 1=disable
  * 1 bit EINT, 4=EINT4, 23=EINT23
  * EINT0,1,2,3 are not handled here.

arch/arm/mach-s3c2410/include/mach/regs-s3c2416-mem.h new file +30 -0

new file mode 100644
index 0000000..2f31b74
@@ -0,0 +1,30 @@
+/* arch/arm/mach-s3c2410/include/mach/regs-s3c2416-mem.h
+ *
+ * Copyright (c) 2009 Yauhen Kharuzhy <[email protected]>,
+ *	as part of OpenInkpot project
+ * Copyright (c) 2009 Promwad Innovation Company
+ *	Yauhen Kharuzhy <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2416 memory register definitions
+*/
+
+#ifndef __ASM_ARM_REGS_S3C2416_MEM
+#define __ASM_ARM_REGS_S3C2416_MEM
+
+#ifndef S3C2416_MEMREG
+#define S3C2416_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
+#endif
+
+#define S3C2416_BANKCFG			S3C2416_MEMREG(0x00)
+#define S3C2416_BANKCON1		S3C2416_MEMREG(0x04)
+#define S3C2416_BANKCON2		S3C2416_MEMREG(0x08)
+#define S3C2416_BANKCON3		S3C2416_MEMREG(0x0C)
+
+#define S3C2416_REFRESH			S3C2416_MEMREG(0x10)
+#define S3C2416_TIMEOUT			S3C2416_MEMREG(0x14)
+
+#endif /*  __ASM_ARM_REGS_S3C2416_MEM */

arch/arm/mach-s3c2410/include/mach/regs-s3c2416.h new file +24 -0

new file mode 100644
index 0000000..e443167
@@ -0,0 +1,24 @@
+/* arch/arm/mach-s3c2410/include/mach/regs-s3c2416.h
+ *
+ * Copyright (c) 2009 Yauhen Kharuzhy <[email protected]>,
+ *	as part of OpenInkpot project
+ * Copyright (c) 2009 Promwad Innovation Company
+ *	Yauhen Kharuzhy <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2416 specific register definitions
+*/
+
+#ifndef __ASM_ARCH_REGS_S3C2416_H
+#define __ASM_ARCH_REGS_S3C2416_H "s3c2416"
+
+#define S3C2416_SWRST		(S3C24XX_VA_CLKPWR + 0x44)
+#define S3C2416_SWRST_RESET	(0x533C2416)
+
+/* see regs-power.h for the other registers in the power block. */
+
+#endif	/* __ASM_ARCH_REGS_S3C2416_H */
+

Signature · 1 line

1.6.3.3

Ben Dooks

author

2010-05-12 02:35 UTC #5 lore raw

PATCH 4/15 ARM: SAMSUNG: Move S3C6400 PLL code to <plat/pll.h> for re-use

In reply to Ben Dooks

The S3C6400 EPLL code matches the S3C2416 and compatible SoCs, so move it from mach-s3c64xx into <plat/pll.h> for easy reuse.

Signed-off-by Ben Dooks <[email protected]>

---
 arch/arm/mach-s3c64xx/include/mach/pll.h      |   35 +---------------
 arch/arm/plat-samsung/include/plat/pll6553x.h |   51 +++++++++++++++++++++++++
 2 files changed, 54 insertions(+), 32 deletions(-)
 create mode 100644 arch/arm/plat-samsung/include/plat/pll6553x.h

arch/arm/mach-s3c64xx/include/mach/pll.h +3 ~~-32~~

index 90bbd72..5ef0bb6 100644
@@ -20,6 +20,7 @@
 #define S3C6400_PLL_SDIV_SHIFT	(0)
 
 #include <asm/div64.h>
+#include <plat/pll6553x.h>
 
 static inline unsigned long s3c6400_get_pll(unsigned long baseclk,
 					    u32 pllcon)

@@ -37,38 +38,8 @@ static inline unsigned long s3c6400_get_pll(unsigned long baseclk,
 	return (unsigned long)fvco;
 }
 
-#define S3C6400_EPLL_MDIV_MASK	((1 << (23-16)) - 1)
-#define S3C6400_EPLL_PDIV_MASK	((1 << (13-8)) - 1)
-#define S3C6400_EPLL_SDIV_MASK	((1 << (2-0)) - 1)
-#define S3C6400_EPLL_MDIV_SHIFT	(16)
-#define S3C6400_EPLL_PDIV_SHIFT	(8)
-#define S3C6400_EPLL_SDIV_SHIFT	(0)
-#define S3C6400_EPLL_KDIV_MASK  (0xffff)
-
 static inline unsigned long s3c6400_get_epll(unsigned long baseclk)
 {
-	unsigned long result;
-	u32 epll0 = __raw_readl(S3C_EPLL_CON0);
-	u32 epll1 = __raw_readl(S3C_EPLL_CON1);
-	u32 mdiv, pdiv, sdiv, kdiv;
-	u64 tmp;
-
-	mdiv = (epll0 >> S3C6400_EPLL_MDIV_SHIFT) & S3C6400_EPLL_MDIV_MASK;
-	pdiv = (epll0 >> S3C6400_EPLL_PDIV_SHIFT) & S3C6400_EPLL_PDIV_MASK;
-	sdiv = (epll0 >> S3C6400_EPLL_SDIV_SHIFT) & S3C6400_EPLL_SDIV_MASK;
-	kdiv = epll1 & S3C6400_EPLL_KDIV_MASK;
-
-	/* We need to multiple baseclk by mdiv (the integer part) and kdiv
-	 * which is in 2^16ths, so shift mdiv up (does not overflow) and
-	 * add kdiv before multiplying. The use of tmp is to avoid any
-	 * overflows before shifting bac down into result when multipling
-	 * by the mdiv and kdiv pair.
-	 */
-
-	tmp = baseclk;
-	tmp *= (mdiv << 16) + kdiv;
-	do_div(tmp, (pdiv << sdiv));
-	result = tmp >> 16;
-
-	return result;
+	return s3c_get_pll6553x(baseclk, __raw_readl(S3C_EPLL_CON0),
+				__raw_readl(S3C_EPLL_CON1));
 }

arch/arm/plat-samsung/include/plat/pll6553x.h new file +51 -0

51 lines not on this page · raw message

Signature · 1 line

1.6.3.3

Ben Dooks

author

2010-05-12 02:35 UTC #6 lore raw

PATCH 5/15 ARM: SAMSUNG: Add s3c_disable_clocks() and tidy init+disable usage

In reply to Ben Dooks

Add s3c_disable_clocks() and change the clock registration code to use the s3c_register_clocks() followed by s3c_disable_clocks() instead of the loops it was using.

Signed-off-by Ben Dooks <[email protected]>

---
 arch/arm/mach-s3c2443/clock.c              |   27 ++++-----------------------
 arch/arm/plat-s3c24xx/s3c2410-clock.c      |   15 +++------------
 arch/arm/plat-samsung/clock.c              |   15 +++++++++++++++
 arch/arm/plat-samsung/include/plat/clock.h |    1 +
 4 files changed, 23 insertions(+), 35 deletions(-)

arch/arm/mach-s3c2443/clock.c +4 ~~-23~~

index 62cd4ea..76d8d66 100644
@@ -492,7 +492,7 @@ static struct clk clk_prediv = {
 
 /* standard clock definitions */
 
-static struct clk init_clocks_disable[] = {
+static struct clk init_clocks_off[] = {
 	{
 		.name		= "nand",
 		.id		= -1,

@@ -761,9 +761,7 @@ void __init_or_cpufreq s3c2443_setup_clocks(void)
 
 void __init s3c2443_init_clocks(int xtal)
 {
-	struct clk *clkp;
 	unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
-	int ret;
 	int ptr;
 
 	/* s3c2443 parents h and p clocks from prediv */

@@ -774,15 +772,7 @@ void __init s3c2443_init_clocks(int xtal)
 	s3c2443_setup_clocks();
 	s3c2443_clk_initparents();
 
-	for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
-		clkp = clks[ptr];
-
-		ret = s3c24xx_register_clock(clkp);
-		if (ret < 0) {
-			printk(KERN_ERR "Failed to register clock %s (%d)\n",
-			       clkp->name, ret);
-		}
-	}
+	s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
 
 	for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
 		s3c_register_clksrc(clksrcs[ptr], 1);

@@ -819,17 +809,8 @@ void __init s3c2443_init_clocks(int xtal)
 
 	/* install (and disable) the clocks we do not need immediately */
 
-	clkp = init_clocks_disable;
-	for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
-
-		ret = s3c24xx_register_clock(clkp);
-		if (ret < 0) {
-			printk(KERN_ERR "Failed to register clock %s (%d)\n",
-			       clkp->name, ret);
-		}
-
-		(clkp->enable)(clkp, 0);
-	}
+	s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+	s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
 
 	s3c_pwmclk_init();
 }

arch/arm/plat-s3c24xx/s3c2410-clock.c +3 ~~-12~~

index b61bdb7..9ecc5d9 100644
@@ -87,7 +87,7 @@ static int s3c2410_upll_enable(struct clk *clk, int enable)
 
 /* standard clock definitions */
 
-static struct clk init_clocks_disable[] = {
+static struct clk init_clocks_off[] = {
 	{
 		.name		= "nand",
 		.id		= -1,

@@ -249,17 +249,8 @@ int __init s3c2410_baseclk_add(void)
 
 	/* install (and disable) the clocks we do not need immediately */
 
-	clkp = init_clocks_disable;
-	for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
-
-		ret = s3c24xx_register_clock(clkp);
-		if (ret < 0) {
-			printk(KERN_ERR "Failed to register clock %s (%d)\n",
-			       clkp->name, ret);
-		}
-
-		s3c2410_clkcon_enable(clkp, 0);
-	}
+	s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+	s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
 
 	/* show the clock-slow value */

arch/arm/plat-samsung/clock.c +15 -0

index 1b25c9d..8bf79f3 100644
@@ -376,6 +376,21 @@ void __init s3c_register_clocks(struct clk *clkp, int nr_clks)
 	}
 }
 
+/**
+ * s3c_disable_clocks() - disable an array of clocks
+ * @clkp: Pointer to the first clock in the array.
+ * @nr_clks: Number of clocks to register.
+ *
+ * for internal use only at initialisation time. disable the clocks in the
+ * @clkp array.
+ */
+
+void __init s3c_disable_clocks(struct clk *clkp, int nr_clks)
+{
+	for (; nr_clks > 0; nr_clks--, clkp++)
+		(clkp->enable)(clkp, 0);
+}
+
 /* initalise all the clocks */
 
 int __init s3c24xx_register_baseclocks(unsigned long xtal)

arch/arm/plat-samsung/include/plat/clock.h +1 -0

index 60b6269..12caf48 100644
@@ -91,6 +91,7 @@ extern int s3c24xx_register_clock(struct clk *clk);
 extern int s3c24xx_register_clocks(struct clk **clk, int nr_clks);
 
 extern void s3c_register_clocks(struct clk *clk, int nr_clks);
+extern void s3c_disable_clocks(struct clk *clkp, int nr_clks);
 
 extern int s3c24xx_register_baseclocks(unsigned long xtal);

Signature · 1 line

1.6.3.3

Ben Dooks

author

2010-05-12 02:35 UTC #7 lore raw

PATCH 6/15 ARM: S3C2416: Add arch support

In reply to Ben Dooks

From: Yauhen Kharuzhy <[email protected]>

Add arch/arm/mach-s3c2416 for support of the Samsung S3C2416 SoC.

This patch adds support of the S3C2416 SoC, clocks, timers, and initial IRQ support (without support of secondary set of registers).

Signed-off-by Yauhen Kharuzhy <[email protected]>

[ben-linux at fluff.org: removed files to be reworked, fixed conflicts]

[ben-linux at fluff.org: use s3c2443 reset instead of specific reset code]

Signed-off-by Ben Dooks <[email protected]>

---
 arch/arm/Kconfig                             |    3 +-
 arch/arm/Makefile                            |    2 +-
 arch/arm/mach-s3c2412/Kconfig                |    3 +-
 arch/arm/mach-s3c2416/Kconfig                |   25 +++
 arch/arm/mach-s3c2416/Makefile               |   18 ++
 arch/arm/mach-s3c2416/irq.c                  |  254 ++++++++++++++++++++++++++
 arch/arm/mach-s3c2416/s3c2416.c              |  115 ++++++++++++
 arch/arm/plat-s3c24xx/cpu.c                  |   13 ++
 arch/arm/plat-s3c24xx/include/plat/s3c2416.h |   31 +++
 arch/arm/plat-samsung/include/plat/cpu.h     |    1 +
 10 files changed, 462 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm/mach-s3c2416/Kconfig
 create mode 100644 arch/arm/mach-s3c2416/Makefile
 create mode 100644 arch/arm/mach-s3c2416/irq.c
 create mode 100644 arch/arm/mach-s3c2416/s3c2416.c
 create mode 100644 arch/arm/plat-s3c24xx/include/plat/s3c2416.h

arch/arm/Kconfig +2 -1

index 92622eb..6785c33 100644
@@ -647,7 +647,7 @@ config ARCH_SA1100
 	  Support for StrongARM 11x0 based boards.
 
 config ARCH_S3C2410
-	bool "Samsung S3C2410, S3C2412, S3C2413, S3C2440, S3C2442, S3C2443"
+	bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443"
 	select GENERIC_GPIO
 	select ARCH_HAS_CPUFREQ
 	select HAVE_CLK

@@ -892,6 +892,7 @@ if ARCH_S3C2410
 source "arch/arm/mach-s3c2400/Kconfig"
 source "arch/arm/mach-s3c2410/Kconfig"
 source "arch/arm/mach-s3c2412/Kconfig"
+source "arch/arm/mach-s3c2416/Kconfig"
 source "arch/arm/mach-s3c2440/Kconfig"
 source "arch/arm/mach-s3c2443/Kconfig"
 endif

arch/arm/Makefile +1 -1

index ed820e7..1594739 100644
@@ -160,7 +160,7 @@ machine-$(CONFIG_ARCH_PNX4008)		:= pnx4008
 machine-$(CONFIG_ARCH_PXA)		:= pxa
 machine-$(CONFIG_ARCH_REALVIEW)		:= realview
 machine-$(CONFIG_ARCH_RPC)		:= rpc
-machine-$(CONFIG_ARCH_S3C2410)		:= s3c2410 s3c2400 s3c2412 s3c2440 s3c2443
+machine-$(CONFIG_ARCH_S3C2410)		:= s3c2410 s3c2400 s3c2412 s3c2416 s3c2440 s3c2443
 machine-$(CONFIG_ARCH_S3C24A0)		:= s3c24a0
 machine-$(CONFIG_ARCH_S3C64XX)		:= s3c64xx
 machine-$(CONFIG_ARCH_S5P6440)		:= s5p6440

arch/arm/mach-s3c2412/Kconfig +2 -1

index 9a8c065..cef6a65 100644
@@ -16,7 +16,8 @@ config CPU_S3C2412
 config CPU_S3C2412_ONLY
 	bool
 	depends on ARCH_S3C2410 && !CPU_S3C2400 && !CPU_S3C2410 && \
-		   !CPU_S3C2440 && !CPU_S3C2442 && !CPU_S3C2443 && CPU_S3C2412
+		   !CPU_2416 && !CPU_S3C2440 && !CPU_S3C2442 && \
+		   !CPU_S3C2443 && CPU_S3C2412
 	default y if CPU_S3C2412
 
 config S3C2412_DMA

arch/arm/mach-s3c2416/Kconfig new file +25 -0

new file mode 100644
index 0000000..cc320f6
@@ -0,0 +1,25 @@
+# arch/arm/mach-s3c2416/Kconfig
+#
+# Copyright 2009 Yauhen Kharuzhy <[email protected]>
+#
+# Licensed under GPLv2
+
+config CPU_S3C2416
+	bool
+	depends on ARCH_S3C2410
+	select CPU_ARM926T
+	select S3C2416_DMA if S3C2410_DMA
+	select CPU_LLSERIAL_S3C2440
+	help
+	  Support for the S3C2416 SoC from the S3C24XX line
+
+config S3C2416_DMA
+	bool
+	depends on CPU_S3C2416
+	help
+	  Internal config node for S3C2416 DMA support
+
+menu "S3C2416 Machines"
+
+
+endmenu

arch/arm/mach-s3c2416/Makefile new file +18 -0

new file mode 100644
index 0000000..34bb70d
@@ -0,0 +1,18 @@
+# arch/arm/mach-s3c2416/Makefile
+#
+# Copyright 2009 Yauhen Kharuzhy <[email protected]>
+#
+# Licensed under GPLv2
+
+obj-y				:=
+obj-m				:=
+obj-n				:=
+obj-				:=
+
+obj-$(CONFIG_CPU_S3C2416)	+= s3c2416.o
+obj-$(CONFIG_CPU_S3C2416)	+= irq.o
+
+#obj-$(CONFIG_S3C2416_DMA)	+= dma.o
+
+# Machine support
+

arch/arm/mach-s3c2416/irq.c new file +254 -0

254 lines not on this page · raw message

arch/arm/mach-s3c2416/s3c2416.c new file +115 -0

115 lines not on this page · raw message

arch/arm/plat-s3c24xx/cpu.c +13 -0

index 9ca64df..494f4f3 100644
@@ -49,6 +49,7 @@
 #include <plat/s3c2400.h>
 #include <plat/s3c2410.h>
 #include <plat/s3c2412.h>
+#include <plat/s3c2416.h>
 #include <plat/s3c244x.h>
 #include <plat/s3c2443.h>

@@ -57,6 +58,7 @@
 static const char name_s3c2400[]  = "S3C2400";
 static const char name_s3c2410[]  = "S3C2410";
 static const char name_s3c2412[]  = "S3C2412";
+static const char name_s3c2416[]  = "S3C2416";
 static const char name_s3c2440[]  = "S3C2440";
 static const char name_s3c2442[]  = "S3C2442";
 static const char name_s3c2442b[]  = "S3C2442B";

@@ -137,6 +139,15 @@ static struct cpu_table cpu_ids[] __initdata = {
 		.init		= s3c2412_init,
 		.name		= name_s3c2412,
 	},
+	{			/* a strange version of the s3c2416 */
+		.idcode		= 0x32450003,
+		.idmask		= 0xffffffff,
+		.map_io		= s3c2416_map_io,
+		.init_clocks	= s3c2416_init_clocks,
+		.init_uarts	= s3c2416_init_uarts,
+		.init		= s3c2416_init,
+		.name		= name_s3c2416,
+	},
 	{
 		.idcode		= 0x32443001,
 		.idmask		= 0xffffffff,

@@ -172,6 +183,8 @@ static unsigned long s3c24xx_read_idcode_v5(void)
 {
 #if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
 	return __raw_readl(S3C2412_GSTATUS1);
+#elif defined(CONFIG_CPU_S3C2416)
+	return __raw_readl(S3C24XX_GSTATUS1);
 #else
 	return 1UL;	/* don't look like an 2400 */
 #endif

arch/arm/plat-s3c24xx/include/plat/s3c2416.h new file +31 -0

new file mode 100644
index 0000000..dc3c090
@@ -0,0 +1,31 @@
+/* linux/include/asm-arm/plat-s3c24xx/s3c2443.h
+ *
+ * Copyright (c) 2009 Yauhen Kharuzhy <[email protected]>
+ *
+ * Header file for s3c2416 cpu support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifdef CONFIG_CPU_S3C2416
+
+struct s3c2410_uartcfg;
+
+extern  int s3c2416_init(void);
+
+extern void s3c2416_map_io(void);
+
+extern void s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+
+extern void s3c2416_init_clocks(int xtal);
+
+extern  int s3c2416_baseclk_add(void);
+
+#else
+#define s3c2416_init_clocks NULL
+#define s3c2416_init_uarts NULL
+#define s3c2416_map_io NULL
+#define s3c2416_init NULL
+#endif

arch/arm/plat-samsung/include/plat/cpu.h +1 -0

index d316b4a..5dbeb79 100644
@@ -73,6 +73,7 @@ extern struct sys_timer s3c24xx_timer;
 extern struct sysdev_class s3c2410_sysclass;
 extern struct sysdev_class s3c2410a_sysclass;
 extern struct sysdev_class s3c2412_sysclass;
+extern struct sysdev_class s3c2416_sysclass;
 extern struct sysdev_class s3c2440_sysclass;
 extern struct sysdev_class s3c2442_sysclass;
 extern struct sysdev_class s3c2443_sysclass;

Signature · 1 line

1.6.3.3

Ben Dooks

author

2010-05-12 02:35 UTC #8 lore raw

PATCH 7/15 ARM: S3C2416: Add initial support of SMDK2416

In reply to Ben Dooks

From: Yauhen Kharuzhy <[email protected]>

Add support of SMDK2416 development board.

Signed-off-by Yauhen Kharuzhy <[email protected]>

Signed-off-by Ben Dooks <[email protected]>

---
 arch/arm/mach-s3c2416/Kconfig         |    6 ++
 arch/arm/mach-s3c2416/Makefile        |    1 +
 arch/arm/mach-s3c2416/mach-smdk2416.c |  144 +++++++++++++++++++++++++++++++++
 3 files changed, 151 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-s3c2416/mach-smdk2416.c

arch/arm/mach-s3c2416/Kconfig +6 -0

index cc320f6..528f273 100644
@@ -21,5 +21,11 @@ config S3C2416_DMA
 
 menu "S3C2416 Machines"
 
+config MACH_SMDK2416
+	bool "SMDK2416"
+	select CPU_S3C2416
+	select S3C_DEV_HSMMC
+	help
+	  Say Y here if you are using an SMDK2416
 
 endmenu

arch/arm/mach-s3c2416/Makefile +1 -0

index 34bb70d..9183e81 100644
@@ -16,3 +16,4 @@ obj-$(CONFIG_CPU_S3C2416)	+= irq.o
 
 # Machine support
 
+obj-$(CONFIG_MACH_SMDK2416)	+= mach-smdk2416.o

arch/arm/mach-s3c2416/mach-smdk2416.c new file +144 -0

144 lines not on this page · raw message

Signature · 1 line

1.6.3.3

Ben Dooks

author

2010-05-12 02:35 UTC #9 lore raw

PATCH 8/15 ARM: S3C24XX: Identify S3C2416 if S3C2412/S3C2413 built in

In reply to Ben Dooks

Extend the ARMv5 ID code to deal with S3C2416 being built with S3C2412/S3C2413 enabled, as these have their ID registers in a different place.

Signed-off-by Ben Dooks <[email protected]>

---
 arch/arm/plat-s3c24xx/cpu.c |   12 ++++++++++--
 1 files changed, 10 insertions(+), 2 deletions(-)

arch/arm/plat-s3c24xx/cpu.c +10 -2

index 494f4f3..32db856 100644
@@ -181,10 +181,18 @@ static struct map_desc s3c_iodesc[] __initdata = {
 
 static unsigned long s3c24xx_read_idcode_v5(void)
 {
+#if defined(CONFIG_CPU_S3C2416)
+	/* s3c2416 is v5, with S3C24XX_GSTATUS1 instead of S3C2412_GSTATUS1 */
+
+	u32 gs = __raw_readl(S3C24XX_GSTATUS1);
+
+	/* test for s3c2416 or similar device */
+	if ((gs >> 16) == 0x3245)
+		return gs;
+#endif
+
 #if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
 	return __raw_readl(S3C2412_GSTATUS1);
-#elif defined(CONFIG_CPU_S3C2416)
-	return __raw_readl(S3C24XX_GSTATUS1);
 #else
 	return 1UL;	/* don't look like an 2400 */
 #endif

Signature · 1 line

1.6.3.3

Ben Dooks

author

2010-05-12 02:36 UTC #10 lore raw

PATCH 9/15 ARM: S3C2443: Move parts of the clock code to common clock file

In reply to Ben Dooks

To share code with some of the newer parts such as the S3C2416, move parts of arch/arm/mach-s3c2443/clock.c to a common file called arch/arm/plat-s3c24xx/s3c2443-clock.c.

Update the build configuration to deal with this new file.

Signed-off-by Ben Dooks <[email protected]>

---
 arch/arm/mach-s3c2443/Kconfig                |    1 +
 arch/arm/mach-s3c2443/clock.c                |  452 +------------------------
 arch/arm/plat-s3c24xx/Kconfig                |    6 +
 arch/arm/plat-s3c24xx/Makefile               |    1 +
 arch/arm/plat-s3c24xx/include/plat/s3c2443.h |   19 +
 arch/arm/plat-s3c24xx/s3c2443-clock.c        |  472 ++++++++++++++++++++++++++
 6 files changed, 505 insertions(+), 446 deletions(-)
 create mode 100644 arch/arm/plat-s3c24xx/s3c2443-clock.c

arch/arm/mach-s3c2443/Kconfig +1 -0

index 698140a..4fef723 100644
@@ -8,6 +8,7 @@ config CPU_S3C2443
 	select S3C2443_DMA if S3C2410_DMA
 	select CPU_LLSERIAL_S3C2440
 	select SAMSUNG_CLKSRC
+	select S3C2443_CLOCK
 	help
 	  Support for the S3C2443 SoC from the S3C24XX line

arch/arm/mach-s3c2443/clock.c +6 ~~-446~~

537 lines not on this page · raw message

arch/arm/plat-s3c24xx/Kconfig +6 -0

index a830fad..3ce8f01 100644
@@ -45,6 +45,12 @@ config S3C2410_CLOCK
 	  Clock code for the S3C2410, and similar processors which
 	  is currently includes the S3C2410, S3C2440, S3C2442.
 
+config S3C2443_CLOCK
+	bool
+	help
+	  Clock code for the S3C2443 and similar processors, which includes
+	  the S3C2416 and S3C2450.
+
 config S3C24XX_DCLK
 	bool
 	help

arch/arm/plat-s3c24xx/Makefile +1 -0

index c2237c4..44aea88 100644
@@ -30,6 +30,7 @@ obj-$(CONFIG_PM)		+= pm.o
 obj-$(CONFIG_PM)		+= irq-pm.o
 obj-$(CONFIG_PM)		+= sleep.o
 obj-$(CONFIG_S3C2410_CLOCK)	+= s3c2410-clock.o
+obj-$(CONFIG_S3C2443_CLOCK)	+= s3c2443-clock.o
 obj-$(CONFIG_S3C2410_DMA)	+= dma.o
 obj-$(CONFIG_S3C2410_IOTIMING)	+= s3c2410-iotiming.o
 obj-$(CONFIG_S3C2412_IOTIMING)	+= s3c2412-iotiming.o

arch/arm/plat-s3c24xx/include/plat/s3c2443.h +19 -0

index 815b107..a19715f 100644
@@ -30,3 +30,22 @@ extern  int s3c2443_baseclk_add(void);
 #define s3c2443_map_io NULL
 #define s3c2443_init NULL
 #endif
+
+/* common code used by s3c2443 and others.
+ * note, not to be used outside of arch/arm/mach-s3c* */
+
+struct clk;	/* some files don't need clk.h otherwise */
+
+typedef unsigned int (*pll_fn)(unsigned int reg, unsigned int base);
+typedef unsigned int (*fdiv_fn)(unsigned long clkcon0);
+
+extern void s3c2443_common_setup_clocks(pll_fn get_mpll, fdiv_fn fdiv);
+extern void s3c2443_common_init_clocks(int xtal, pll_fn get_mpll, fdiv_fn fdiv);
+
+extern int s3c2443_clkcon_enable_h(struct clk *clk, int enable);
+extern int s3c2443_clkcon_enable_p(struct clk *clk, int enable);
+extern int s3c2443_clkcon_enable_s(struct clk *clk, int enable);
+
+extern struct clksrc_clk clk_epllref;
+extern struct clksrc_clk clk_esysclk;
+extern struct clksrc_clk clk_msysclk;

arch/arm/plat-s3c24xx/s3c2443-clock.c new file +472 -0

472 lines not on this page · raw message

Signature · 1 line

1.6.3.3

Ben Dooks

author

2010-05-12 02:36 UTC #11 lore raw

PATCH 10/15 ARM: S3C2416: Add basic clock support

In reply to Ben Dooks

Add basic clock support for the PLLs, HSMMC channels and PWM clocks. This is enough to get a basic system up and running.

Signed-off-by Ben Dooks <[email protected]>

---
 arch/arm/mach-s3c2410/include/mach/regs-clock.h |    2 +
 arch/arm/mach-s3c2416/Kconfig                   |    2 +
 arch/arm/mach-s3c2416/Makefile                  |    2 +-
 arch/arm/mach-s3c2416/clock.c                   |  135 +++++++++++++++++++++++
 arch/arm/plat-s3c24xx/include/plat/pll.h        |   25 ++++
 5 files changed, 165 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-s3c2416/clock.c

arch/arm/mach-s3c2410/include/mach/regs-clock.h +2 -0

index 9a0d169..3415b60 100644
@@ -161,4 +161,6 @@
 
 #endif /* CONFIG_CPU_S3C2412 | CONFIG_CPU_S3C2413 */
 
+#define S3C2416_CLKDIV2		S3C2410_CLKREG(0x28)
+
 #endif /* __ASM_ARM_REGS_CLOCK */

arch/arm/mach-s3c2416/Kconfig +2 -0

index 528f273..677f963 100644
@@ -10,6 +10,8 @@ config CPU_S3C2416
 	select CPU_ARM926T
 	select S3C2416_DMA if S3C2410_DMA
 	select CPU_LLSERIAL_S3C2440
+	select SAMSUNG_CLKSRC
+	select S3C2443_CLOCK
 	help
 	  Support for the S3C2416 SoC from the S3C24XX line

arch/arm/mach-s3c2416/Makefile +1 -1

index 9183e81..6c12c7b 100644
@@ -9,7 +9,7 @@ obj-m				:=
 obj-n				:=
 obj-				:=
 
-obj-$(CONFIG_CPU_S3C2416)	+= s3c2416.o
+obj-$(CONFIG_CPU_S3C2416)	+= s3c2416.o clock.o
 obj-$(CONFIG_CPU_S3C2416)	+= irq.o
 
 #obj-$(CONFIG_S3C2416_DMA)	+= dma.o

arch/arm/mach-s3c2416/clock.c new file +135 -0

135 lines not on this page · raw message

arch/arm/plat-s3c24xx/include/plat/pll.h +25 -0

index 7ea8bff..005729a 100644
@@ -35,3 +35,28 @@ s3c24xx_get_pll(unsigned int pllval, unsigned int baseclk)
 
 	return (unsigned int)fvco;
 }
+
+#define S3C2416_PLL_M_SHIFT	(14)
+#define S3C2416_PLL_P_SHIFT	(5)
+#define S3C2416_PLL_S_MASK	(7)
+#define S3C2416_PLL_M_MASK	((1 << 10) - 1)
+#define S3C2416_PLL_P_MASK	(63)
+
+static inline unsigned int
+s3c2416_get_pll(unsigned int pllval, unsigned int baseclk)
+{
+	unsigned int m, p, s;
+	uint64_t fvco;
+
+	m = pllval >> S3C2416_PLL_M_SHIFT;
+	p = pllval >> S3C2416_PLL_P_SHIFT;
+
+	s = pllval & S3C2416_PLL_S_MASK;
+	m &= S3C2416_PLL_M_MASK;
+	p &= S3C2416_PLL_P_MASK;
+
+	fvco = (uint64_t)baseclk * m;
+	do_div(fvco, (p << s));
+
+	return (unsigned int)fvco;
+}

Signature · 1 line

1.6.3.3

Ben Dooks

author

2010-05-12 02:36 UTC #12 lore raw

PATCH 11/15 ARM: S3C2416: Add support for second HSMMC channel

In reply to Ben Dooks

Add support for the second HSMMC channel on the S3C2416.

Signed-off-by Ben Dooks <[email protected]>

---
 arch/arm/mach-s3c2410/include/mach/irqs.h |    3 +++
 arch/arm/mach-s3c2410/include/mach/map.h  |    5 +++--
 arch/arm/mach-s3c2416/Kconfig             |    1 +
 arch/arm/mach-s3c2416/mach-smdk2416.c     |    1 +
 4 files changed, 8 insertions(+), 2 deletions(-)

arch/arm/mach-s3c2410/include/mach/irqs.h +3 -0

index c1b8ec0..877c15e 100644
@@ -150,7 +150,10 @@
 #define IRQ_S3C2443_HSMMC	S3C2410_IRQ(20)		/* IRQ_SDI */
 #define IRQ_S3C2443_NAND	S3C2410_IRQ(24)		/* reserved */
 
+#define IRQ_S3C2416_HSMMC0	S3C2410_IRQ(21)		/* S3C2416/S3C2450 */
+
 #define IRQ_HSMMC0		IRQ_S3C2443_HSMMC
+#define IRQ_HSMMC1		IRQ_S3C2416_HSMMC0
 
 #define IRQ_S3C2443_LCD1	S3C2410_IRQSUB(14)
 #define IRQ_S3C2443_LCD2	S3C2410_IRQSUB(15)

arch/arm/mach-s3c2410/include/mach/map.h +3 -2

index b049e61..f07d680 100644
@@ -63,9 +63,9 @@
 #define S3C2440_PA_AC97	   (0x5B000000)
 #define S3C2440_SZ_AC97	   SZ_1M
 
-/* S3C2443 High-speed SD/MMC */
+/* S3C2443/S3C2416 High-speed SD/MMC */
 #define S3C2443_PA_HSMMC   (0x4A800000)
-#define S3C2443_SZ_HSMMC   (256)
+#define S3C2416_PA_HSMMC0  (0x4AC00000)
 
 /* S3C2412 memory and IO controls */
 #define S3C2412_PA_SSMC	(0x4F000000)

@@ -110,6 +110,7 @@
 #define S3C_PA_UART	    S3C24XX_PA_UART
 #define S3C_PA_USBHOST	S3C2410_PA_USBHOST
 #define S3C_PA_HSMMC0	    S3C2443_PA_HSMMC
+#define S3C_PA_HSMMC1	    S3C2416_PA_HSMMC0
 #define S3C_PA_NAND	    S3C24XX_PA_NAND
 
 #endif /* __ASM_ARCH_MAP_H */

arch/arm/mach-s3c2416/Kconfig +1 -0

index 677f963..a1308d4 100644
@@ -27,6 +27,7 @@ config MACH_SMDK2416
 	bool "SMDK2416"
 	select CPU_S3C2416
 	select S3C_DEV_HSMMC
+	select S3C_DEV_HSMMC1
 	help
 	  Say Y here if you are using an SMDK2416

arch/arm/mach-s3c2416/mach-smdk2416.c +1 -0

index 8c9aed6..a51973c 100644
@@ -112,6 +112,7 @@ static struct platform_device *smdk2416_devices[] __initdata = {
 	&s3c_device_wdt,
 	&s3c_device_i2c0,
 	&s3c_device_hsmmc0,
+	&s3c_device_hsmmc1,
 };
 
 static void __init smdk2416_map_io(void)

Signature · 1 line

1.6.3.3

Darius Augulis

2010-06-17 19:05 UTC #13 lore raw

PATCH 11/15 ARM: S3C2416: Add support for second HSMMC channel

Quoted 1 line · Ben Dooks

Add support for the second HSMMC channel on the S3C2416.

There is issue with mach-s3c2416 and sdhci-s3c driver. Driver probe crashes with following backtrace:

sdhci: Secure Digital Host Controller Interface driver
sdhci: Copyright(c) Pierre Ossman

Unable to handle kernel NULL pointer dereference at virtual address 00000000
pgd = c0004000
[00000000] *pgd=00000000
Internal error: Oops: 5 [#1]
last sysfs file:
CPU: 0    Not tainted  (2.6.35-rc3-00001-g7dfb002 #31)
PC is at sdhci_s3c_probe+0x188/0x42c
LR is at clk_enable+0x50/0x60

The reason is not completely initialised s3c_sdhci_platdata structure. When getting clocks in sdhci_s3c_probe():

for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
                 struct clk *clk;
                 char *name = pdata->clocks[ptr];

Pointer clocks is not initialised at all, because mach-s3c2416 doesn't have such helpers like mach-s3c64xx does:

s3c6400_default_sdhci0()
s3c6400_default_sdhci1()
s3c6400_default_sdhci2()

Also other necessary s3c_sdhci_platdata members cfg_gpio and cfg_card are missing on s3c2416.

Is there any patch adding this missing info to mach-s3c2416?

Quoted 72 lines

Signed-off-by Ben Dooks<[email protected]>

---
  arch/arm/mach-s3c2410/include/mach/irqs.h |    3 +++
  arch/arm/mach-s3c2410/include/mach/map.h  |    5 +++--
  arch/arm/mach-s3c2416/Kconfig             |    1 +
  arch/arm/mach-s3c2416/mach-smdk2416.c     |    1 +
  4 files changed, 8 insertions(+), 2 deletions(-)

arch/arm/mach-s3c2410/include/mach/irqs.h +3 -0

index c1b8ec0..877c15e 100644
@@ -150,7 +150,10 @@
  #define IRQ_S3C2443_HSMMC	S3C2410_IRQ(20)		/* IRQ_SDI */
  #define IRQ_S3C2443_NAND	S3C2410_IRQ(24)		/* reserved */
 
+#define IRQ_S3C2416_HSMMC0	S3C2410_IRQ(21)		/* S3C2416/S3C2450 */
+
  #define IRQ_HSMMC0		IRQ_S3C2443_HSMMC
+#define IRQ_HSMMC1		IRQ_S3C2416_HSMMC0
 
  #define IRQ_S3C2443_LCD1	S3C2410_IRQSUB(14)
  #define IRQ_S3C2443_LCD2	S3C2410_IRQSUB(15)

arch/arm/mach-s3c2410/include/mach/map.h +3 -2

index b049e61..f07d680 100644
@@ -63,9 +63,9 @@
  #define S3C2440_PA_AC97	   (0x5B000000)
  #define S3C2440_SZ_AC97	   SZ_1M
 
-/* S3C2443 High-speed SD/MMC */
+/* S3C2443/S3C2416 High-speed SD/MMC */
  #define S3C2443_PA_HSMMC   (0x4A800000)
-#define S3C2443_SZ_HSMMC   (256)
+#define S3C2416_PA_HSMMC0  (0x4AC00000)
 
  /* S3C2412 memory and IO controls */
  #define S3C2412_PA_SSMC	(0x4F000000)

@@ -110,6 +110,7 @@
  #define S3C_PA_UART	    S3C24XX_PA_UART
  #define S3C_PA_USBHOST	S3C2410_PA_USBHOST
  #define S3C_PA_HSMMC0	    S3C2443_PA_HSMMC
+#define S3C_PA_HSMMC1	    S3C2416_PA_HSMMC0
  #define S3C_PA_NAND	    S3C24XX_PA_NAND
 
  #endif /* __ASM_ARCH_MAP_H */

arch/arm/mach-s3c2416/Kconfig +1 -0

index 677f963..a1308d4 100644
@@ -27,6 +27,7 @@ config MACH_SMDK2416
  	bool "SMDK2416"
  	select CPU_S3C2416
  	select S3C_DEV_HSMMC
+	select S3C_DEV_HSMMC1
  	help
  	  Say Y here if you are using an SMDK2416

arch/arm/mach-s3c2416/mach-smdk2416.c +1 -0

index 8c9aed6..a51973c 100644
@@ -112,6 +112,7 @@ static struct platform_device *smdk2416_devices[] __initdata = {
  	&s3c_device_wdt,
  	&s3c_device_i2c0,
  	&s3c_device_hsmmc0,
+	&s3c_device_hsmmc1,
  };
 
  static void __init smdk2416_map_io(void)

Yauhen Kharuzhy

2010-06-17 19:19 UTC #14 lore raw

PATCH 11/15 ARM: S3C2416: Add support for second HSMMC channel

Quoted 27 lines · Darius Augulis

Quoted 1 line · Ben Dooks
Add support for the second HSMMC channel on the S3C2416.
There is issue with mach-s3c2416 and sdhci-s3c driver. Driver probe crashes with following backtrace:
sdhci: Secure Digital Host Controller Interface driver
sdhci: Copyright(c) Pierre Ossman
Unable to handle kernel NULL pointer dereference at virtual address 00000000
pgd = c0004000
[00000000] *pgd=00000000
Internal error: Oops: 5 [#1]
last sysfs file:
CPU: 0    Not tainted  (2.6.35-rc3-00001-g7dfb002 #31)
PC is at sdhci_s3c_probe+0x188/0x42c
LR is at clk_enable+0x50/0x60
The reason is not completely initialised s3c_sdhci_platdata structure. When getting clocks in sdhci_s3c_probe():
for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
                struct clk *clk;
                char *name = pdata->clocks[ptr];
Pointer clocks is not initialised at all, because mach-s3c2416 doesn't have such helpers like mach-s3c64xx does:

Quoted 8 lines

s3c6400_default_sdhci0()
s3c6400_default_sdhci1()
s3c6400_default_sdhci2()
Also other necessary s3c_sdhci_platdata members cfg_gpio and cfg_card are missing on s3c2416.
Is there any patch adding this missing info to mach-s3c2416?

I am already wrote such patch today and will post it after testing tomorrow, I hope.

Signature · 5 lines

Yauhen Kharuzhy		jekhor _at_ gmail.com
			JID: jek at jabber.ru

A: No
Q: Should I quote below my post?

Darius Augulis

2010-06-18 18:30 UTC #15 lore raw

PATCH 11/15 ARM: S3C2416: Add support for second HSMMC channel

Quoted 32 lines · Yauhen Kharuzhy

Quoted 31 lines · Darius Augulis
Quoted 1 line · Ben Dooks
Add support for the second HSMMC channel on the S3C2416.
There is issue with mach-s3c2416 and sdhci-s3c driver. Driver probe crashes with following backtrace:
sdhci: Secure Digital Host Controller Interface driver
sdhci: Copyright(c) Pierre Ossman
Unable to handle kernel NULL pointer dereference at virtual address 00000000
pgd = c0004000
[00000000] *pgd=00000000
Internal error: Oops: 5 [#1]
last sysfs file:
CPU: 0    Not tainted  (2.6.35-rc3-00001-g7dfb002 #31)
PC is at sdhci_s3c_probe+0x188/0x42c
LR is at clk_enable+0x50/0x60
The reason is not completely initialised s3c_sdhci_platdata structure. When getting clocks in sdhci_s3c_probe():
for (clks = 0, ptr = 0; ptr<  MAX_BUS_CLK; ptr++) {
                 struct clk *clk;
                 char *name = pdata->clocks[ptr];
Pointer clocks is not initialised at all, because mach-s3c2416 doesn't have such helpers like mach-s3c64xx does:
s3c6400_default_sdhci0()
s3c6400_default_sdhci1()
s3c6400_default_sdhci2()

Quoted 7 lines

Quoted 4 lines
Also other necessary s3c_sdhci_platdata members cfg_gpio and cfg_card are missing on s3c2416.
Is there any patch adding this missing info to mach-s3c2416?
I am already wrote such patch today and will post it after testing tomorrow, I hope.

Hi Yauhen,

could you please send me this patch? I will test it too by my side. thanks.

Quoted 1 line

Ben Dooks

author

2010-05-12 02:36 UTC #16 lore raw

PATCH 12/15 ARM: S3C2416: Add support for OHCI on SMDK2416

In reply to Ben Dooks

Add device definition and ensure that the host port is powered up at start time. Full power control can be added at a later date.

Signed-off-by Ben Dooks <[email protected]>

---
 arch/arm/mach-s3c2416/mach-smdk2416.c |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

arch/arm/mach-s3c2416/mach-smdk2416.c +5 -0

index a51973c..99d24c4 100644
@@ -21,6 +21,7 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/mtd/partitions.h>
+#include <linux/gpio.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>

@@ -110,6 +111,7 @@ static struct s3c2410_uartcfg smdk2416_uartcfgs[] __initdata = {
 
 static struct platform_device *smdk2416_devices[] __initdata = {
 	&s3c_device_wdt,
+	&s3c_device_ohci,
 	&s3c_device_i2c0,
 	&s3c_device_hsmmc0,
 	&s3c_device_hsmmc1,

@@ -128,6 +130,9 @@ static void __init smdk2416_machine_init(void)
 {
 	s3c_i2c0_set_platdata(NULL);
 
+	gpio_request(S3C2410_GPB(4), "USBHost Power");
+	gpio_direction_output(S3C2410_GPB(4), 1);
+
 	platform_add_devices(smdk2416_devices, ARRAY_SIZE(smdk2416_devices));
 	smdk_machine_init();
 }

Signature · 1 line

1.6.3.3

Ben Dooks

author

2010-05-12 02:36 UTC #17 lore raw

PATCH 13/15 ARM: S3C2416: Use s3c2440 style i2c controller

In reply to Ben Dooks

The s3c2416 i2c controllers are compatible with the s3c2440 style i2c block, so change the device name appropriately.

Signed-off-by Ben Dooks <[email protected]>y

---
 arch/arm/mach-s3c2416/s3c2416.c |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

arch/arm/mach-s3c2416/s3c2416.c +6 -0

index 6165dc7..ad5a63a 100644
@@ -50,6 +50,8 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 
+#include <plat/iic-core.h>
+
 static struct map_desc s3c2416_iodesc[] __initdata = {
 	IODESC_ENT(WATCHDOG),
 	IODESC_ENT(CLKPWR),

@@ -80,6 +82,10 @@ int __init s3c2416_init(void)
 	s3c_device_wdt.resource[1].start = IRQ_S3C2443_WDT;
 	s3c_device_wdt.resource[1].end   = IRQ_S3C2443_WDT;
 
+	/* the i2c devices are directly compatible with s3c2440 */
+	s3c_i2c0_setname("s3c2440-i2c");
+	s3c_i2c1_setname("s3c2440-i2c");
+
 	return sysdev_register(&s3c2416_sysdev);
 }

Signature · 1 line

1.6.3.3

Ben Dooks

author

2010-05-12 02:36 UTC #18 lore raw

PATCH 14/15 ARM: S3C2413: Update GPIO pull-up support

In reply to Ben Dooks

Ensure the right get/set pull code is selected and assigned to the GPIO core.

Signed-off-by Ben Dooks <[email protected]>

---
 arch/arm/mach-s3c2416/Kconfig   |    1 +
 arch/arm/mach-s3c2416/s3c2416.c |    7 +++++++
 2 files changed, 8 insertions(+), 0 deletions(-)

arch/arm/mach-s3c2416/Kconfig +1 -0

index a1308d4..6d077b2 100644
@@ -10,6 +10,7 @@ config CPU_S3C2416
 	select CPU_ARM926T
 	select S3C2416_DMA if S3C2410_DMA
 	select CPU_LLSERIAL_S3C2440
+	select S3C_GPIO_PULL_UPDOWN
 	select SAMSUNG_CLKSRC
 	select S3C2443_CLOCK
 	help

arch/arm/mach-s3c2416/s3c2416.c +7 -0

index ad5a63a..3bff057 100644
@@ -28,6 +28,7 @@
 #include <linux/list.h>
 #include <linux/timer.h>
 #include <linux/init.h>
+#include <linux/gpio.h>
 #include <linux/platform_device.h>
 #include <linux/serial_core.h>
 #include <linux/sysdev.h>

@@ -46,6 +47,9 @@
 #include <mach/idle.h>
 #include <mach/regs-s3c2443-clock.h>
 
+#include <plat/gpio-core.h>
+#include <plat/gpio-cfg.h>
+#include <plat/gpio-cfg-helpers.h>
 #include <plat/s3c2416.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>

@@ -104,6 +108,9 @@ void __init s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 
 void __init s3c2416_map_io(void)
 {
+	s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_updown;
+	s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_updown;
+
 	iotable_init(s3c2416_iodesc, ARRAY_SIZE(s3c2416_iodesc));
 }

Signature · 1 line

1.6.3.3

Ben Dooks

author

2010-05-12 02:36 UTC #19 lore raw

PATCH 15/15 ARM: SAMSUNG: Update S3C2416 entry with S3C2450

In reply to Ben Dooks

These devices are so similar that they share the same SoC ID code, so note this.

Signed-off-by Ben Dooks <[email protected]>

---
 arch/arm/Kconfig              |    6 +++++-
 arch/arm/mach-s3c2416/Kconfig |    3 +++
 arch/arm/plat-s3c24xx/cpu.c   |    2 +-
 3 files changed, 9 insertions(+), 2 deletions(-)

arch/arm/Kconfig +5 -1

index 6785c33..3f8718f 100644
@@ -647,7 +647,7 @@ config ARCH_SA1100
 	  Support for StrongARM 11x0 based boards.
 
 config ARCH_S3C2410
-	bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443"
+	bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
 	select GENERIC_GPIO
 	select ARCH_HAS_CPUFREQ
 	select HAVE_CLK

@@ -656,6 +656,10 @@ config ARCH_S3C2410
 	  BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
 	  the Samsung SMDK2410 development board (and derivatives).
 
+	  Note, the S3C2416 and the S3C2450 are so close that they even share
+	  the same SoC ID code. This means that there is no seperate machine
+	  directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
+
 config ARCH_S3C64XX
 	bool "Samsung S3C64XX"
 	select PLAT_SAMSUNG

arch/arm/mach-s3c2416/Kconfig +3 -0

index 6d077b2..29103a6 100644
@@ -4,6 +4,9 @@
 #
 # Licensed under GPLv2
 
+# note, this also supports the S3C2450 which is so similar it has the same
+# ID code as the S3C2416.
+
 config CPU_S3C2416
 	bool
 	depends on ARCH_S3C2410

arch/arm/plat-s3c24xx/cpu.c +1 -1

index 32db856..76d0858 100644
@@ -58,7 +58,7 @@
 static const char name_s3c2400[]  = "S3C2400";
 static const char name_s3c2410[]  = "S3C2410";
 static const char name_s3c2412[]  = "S3C2412";
-static const char name_s3c2416[]  = "S3C2416";
+static const char name_s3c2416[]  = "S3C2416/S3C2450";
 static const char name_s3c2440[]  = "S3C2440";
 static const char name_s3c2442[]  = "S3C2442";
 static const char name_s3c2442b[]  = "S3C2442B";

Signature · 1 line

1.6.3.3