OMAP4: Smartreflex and Voltage layer support

-----Original Message-----
From: [email protected] [mailto:linux-omap- [email protected]] On Behalf Of Thara Gopinath
Sent: Saturday, September 25, 2010 6:21 PM
To: [email protected]
Cc: [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; Thara Gopinath
Subject: [PATCH v2 03/11] OMAP4: Add the new voltage to vsel calculation formula

TWL6030 the power IC used along with OMAP4 in OMAP4 SDPs, blaze boards and panda boards has a different formula from that of TWL4030 for voltage to vsel and
vsel to voltage calculation. This patch implements the new formula depending on the PMIC type.

Signed-off-by Thara Gopinath <[email protected]>

---
 arch/arm/plat-omap/opp_twl_tps.c |   71
++++++++++++++++++++++++++++++++++++++
 1 files changed, 71 insertions(+), 0 deletions(-)

arch/arm/plat- renamed from arch/arm/plat-omap/opp_twl_tps.c +0 -0

omap/opp_twl_tps.c
index 4448fc5..358b67b 100644

arch/arm/plat-omap/opp_twl_tps.c +8 -0

@@ -15,9 +15,16 @@
 
 #include <linux/module.h>
 
+#include <linux/i2c/twl.h>
+
 #include <plat/opp_twl_tps.h>
 #include <plat/voltage.h>
 
+static bool is_offset_valid;
+static u8 smps_offset;
+
+#define REG_SMPS_OFFSET         0xE0
+
 /**
  * omap_twl_vsel_to_vdc - convert TWL/TPS VSEL value to microvolts DC
  * @vsel: TWL/TPS VSEL value to convert

@@ -27,6 +34,38 @@
  */
 unsigned long omap_twl_vsel_to_uv(const u8 vsel)
 {
+	if (twl_class_is_6030()) {

arch/arm/plat-omap/opp_twl_tps.c +20 -0

+
+		if (smps_offset & 0x8) {
+			return ((((vsel - 1) * 125) + 7000)) * 100;
+		} else {
+			/*
+			 * In case of the supported voltage range being
+			 * between 0.6V - 1.3V, there is not specific
+			 * formula for voltage to vsel conversion above
+			 * 1.3V. There are special hardcoded values for
+			 * voltages above 1.3V. Currently we are hardcodig
+			 * only for 1.35 V which is used for 1GH OPP for
+			 * OMAP4430.
+			 */
+			if (vsel == 0x3A)
+				return 1350000;
+			return ((((vsel - 1) * 125) + 6000)) * 100;
+		}
+	}
+
 	return (((vsel * 125) + 6000)) * 100;
 }
 

@@ -40,6 +79,38 @@ unsigned long omap_twl_vsel_to_uv(const u8 vsel)
 u8 omap_twl_uv_to_vsel(unsigned long uv)
 {
 	/* Round up to higher voltage */
+	if (twl_class_is_6030()) {

arch/arm/plat-omap/opp_twl_tps.c +19 -1

+
+		if (smps_offset & 0x8) {
+			return DIV_ROUND_UP(uv - 700000, 12500) + 1;
+		} else {
+			/*
+			 * In case of the supported voltage range being
+			 * between 0.6V - 1.3V, there is not specific
+			 * formula for voltage to vsel conversion above
+			 * 1.3V. There are special hardcoded values for
+			 * voltages above 1.3V. Currently we are hardcodig
+			 * only for 1.35 V which is used for 1GH OPP for
+			 * OMAP4430.
+			 */
+			if (uv == 1350000)
+				return 0x3A;
+			return DIV_ROUND_UP(uv - 600000, 12500) + 1;
+		}
+	}
+
 	return DIV_ROUND_UP(uv - 600000, 12500);
 }
 
--

1.7.0.4

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Quoted 72 lines

-----Original Message-----
From: Manuel, Lesly Arackal
Sent: Monday, September 27, 2010 9:44 AM
To: Gopinath, Thara; [email protected]
Cc: [email protected]; [email protected]; Cousson, Benoit; Sripathy, Vishwanath; Sawant, Anand
Subject: RE: [PATCH v2 03/11] OMAP4: Add the new voltage to vsel calculation formula

Hi Thara,

Quoted 49 lines

-----Original Message-----
From: [email protected] [mailto:linux-omap- [email protected]] On Behalf Of Thara Gopinath
Sent: Saturday, September 25, 2010 6:21 PM
To: [email protected]
Cc: [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; Thara Gopinath
Subject: [PATCH v2 03/11] OMAP4: Add the new voltage to vsel calculation formula

TWL6030 the power IC used along with OMAP4 in OMAP4 SDPs, blaze boards and panda boards has a different formula from that of TWL4030 for voltage to vsel and
vsel to voltage calculation. This patch implements the new formula depending on the PMIC type.

Signed-off-by Thara Gopinath <[email protected]>

---
 arch/arm/plat-omap/opp_twl_tps.c |   71
++++++++++++++++++++++++++++++++++++++
 1 files changed, 71 insertions(+), 0 deletions(-)

arch/arm/plat- renamed from arch/arm/plat-omap/opp_twl_tps.c +0 -0

omap/opp_twl_tps.c
index 4448fc5..358b67b 100644

arch/arm/plat-omap/opp_twl_tps.c +8 -0

@@ -15,9 +15,16 @@
 
 #include <linux/module.h>
 
+#include <linux/i2c/twl.h>
+
 #include <plat/opp_twl_tps.h>
 #include <plat/voltage.h>
 
+static bool is_offset_valid;
+static u8 smps_offset;
+
+#define REG_SMPS_OFFSET         0xE0
+
 /**
  * omap_twl_vsel_to_vdc - convert TWL/TPS VSEL value to microvolts DC
  * @vsel: TWL/TPS VSEL value to convert

@@ -27,6 +34,38 @@
  */
 unsigned long omap_twl_vsel_to_uv(const u8 vsel)
 {
+	if (twl_class_is_6030()) {

arch/arm/plat-omap/opp_twl_tps.c line 47

Quoted 10 lines

arch/arm/plat-omap/opp_twl_tps.c +10 -0

+		/*
+		 * In TWL6030 depending on the value of SMPS_OFFSET
+		 * efuse register the voltage range supported in
+		 * standard mode can be either between 0.6V - 1.3V or
+		 * 0.7V - 1.4V. In TWL6030 ES1.0 SMPS_OFFSET efuse
+		 * is programmed to all 0's where as starting from
+		 * TWL6030 ES1.1 the efuse is programmed to 1
+		 */
+		if (!is_offset_valid) {
+			twl_i2c_read_u8(TWL6030_MODULE_ID0, &smps_offset,

0xE0);

Quoted 5 lines

arch/arm/plat-omap/opp_twl_tps.c line 49

Quoted 2 lines

arch/arm/plat-omap/opp_twl_tps.c +2 -0

+			is_offset_valid = true;
+		}

Is it necessary to do the i2c read each time to check the smps_offset? OR it can be done one time initially.

This patch extends the OMAP4 clock data to include various x2 clockc nodes as the clock framework skips a *2 whie calculating the dpll locked frequency.

Signed-off-by Thara Gopinath <[email protected]>

---
 arch/arm/mach-omap2/clock44xx_data.c |   40 +++++++++++++++++++++++++++------
 1 files changed, 32 insertions(+), 8 deletions(-)

arch/arm/mach-omap2/clock44xx_data.c +32 -8

index edf2c28..3652fda 100644
@@ -481,14 +481,21 @@ static struct clk dpll_core_m5_ck = {
 	.set_rate	= &omap2_clksel_set_rate,
 };
 
+static struct clk dpll_core_m5x2_ck = {
+	.name		= "dpll_core_m5x2_ck",
+	.parent		= &dpll_core_m5_ck,
+	.ops		= &clkops_null,
+	.recalc		= &omap3_clkoutx2_recalc,
+};
+
 static const struct clksel div_core_div[] = {
-	{ .parent = &dpll_core_m5_ck, .rates = div2_1to2_rates },
+	{ .parent = &dpll_core_m5x2_ck, .rates = div2_1to2_rates },
 	{ .parent = NULL },
 };
 
 static struct clk div_core_ck = {
 	.name		= "div_core_ck",
-	.parent		= &dpll_core_m5_ck,
+	.parent		= &dpll_core_m5x2_ck,
 	.clksel		= div_core_div,
 	.clksel_reg	= OMAP4430_CM_CLKSEL_CORE,
 	.clksel_mask	= OMAP4430_CLKSEL_CORE_MASK,

@@ -507,13 +514,13 @@ static const struct clksel_rate div4_1to8_rates[] = {
 };
 
 static const struct clksel div_iva_hs_clk_div[] = {
-	{ .parent = &dpll_core_m5_ck, .rates = div4_1to8_rates },
+	{ .parent = &dpll_core_m5x2_ck, .rates = div4_1to8_rates },
 	{ .parent = NULL },
 };
 
 static struct clk div_iva_hs_clk = {
 	.name		= "div_iva_hs_clk",
-	.parent		= &dpll_core_m5_ck,
+	.parent		= &dpll_core_m5x2_ck,
 	.clksel		= div_iva_hs_clk_div,
 	.clksel_reg	= OMAP4430_CM_BYPCLK_DPLL_IVA,
 	.clksel_mask	= OMAP4430_CLKSEL_0_1_MASK,

@@ -525,7 +532,7 @@ static struct clk div_iva_hs_clk = {
 
 static struct clk div_mpu_hs_clk = {
 	.name		= "div_mpu_hs_clk",
-	.parent		= &dpll_core_m5_ck,
+	.parent		= &dpll_core_m5x2_ck,
 	.clksel		= div_iva_hs_clk_div,
 	.clksel_reg	= OMAP4430_CM_BYPCLK_DPLL_MPU,
 	.clksel_mask	= OMAP4430_CLKSEL_0_1_MASK,

@@ -651,6 +658,13 @@ static struct clk dpll_iva_m4_ck = {
 	.set_rate	= &omap2_clksel_set_rate,
 };
 
+static struct clk dpll_iva_m4x2_ck = {
+	.name		= "dpll_iva_m4x2_ck",
+	.parent		= &dpll_iva_m4_ck,
+	.ops		= &clkops_null,
+	.recalc		= &omap3_clkoutx2_recalc,
+};
+
 static struct clk dpll_iva_m5_ck = {
 	.name		= "dpll_iva_m5_ck",
 	.parent		= &dpll_iva_ck,

@@ -663,6 +677,13 @@ static struct clk dpll_iva_m5_ck = {
 	.set_rate	= &omap2_clksel_set_rate,
 };
 
+static struct clk dpll_iva_m5x2_ck = {
+	.name		= "dpll_iva_m5x2_ck",
+	.parent		= &dpll_iva_m5_ck,
+	.ops		= &clkops_null,
+	.recalc		= &omap3_clkoutx2_recalc,
+};
+
 /* DPLL_MPU */
 static struct dpll_data dpll_mpu_dd = {
 	.mult_div1_reg	= OMAP4430_CM_CLKSEL_DPLL_MPU,

@@ -1350,7 +1371,7 @@ static struct clk dsp_fck = {
 	.enable_reg	= OMAP4430_CM_TESLA_TESLA_CLKCTRL,
 	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
 	.clkdm_name	= "tesla_clkdm",
-	.parent		= &dpll_iva_m4_ck,
+	.parent		= &dpll_iva_m4x2_ck,
 	.recalc		= &followparent_recalc,
 };
 

@@ -1725,7 +1746,7 @@ static struct clk iva_fck = {
 	.enable_reg	= OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
 	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
 	.clkdm_name	= "ivahd_clkdm",
-	.parent		= &dpll_iva_m5_ck,
+	.parent		= &dpll_iva_m5x2_ck,
 	.recalc		= &followparent_recalc,
 };
 

@@ -2089,7 +2110,7 @@ static struct clk sl2if_ick = {
 	.enable_reg	= OMAP4430_CM_IVAHD_SL2_CLKCTRL,
 	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
 	.clkdm_name	= "ivahd_clkdm",
-	.parent		= &dpll_iva_m5_ck,
+	.parent		= &dpll_iva_m5x2_ck,
 	.recalc		= &followparent_recalc,
 };
 

@@ -2782,6 +2803,7 @@ static struct omap_clk omap44xx_clks[] = {
 	CLK(NULL,	"dpll_core_m2_ck",		&dpll_core_m2_ck,	CK_443X),
 	CLK(NULL,	"ddrphy_ck",			&ddrphy_ck,	CK_443X),
 	CLK(NULL,	"dpll_core_m5_ck",		&dpll_core_m5_ck,	CK_443X),
+	CLK(NULL,	"dpll_core_m5x2_ck",		&dpll_core_m5x2_ck,	CK_443X),
 	CLK(NULL,	"div_core_ck",			&div_core_ck,	CK_443X),
 	CLK(NULL,	"div_iva_hs_clk",		&div_iva_hs_clk,	CK_443X),
 	CLK(NULL,	"div_mpu_hs_clk",		&div_mpu_hs_clk,	CK_443X),

@@ -2793,7 +2815,9 @@ static struct omap_clk omap44xx_clks[] = {
 	CLK(NULL,	"iva_hsd_byp_clk_mux_ck",	&iva_hsd_byp_clk_mux_ck,	CK_443X),
 	CLK(NULL,	"dpll_iva_ck",			&dpll_iva_ck,	CK_443X),
 	CLK(NULL,	"dpll_iva_m4_ck",		&dpll_iva_m4_ck,	CK_443X),
+	CLK(NULL,	"dpll_iva_m4x2_ck",		&dpll_iva_m4x2_ck,	CK_443X),
 	CLK(NULL,	"dpll_iva_m5_ck",		&dpll_iva_m5_ck,	CK_443X),
+	CLK(NULL,	"dpll_iva_m5x2_ck",		&dpll_iva_m5x2_ck,	CK_443X),
 	CLK(NULL,	"dpll_mpu_ck",			&dpll_mpu_ck,	CK_443X),
 	CLK(NULL,	"dpll_mpu_m2_ck",		&dpll_mpu_m2_ck,	CK_443X),
 	CLK(NULL,	"per_hs_clk_div_ck",		&per_hs_clk_div_ck,	CK_443X),

Quoted 16 lines

-----Original Message-----
From: Kevin Hilman [mailto:[email protected]]
Sent: Wednesday, September 29, 2010 4:39 AM
To: Gopinath, Thara
Cc: [email protected]; [email protected]; Cousson, Benoit; Sripathy, Vishwanath; Sawant, Anand
Subject: Re: [PATCH v2 04/11] OMAP4: Extend clock data.

Quoted 4 lines · Thara Gopinath

This patch extends the OMAP4 clock data to include various x2 clockc nodes as the clock framework skips a *2 whie calculating the dpll locked frequency.

Quoted 5 lines

Quoted 1 line

Signed-off-by Thara Gopinath <[email protected]>

Acked-by Kevin Hilman <[email protected]>

Please post this as a separate patch, and Paul can queue for 2.6.37.

Quoted 142 lines

Thanks,

Kevin

Quoted 2 lines

---
 arch/arm/mach-omap2/clock44xx_data.c |   40 +++++++++++++++++++++++++++---

---

arch/arm/mach-

Quoted 3 lines

 1 files changed, 32 insertions(+), 8 deletions(-)

arch/arm/mach- renamed from arch/arm/mach-omap2/clock44xx_data.c +0 -0

omap2/clock44xx_data.c

Quoted 108 lines

index edf2c28..3652fda 100644

arch/arm/mach-omap2/clock44xx_data.c +29 -8

@@ -481,14 +481,21 @@ static struct clk dpll_core_m5_ck = {
 	.set_rate	= &omap2_clksel_set_rate,
 };
 
+static struct clk dpll_core_m5x2_ck = {
+	.name		= "dpll_core_m5x2_ck",
+	.parent		= &dpll_core_m5_ck,
+	.ops		= &clkops_null,
+	.recalc		= &omap3_clkoutx2_recalc,
+};
+
 static const struct clksel div_core_div[] = {
-	{ .parent = &dpll_core_m5_ck, .rates = div2_1to2_rates },
+	{ .parent = &dpll_core_m5x2_ck, .rates = div2_1to2_rates },
 	{ .parent = NULL },
 };
 
 static struct clk div_core_ck = {
 	.name		= "div_core_ck",
-	.parent		= &dpll_core_m5_ck,
+	.parent		= &dpll_core_m5x2_ck,
 	.clksel		= div_core_div,
 	.clksel_reg	= OMAP4430_CM_CLKSEL_CORE,
 	.clksel_mask	= OMAP4430_CLKSEL_CORE_MASK,

@@ -507,13 +514,13 @@ static const struct clksel_rate div4_1to8_rates[] = {
 };
 
 static const struct clksel div_iva_hs_clk_div[] = {
-	{ .parent = &dpll_core_m5_ck, .rates = div4_1to8_rates },
+	{ .parent = &dpll_core_m5x2_ck, .rates = div4_1to8_rates },
 	{ .parent = NULL },
 };
 
 static struct clk div_iva_hs_clk = {
 	.name		= "div_iva_hs_clk",
-	.parent		= &dpll_core_m5_ck,
+	.parent		= &dpll_core_m5x2_ck,
 	.clksel		= div_iva_hs_clk_div,
 	.clksel_reg	= OMAP4430_CM_BYPCLK_DPLL_IVA,
 	.clksel_mask	= OMAP4430_CLKSEL_0_1_MASK,

@@ -525,7 +532,7 @@ static struct clk div_iva_hs_clk = {
 
 static struct clk div_mpu_hs_clk = {
 	.name		= "div_mpu_hs_clk",
-	.parent		= &dpll_core_m5_ck,
+	.parent		= &dpll_core_m5x2_ck,
 	.clksel		= div_iva_hs_clk_div,
 	.clksel_reg	= OMAP4430_CM_BYPCLK_DPLL_MPU,
 	.clksel_mask	= OMAP4430_CLKSEL_0_1_MASK,

@@ -651,6 +658,13 @@ static struct clk dpll_iva_m4_ck = {
 	.set_rate	= &omap2_clksel_set_rate,
 };
 
+static struct clk dpll_iva_m4x2_ck = {
+	.name		= "dpll_iva_m4x2_ck",
+	.parent		= &dpll_iva_m4_ck,
+	.ops		= &clkops_null,
+	.recalc		= &omap3_clkoutx2_recalc,
+};
+
 static struct clk dpll_iva_m5_ck = {
 	.name		= "dpll_iva_m5_ck",
 	.parent		= &dpll_iva_ck,

@@ -663,6 +677,13 @@ static struct clk dpll_iva_m5_ck = {
 	.set_rate	= &omap2_clksel_set_rate,
 };
 
+static struct clk dpll_iva_m5x2_ck = {
+	.name		= "dpll_iva_m5x2_ck",
+	.parent		= &dpll_iva_m5_ck,
+	.ops		= &clkops_null,
+	.recalc		= &omap3_clkoutx2_recalc,
+};
+
 /* DPLL_MPU */
 static struct dpll_data dpll_mpu_dd = {
 	.mult_div1_reg	= OMAP4430_CM_CLKSEL_DPLL_MPU,

@@ -1350,7 +1371,7 @@ static struct clk dsp_fck = {
 	.enable_reg	= OMAP4430_CM_TESLA_TESLA_CLKCTRL,
 	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
 	.clkdm_name	= "tesla_clkdm",
-	.parent		= &dpll_iva_m4_ck,
+	.parent		= &dpll_iva_m4x2_ck,
 	.recalc		= &followparent_recalc,
 };
 

@@ -1725,7 +1746,7 @@ static struct clk iva_fck = {
 	.enable_reg	= OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
 	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
 	.clkdm_name	= "ivahd_clkdm",
-	.parent		= &dpll_iva_m5_ck,
+	.parent		= &dpll_iva_m5x2_ck,
 	.recalc		= &followparent_recalc,
 };
 

@@ -2089,7 +2110,7 @@ static struct clk sl2if_ick = {
 	.enable_reg	= OMAP4430_CM_IVAHD_SL2_CLKCTRL,
 	.enable_bit	= OMAP4430_MODULEMODE_HWCTRL,
 	.clkdm_name	= "ivahd_clkdm",
-	.parent		= &dpll_iva_m5_ck,
+	.parent		= &dpll_iva_m5x2_ck,
 	.recalc		= &followparent_recalc,
 };
 

arch/arm/mach-omap2/clock44xx_data.c static struct omap_clk omap44xx_clks[] = { · line 2806

Quoted 4 lines

arch/arm/mach-omap2/clock44xx_data.c +1 -0

@@ -2782,6 +2803,7 @@ static struct omap_clk omap44xx_clks[] = {
 	CLK(NULL,	"dpll_core_m2_ck",		&dpll_core_m2_ck,	CK_443X),
 	CLK(NULL,	"ddrphy_ck",			&ddrphy_ck,	CK_443X),
 	CLK(NULL,	"dpll_core_m5_ck",		&dpll_core_m5_ck,	CK_443X),
+	CLK(NULL,	"dpll_core_m5x2_ck",		&dpll_core_m5x2_ck,

	CK_443X),

arch/arm/mach-omap2/clock44xx_data.c static struct omap_clk omap44xx_clks[] = { · line 2815

Quoted 5 lines

arch/arm/mach-omap2/clock44xx_data.c +0 -0

 	CLK(NULL,	"div_core_ck",			&div_core_ck,	CK_443X),
 	CLK(NULL,	"div_iva_hs_clk",		&div_iva_hs_clk,	CK_443X),
 	CLK(NULL,	"div_mpu_hs_clk",		&div_mpu_hs_clk,	CK_443X),

@@ -2793,7 +2815,9 @@ static struct omap_clk omap44xx_clks[] = {
 	CLK(NULL,	"iva_hsd_byp_clk_mux_ck",	&iva_hsd_byp_clk_mux_ck,

	CK_443X),

arch/arm/mach-omap2/clock44xx_data.c static struct omap_clk omap44xx_clks[] = {

Quoted 3 lines

arch/arm/mach-omap2/clock44xx_data.c +1 -0

 	CLK(NULL,	"dpll_iva_ck",			&dpll_iva_ck,	CK_443X),
 	CLK(NULL,	"dpll_iva_m4_ck",		&dpll_iva_m4_ck,	CK_443X),
+	CLK(NULL,	"dpll_iva_m4x2_ck",		&dpll_iva_m4x2_ck,

	CK_443X),

arch/arm/mach-omap2/clock44xx_data.c static struct omap_clk omap44xx_clks[] = { · line 2820

Quoted 2 lines

arch/arm/mach-omap2/clock44xx_data.c +1 -0

 	CLK(NULL,	"dpll_iva_m5_ck",		&dpll_iva_m5_ck,	CK_443X),
+	CLK(NULL,	"dpll_iva_m5x2_ck",		&dpll_iva_m5x2_ck,

	CK_443X),

arch/arm/mach-omap2/clock44xx_data.c static struct omap_clk omap44xx_clks[] = {

Quoted 3 lines

arch/arm/mach-omap2/clock44xx_data.c +0 -0

 	CLK(NULL,	"dpll_mpu_ck",			&dpll_mpu_ck,	CK_443X),
 	CLK(NULL,	"dpll_mpu_m2_ck",		&dpll_mpu_m2_ck,	CK_443X),
 	CLK(NULL,	"per_hs_clk_div_ck",		&per_hs_clk_div_ck,

	CK_443X),

arch/arm/plat-omap/include/plat/control.h +2 -0

index 042eb6e..1e8f6ec 100644
@@ -181,6 +181,18 @@
 #define OMAP3630_CONTROL_FUSE_OPP50_VDD2
 (OMAP2_CONTROL_GENERAL + 0x0128)
 #define OMAP3630_CONTROL_FUSE_OPP100_VDD2
 (OMAP2_CONTROL_GENERAL + 0x012C)
 
+/* 44xx control efuse offsets */
+#define OMAP44XX_CONTROL_FUSE_IVA_OPP50                0x22C

Quoted 13 lines · Thara Gopinath

arch/arm/plat-omap/include/plat/control.h +2 -0

index 042eb6e..1e8f6ec 100644
@@ -181,6 +181,18 @@
  #define OMAP3630_CONTROL_FUSE_OPP50_VDD2
 (OMAP2_CONTROL_GENERAL + 0x0128)
  #define OMAP3630_CONTROL_FUSE_OPP100_VDD2
 (OMAP2_CONTROL_GENERAL + 0x012C)
 
+/* 44xx control efuse offsets */
+#define OMAP44XX_CONTROL_FUSE_IVA_OPP50                0x22C

arch/arm/plat-omap/include/plat/control.h line 197

Quoted 10 lines

arch/arm/plat-omap/include/plat/control.h +10 -0

+#define OMAP44XX_CONTROL_FUSE_IVA_OPP100       0x22F
+#define OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO     0x232
+#define OMAP44XX_CONTROL_FUSE_IVA_OPPNITRO     0x235
+#define OMAP44XX_CONTROL_FUSE_MPU_OPP50                0x240
+#define OMAP44XX_CONTROL_FUSE_MPU_OPP100       0x243
+#define OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO     0x246
+#define OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO     0x249
+#define OMAP44XX_CONTROL_FUSE_CORE_OPP50       0x254
+#define OMAP44XX_CONTROL_FUSE_CORE_OPP100      0x257
+

These names are not consistent with the TRM (ES2.x NDA TRM vL). e.g. rather than MPU_OPP50, OPP1, the TRM has MPU_0, MPU_1. However, the TRM is confusing here too since the register names are MPU_0, MPU_1, etc. but the field names in the register descriptions use OPP50, OPP100, etc. What a mess. We need a consistent naming for these.

Benoit?

Also, based on the TRM, the offsets here don't look quite right. e.g. there is no MPU OPP at 0x240, so the OMAP4 the code reading these is using reserved/undocumented bits for the first OPP.

Also, the single byte offsets here could use a better explanation, not necessarily here but in the omap4 code that reads the nvalues. I expected that these would be single byte aligned to compact the address space and remove some unused space, but no, they seem to be arbitrarily shifted around.

Kevin

This patch adds dev attributes for smartreflex modules in the OMAP4 hwmod database. This patch also updates the smartreflex rev in the smartreflex class data structure in the OMAP4 hwmod database.

Signed-off-by Thara Gopinath<[email protected]>

---
  arch/arm/mach-omap2/omap_hwmod_44xx_data.c |   56 ++++++++++++++++++++++++++++
  arch/arm/plat-omap/include/plat/control.h  |   12 ++++++
  2 files changed, 68 insertions(+), 0 deletions(-)

arch/arm/mach-omap2/omap_hwmod_44xx_data.c +3 -0

index ba3c215..82657b5 100644
@@ -22,6 +22,8 @@
 
  #include<plat/omap_hwmod.h>
  #include<plat/cpu.h>
+#include<plat/smartreflex.h>
+#include<plat/control.h>
 
  #include "omap_hwmod_common_data.h"
 

@@ -474,6 +476,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
  static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
  	.name = "smartreflex",
  	.sysc =&omap44xx_smartreflex_sysc,
+	.rev  = 2,
  };
 
  /* smartreflex_core */

arch/arm/mach-omap2/omap_hwmod_44xx_data.c +46 -0

+
+static struct omap_sr_dev_data omap44xx_sr_core_dev_attr = {
+	.efuse_nvalues_offs	= omap44xx_sr_core_efuse_offs,
+	.test_sennenable	= 0x1,
+	.test_senpenable	= 0x1,
+	.test_nvalues		= omap44xx_sr_core_test_nvalues,
+	.vdd_name		= "core"
+};
+
  static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
  	.name		= "smartreflex_core",
  	.class		=&omap44xx_smartreflex_hwmod_class,

@@ -518,6 +537,7 @@ static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
  	},
  	.slaves		= omap44xx_smartreflex_core_slaves,
  	.slaves_cnt	= ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
+	.dev_attr	=&omap44xx_sr_core_dev_attr,
  	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  };
 

@@ -550,6 +570,23 @@ static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
  	&omap44xx_l4_cfg__smartreflex_iva,
  };
 
+static u32 omap44xx_sr_iva_efuse_offs[] = {
+	OMAP44XX_CONTROL_FUSE_IVA_OPP50, OMAP44XX_CONTROL_FUSE_IVA_OPP100,
+	OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO,
+};
+
+static u32 omap44xx_sr_iva_test_nvalues[] = {
+	0x0, 0x0, 0x0, 0x0
+};
+
+static struct omap_sr_dev_data omap44xx_sr_iva_dev_attr = {
+	.efuse_nvalues_offs	= omap44xx_sr_iva_efuse_offs,
+	.test_sennenable	= 0x1,
+	.test_senpenable	= 0x1,
+	.test_nvalues		= omap44xx_sr_iva_test_nvalues,
+	.vdd_name		= "iva"
+};
+
  static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
  	.name		= "smartreflex_iva",
  	.class		=&omap44xx_smartreflex_hwmod_class,

@@ -563,6 +600,7 @@ static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
  	},
  	.slaves		= omap44xx_smartreflex_iva_slaves,
  	.slaves_cnt	= ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
+	.dev_attr	=&omap44xx_sr_iva_dev_attr,
  	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  };
 

@@ -595,6 +633,23 @@ static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
  	&omap44xx_l4_cfg__smartreflex_mpu,
  };
 
+static u32 omap44xx_sr_mpu_efuse_offs[] = {
+	OMAP44XX_CONTROL_FUSE_MPU_OPP50, OMAP44XX_CONTROL_FUSE_MPU_OPP100,
+	OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO, OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO,
+};
+
+static u32 omap44xx_sr_mpu_test_nvalues[] = {
+	0x0, 0x0, 0x0, 0x0
+};
+
+static struct omap_sr_dev_data omap44xx_sr_mpu_dev_attr = {
+	.efuse_nvalues_offs	= omap44xx_sr_mpu_efuse_offs,
+	.test_sennenable	= 0x1,
+	.test_senpenable	= 0x1,
+	.test_nvalues		= omap44xx_sr_mpu_test_nvalues,
+	.vdd_name		= "mpu"
+};
+
  static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
  	.name		= "smartreflex_mpu",
  	.class		=&omap44xx_smartreflex_hwmod_class,

@@ -608,6 +663,7 @@ static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
  	},
  	.slaves		= omap44xx_smartreflex_mpu_slaves,
  	.slaves_cnt	= ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
+	.dev_attr	=&omap44xx_sr_mpu_dev_attr,
  	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  };
 

arch/arm/plat-omap/include/plat/control.h +12 -0

index 042eb6e..1e8f6ec 100644
@@ -181,6 +181,18 @@
  #define OMAP3630_CONTROL_FUSE_OPP50_VDD2        (OMAP2_CONTROL_GENERAL + 0x0128)
  #define OMAP3630_CONTROL_FUSE_OPP100_VDD2       (OMAP2_CONTROL_GENERAL + 0x012C)
 
+/* 44xx control efuse offsets */
+#define OMAP44XX_CONTROL_FUSE_IVA_OPP50		0x22C
+#define OMAP44XX_CONTROL_FUSE_IVA_OPP100	0x22F
+#define OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO	0x232
+#define OMAP44XX_CONTROL_FUSE_IVA_OPPNITRO	0x235
+#define OMAP44XX_CONTROL_FUSE_MPU_OPP50		0x240
+#define OMAP44XX_CONTROL_FUSE_MPU_OPP100	0x243
+#define OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO	0x246
+#define OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO	0x249
+#define OMAP44XX_CONTROL_FUSE_CORE_OPP50	0x254
+#define OMAP44XX_CONTROL_FUSE_CORE_OPP100	0x257
+
  /* AM35XX only CONTROL_GENERAL register offsets */
  #define AM35XX_CONTROL_MSUSPENDMUX_6    (OMAP2_CONTROL_GENERAL + 0x0038)
  #define AM35XX_CONTROL_DEVCONF2         (OMAP2_CONTROL_GENERAL + 0x0310)

Quoted 33 lines · Thara

This patch adds dev attributes for smartreflex modules in the OMAP4 hwmod database. This patch also updates the smartreflex rev in the smartreflex class data structure in the OMAP4 hwmod database.

Signed-off-by Thara Gopinath<[email protected]>

---
  arch/arm/mach-omap2/omap_hwmod_44xx_data.c |   56 ++++++++++++++++++++++++++++
  arch/arm/plat-omap/include/plat/control.h  |   12 ++++++
  2 files changed, 68 insertions(+), 0 deletions(-)

arch/arm/mach-omap2/omap_hwmod_44xx_data.c +3 -0

index ba3c215..82657b5 100644
@@ -22,6 +22,8 @@
 
  #include<plat/omap_hwmod.h>
  #include<plat/cpu.h>
+#include<plat/smartreflex.h>
+#include<plat/control.h>
 
  #include "omap_hwmod_common_data.h"
 

@@ -474,6 +476,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
  static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
  	.name = "smartreflex",
  	.sysc =&omap44xx_smartreflex_sysc,
+	.rev  = 2,
  };
 
  /* smartreflex_core */

arch/arm/mach-omap2/omap_hwmod_44xx_data.c static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = { · line 517

Quoted 10 lines

arch/arm/mach-omap2/omap_hwmod_44xx_data.c +7 -0

@@ -505,6 +508,22 @@ static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
  	&omap44xx_l4_cfg__smartreflex_core,
  };
 
+static u32 omap44xx_sr_core_efuse_offs[] = {
+	OMAP44XX_CONTROL_FUSE_CORE_OPP50, OMAP44XX_CONTROL_FUSE_CORE_OPP100,
+};
+
+static u32 omap44xx_sr_core_test_nvalues[] = {
+	0x0, 0x0
+};

At first, I thought it was a good idea to put such data here, but now after the discussion about timer hwmod data, I realize I was wrong.

These informations belong to omap_volt_data. For each OPP you should provide the efuse offset an the SW nvalues.
BTW, you should not call them test Nvalues, these are perfectly valid and can be potentially used in production. There are just not as optimized as a efuse Nvalue.

Quoted 48 lines · Benoit

Quoted 33 lines · Thara

This patch adds dev attributes for smartreflex modules in the OMAP4 hwmod database. This patch also updates the smartreflex rev in the smartreflex class data structure in the OMAP4 hwmod database.

Signed-off-by Thara Gopinath<[email protected]>

---
   arch/arm/mach-omap2/omap_hwmod_44xx_data.c |   56 ++++++++++++++++++++++++++++
   arch/arm/plat-omap/include/plat/control.h  |   12 ++++++
   2 files changed, 68 insertions(+), 0 deletions(-)

arch/arm/mach-omap2/omap_hwmod_44xx_data.c +3 -0

index ba3c215..82657b5 100644
@@ -22,6 +22,8 @@
 
   #include<plat/omap_hwmod.h>
   #include<plat/cpu.h>
+#include<plat/smartreflex.h>
+#include<plat/control.h>
 
   #include "omap_hwmod_common_data.h"
 

@@ -474,6 +476,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
   static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
   	.name = "smartreflex",
   	.sysc =&omap44xx_smartreflex_sysc,
+	.rev  = 2,
   };
 
   /* smartreflex_core */

arch/arm/mach-omap2/omap_hwmod_44xx_data.c static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = { · line 517

Quoted 10 lines

arch/arm/mach-omap2/omap_hwmod_44xx_data.c +7 -0

@@ -505,6 +508,22 @@ static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
   	&omap44xx_l4_cfg__smartreflex_core,
   };
 
+static u32 omap44xx_sr_core_efuse_offs[] = {
+	OMAP44XX_CONTROL_FUSE_CORE_OPP50, OMAP44XX_CONTROL_FUSE_CORE_OPP100,
+};
+
+static u32 omap44xx_sr_core_test_nvalues[] = {
+	0x0, 0x0
+};

At first, I thought it was a good idea to put such data here, but now after the discussion about timer hwmod data, I realize I was wrong.

Quoted 5 lines

These informations belong to omap_volt_data. For each OPP you should provide the efuse offset an the SW nvalues.
BTW, you should not call them test Nvalues, these are perfectly valid and can be potentially used in production. There are just not as optimized as a efuse Nvalue.

Just to clarify...

Benoit, what's your opinion of my comment that these values don't belong in the volt_data.