spi: spi-fsl-spi: Make spi-fsl-spi usable in cpu mode outside of FSL SOC environments and add a grlib variant normally running on sparc

This makes the cpu mode of the driver available outside of an FSL SOC and even powerpc environment. This is accomplished by putting things regarding fsl specific code and to cpm specific code within ifdefs.

Furthermore, this adds support for the mostly register-compatible SPICTRL core from the GRLIB VHDL IP core library normally running on sparc. A different entry in of_fsl_spi_match matches this core and indicates a different hardware type that is used to set up different function pointers and special cases. The fetching of irq is changed to work under sparc as well.

The GRLIB core operates in cpu mode and from the driver's point of view the important differences are that the number of bits per word might be limited and that there might be native chipselects selected via the added slvsel register. These differences if present are indicated by an added capabilities register.

---

This patch relies upon parts of the "of, of_gpio, of_spi: Fix and improve of_parse_phandle_with_args, of_gpio_named_count and of_spi_register_master" patchset - https://lkml.org/lkml/2012/12/27/54.

The grlib type has been tested under sparc, but the fsl type has only been compile tested, so it would be great if someone with an fsl board could test this out.

One could argue that it would be better to add the grlib variant as a mode flag in of_mpc8xxx_spi_probe instead of using a new type field, but that would require to add a flag for this core in include/linux/fsl_devices.h which does not feel right given that this core is not part of an fsl device.

Maybe the different out/in_be32 vs iowrite/read32be in spi-fsl-lib.h is over the top, but I'm not sure if there might be subtle differences between those on powerpc and I don't have any fsl hardware to try things out on.

 drivers/spi/Kconfig       |    4 +-
 drivers/spi/spi-fsl-lib.c |   10 ++
 drivers/spi/spi-fsl-lib.h |   19 +++
 drivers/spi/spi-fsl-spi.c |  276 ++++++++++++++++++++++++++++++++++++++-------
 4 files changed, 267 insertions(+), 42 deletions(-)

index 2e188e1..17db805 100644
@@ -218,11 +218,11 @@ config SPI_MPC512x_PSC
 
 config SPI_FSL_LIB
 	tristate
-	depends on FSL_SOC
+	depends on OF
 
 config SPI_FSL_SPI
 	bool "Freescale SPI controller"
-	depends on FSL_SOC
+	depends on OF
 	select SPI_FSL_LIB
 	help
 	  This enables using the Freescale SPI controllers in master mode.

index 8ade675..e3ea564 100644
@@ -23,7 +23,9 @@
 #include <linux/mm.h>
 #include <linux/of_platform.h>
 #include <linux/spi/spi.h>
+#ifdef CONFIG_FSL_SOC
 #include <sysdev/fsl_soc.h>
+#endif
 
 #include "spi-fsl-lib.h"
 

@@ -208,6 +210,7 @@ int of_mpc8xxx_spi_probe(struct platform_device *ofdev)
 	/* Allocate bus num dynamically. */
 	pdata->bus_num = -1;
 
+#ifdef CONFIG_FSL_SOC
 	/* SPI controller is either clocked from QE or SoC clock. */
 	pdata->sysclk = get_brgfreq();
 	if (pdata->sysclk == -1) {

@@ -217,16 +220,23 @@ int of_mpc8xxx_spi_probe(struct platform_device *ofdev)
 			goto err;
 		}
 	}
+#else
+	ret = of_property_read_u32(np, "clock-frequency", &pdata->sysclk);
+	if (ret)
+		goto err;
+#endif
 
 	prop = of_get_property(np, "mode", NULL);
 	if (prop && !strcmp(prop, "cpu-qe"))
 		pdata->flags = SPI_QE_CPU_MODE;
+#ifdef CONFIG_FSL_SOC
 	else if (prop && !strcmp(prop, "qe"))
 		pdata->flags = SPI_CPM_MODE | SPI_QE;
 	else if (of_device_is_compatible(np, "fsl,cpm2-spi"))
 		pdata->flags = SPI_CPM_MODE | SPI_CPM2;
 	else if (of_device_is_compatible(np, "fsl,cpm1-spi"))
 		pdata->flags = SPI_CPM_MODE | SPI_CPM1;
+#endif
 
 	return 0;
 

index cbe881b..f66f736 100644
@@ -34,8 +34,10 @@ struct mpc8xxx_spi {
 
 	int subblock;
 	struct spi_pram __iomem *pram;
+#ifdef CONFIG_FSL_SOC
 	struct cpm_buf_desc __iomem *tx_bd;
 	struct cpm_buf_desc __iomem *rx_bd;
+#endif
 
 	struct spi_transfer *xfer_in_progress;
 

@@ -67,6 +69,15 @@ struct mpc8xxx_spi {
 
 	unsigned int flags;
 
+#ifdef CONFIG_SPI_FSL_SPI
+	int type;
+	int native_chipselects;
+	u8 max_bits_per_word;
+
+	void (*set_shifts)(u32 *rx_shift, u32 *tx_shift,
+			   int bits_per_word, int msb_first);
+#endif
+
 	struct workqueue_struct *workqueue;
 	struct work_struct work;
 

@@ -87,12 +98,20 @@ struct spi_mpc8xxx_cs {
 
 static inline void mpc8xxx_spi_write_reg(__be32 __iomem *reg, u32 val)
 {
+#ifdef CONFIG_FSL_SOC
 	out_be32(reg, val);
+#else
+	iowrite32be(val, reg);
+#endif
 }
 
 static inline u32 mpc8xxx_spi_read_reg(__be32 __iomem *reg)
 {
+#ifdef CONFIG_FSL_SOC
 	return in_be32(reg);
+#else
+	return ioread32be(reg);
+#endif
 }
 
 struct mpc8xxx_spi_probe_info {

1.7.0.4

Any comments anyone?

This patch takes "Approach A" discussed and supported in
http://sourceforge.net/mailarchive/message.php?msg_id=30131080

Cheers,
Andreas Larsson

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I don't seem to have been CCed on the patch...

No, but I thought it might be useful to get you in the loop given the recent maintainerhood status change proposal.

You can find the patch at https://lkml.org/lkml/2012/12/28/83 or
http://sourceforge.net/mailarchive/message.php?msg_id=30280254

If you would like I'll resend the patch adding you to the CC list.

Cheers,
Andreas Larsson

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Yes, please.