Krait L1/L2 EDAC driver

The Krait L1/L2 error reporting device is made up of two interrupts, one per-CPU interrupt for the L1 caches and one interrupt for the L2 cache.

Cc Mark Rutland <[email protected]>

Cc Kumar Gala <[email protected]>

Cc <[email protected]>

Signed-off-by Stephen Boyd <[email protected]>

---
Documentation/devicetree/bindings/arm/cpus.txt | 49 ++++++++++++++++++++++++++

1 file changed, 49 insertions(+)

Documentation/devicetree/bindings/arm/cpus.txt +2 -0

index f32494d..0f7b27f 100644
@@ -44,6 +44,8 @@ For the ARM architecture every CPU node must contain the following properties:
 		"marvell,mohawk"
 		"marvell,xsc3"
 		"marvell,xscale"
+		"qcom,scorpion"
+		"qcom,krait"
 

Example:

Documentation/devicetree/bindings/arm/cpus.txt +43 -0

+
+ - compatible: Shall contain at least "cache"
+ - cache-level: Must be 2
+ - interrupts: Shall contain the L2 error interrupt
+
+Example:
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <1 9 0xf04>;
+		compatible = "qcom,krait";
+
+		cpu at 0 {
+			device_type = "cpu";
+			reg = <0>;
+			next-level-cache = <&L2>;
+		};
+
+		cpu at 1 {
+			device_type = "cpu";
+			reg = <1>;
+			next-level-cache = <&L2>;
+		};
+
+		cpu at 2 {
+			device_type = "cpu";
+			reg = <2>;
+			next-level-cache = <&L2>;
+		};
+
+		cpu at 3 {
+			device_type = "cpu";
+			reg = <3>;
+			next-level-cache = <&L2>;
+		};
+
+		L2: l2-cache {
+			compatible = "cache";
+			cache-level = <2>;
+			interrupts = <0 2 0x4>;
+		};
+	};

Signature · 2 lines

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Documentation/devicetree/bindings/arm/cpus.txt Example: · line 82

Quoted 7 lines · Stephen Boyd

Documentation/devicetree/bindings/arm/cpus.txt +3 -0

@@ -75,3 +77,50 @@ Example:
 			reg = <0x101>;
 		};
 	};
+
+If the compatible string contains "qcom,krait" there shall be an interrupts
+property containing the L1/CPU error interrupt number. There shall also be an

'also be a'

Documentation/devicetree/bindings/arm/cpus.txt Example: · line 83

Quoted 2 lines

Documentation/devicetree/bindings/arm/cpus.txt +1 -0

+l2-cache node containing the following properties:

Is the L1 interrupt not per core L1 cache (even if they are OR together at PIC)?

Quoted 14 lines

Documentation/devicetree/bindings/arm/cpus.txt +12 -0

+
+ - compatible: Shall contain at least "cache"
+ - cache-level: Must be 2
+ - interrupts: Shall contain the L2 error interrupt
+
+Example:
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <1 9 0xf04>;
+		compatible = "qcom,krait";

Quoted 10 lines · Kumar Gala

Documentation/devicetree/bindings/arm/cpus.txt Example: · line 82

Quoted 7 lines · Stephen Boyd

Documentation/devicetree/bindings/arm/cpus.txt +3 -0

@@ -75,3 +77,50 @@ Example:
 			reg = <0x101>;
 		};
 	};
+
+If the compatible string contains "qcom,krait" there shall be an interrupts
+property containing the L1/CPU error interrupt number. There shall also be an

'also be a'

ok

Quoted 3 lines

Documentation/devicetree/bindings/arm/cpus.txt Example: · line 83

Quoted 2 lines

Documentation/devicetree/bindings/arm/cpus.txt +1 -0

+l2-cache node containing the following properties:

Is the L1 interrupt not per core L1 cache (even if they are OR together at PIC)?

Yes it is per CPU. That is what the 0xf part of the cpus interrupts property is showing.

Quoted 13 lines

Documentation/devicetree/bindings/arm/cpus.txt Example: · line 95

Quoted 13 lines

Documentation/devicetree/bindings/arm/cpus.txt +11 -0

+ - compatible: Shall contain at least "cache"
+ - cache-level: Must be 2
+ - interrupts: Shall contain the L2 error interrupt
+
+Example:
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <1 9 0xf04>;
+		compatible = "qcom,krait";

Quoted 6 lines · Stephen Boyd

Quoted 3 lines · Kumar Gala

Quoted 1 line · Stephen Boyd

+l2-cache node containing the following properties:

Is the L1 interrupt not per core L1 cache (even if they are OR together at PIC)?

Yes it is per CPU. That is what the 0xf part of the cpus interrupts property is showing.

Than why not have it in each cpu node?

Quoted 6 lines · Kumar Gala

Quoted 4 lines · Stephen Boyd

Quoted 3 lines · Kumar Gala

Quoted 1 line · Stephen Boyd

+l2-cache node containing the following properties:

Is the L1 interrupt not per core L1 cache (even if they are OR together at PIC)?

Quoted 3 lines

Quoted 2 lines

Yes it is per CPU. That is what the 0xf part of the cpus interrupts property is showing.

Than why not have it in each cpu node?

Because that duplicates things unnecessarily? The cpus node can hold things that are common to all CPUs to avoid duplication. If it was a different PPI for each CPU then I would agree that we need to put it in each cpu node.

Quoted 9 lines · Stephen Boyd

Quoted 8 lines · Kumar Gala

Quoted 6 lines · Stephen Boyd

Quoted 3 lines · Kumar Gala

Quoted 1 line · Stephen Boyd

+l2-cache node containing the following properties:

Is the L1 interrupt not per core L1 cache (even if they are OR together at PIC)?

Yes it is per CPU. That is what the 0xf part of the cpus interrupts property is showing.

Quoted 6 lines

Quoted 1 line

Than why not have it in each cpu node?

Because that duplicates things unnecessarily? The cpus node can hold things that are common to all CPUs to avoid duplication. If it was a different PPI for each CPU then I would agree that we need to put it in each cpu node.

Ok, I'll accept that as the binding is specific to Krait (and I assume all SoCs w/Krait wire this up to a common interrupt)

Quoted 19 lines · Kumar Gala

Quoted 15 lines · Stephen Boyd

Quoted 9 lines · Kumar Gala

Quoted 6 lines · Stephen Boyd

Quoted 3 lines · Kumar Gala

Quoted 1 line · Stephen Boyd

+l2-cache node containing the following properties:

Is the L1 interrupt not per core L1 cache (even if they are OR together at PIC)?

Yes it is per CPU. That is what the 0xf part of the cpus interrupts property is showing.

Than why not have it in each cpu node?

Because that duplicates things unnecessarily? The cpus node can hold things that are common to all CPUs to avoid duplication. If it was a different PPI for each CPU then I would agree that we need to put it in each cpu node.

Quoted 2 lines

Ok, I'll accept that as the binding is specific to Krait (and I assume all SoCs w/Krait wire this up to a common interrupt)

Can I take that as an ack? I'll resend with the s/an/a/ fix today.

This allows us to probe the krait-edac driver.

Cc David Brown <[email protected]>

Signed-off-by Stephen Boyd <[email protected]>

---
arch/arm/boot/dts/qcom-msm8974.dtsi | 37 +++++++++++++++++++++++++++++++++++++

1 file changed, 37 insertions(+)