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This patch adds support for APM X-Gene SoC 15Gbps Multi-purpose PHY. This is the physical layer interface for the corresponding host controller. This driver uses the new PHY generic framework posted by Kishon Vijay Abrahm. In addition, the new PHY generic framework is patched to provide an function to set the speed of the PHY.
v4
* Update documentation with 'apm,' instead 'apm-'
* Change DTS override parameter to have 'apm,'
* Add select GENERIC_PHY to Kconfig PHY_XGENE
* Make override parameters to be pair of three values instead one
* Some minor comment and indentation changes
* Remove error register addition offset
* Add ULL to constants
* Use module_init instead subsys_initcall
* Make DTS node based on first register address
* Update override setting values
v3
* Major re-write of the code based on various review comments
* Support external clock only at the moment
* Support SATA mode only at the moment
* No UEFI support at the moment
v2
* Remove port knowledge from functions
* Make all functions static
* Remove ID completely
* Make resource requirement based on compatible type
* Rename override PHY parameters with more descriptive name
* Add override PHY parameter for per controller, per port, and per speed
* Patch the generic PHY frame to expose set_speed operation
v1
* Initial version
---
Loc Ho (4):
PHY: Add function set_speed to generic PHY framework
Documentation: Add APM X-Gene SoC 15Gbps Multi-purpose PHY driver
binding documentation
PHY: add APM X-Gene SoC 15Gbps Multi-purpose PHY driver
arm64: Add APM X-Gene SoC 15Gbps Multi-purpose PHY DTS entries
.../devicetree/bindings/ata/apm-xgene-phy.txt | 89 + arch/arm64/boot/dts/apm-storm.dtsi | 31 + drivers/phy/Kconfig | 7 + drivers/phy/Makefile | 2 + drivers/phy/phy-core.c | 21 + drivers/phy/phy-xgene.c | 1854 ++++++++++++++++++++ include/linux/phy/phy.h | 8 + 7 files changed, 2012 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/ata/apm-xgene-phy.txt create mode 100644 drivers/phy/phy-xgene.c
PATCH v4 1/4 PHY: Add function set_speed to generic PHY framework
This patch adds function set_speed to the generic PHY framework operation structure. This function can be called to instruct the PHY underlying layer at specified lane to configure for specified speed in hertz.
--- drivers/phy/phy-core.c | 21 +++++++++++++++++++++ include/linux/phy/phy.h | 8 ++++++++ 2 files changed, 29 insertions(+), 0 deletions(-)
drivers/phy/phy-core.c +21 -0
@@ -239,6 +239,27 @@ out: }EXPORT_SYMBOL_GPL (phy_power_off); +int phy_set_speed (struct phy *phy,int lane,u64 speed) +{ +int ret = -ENOTSUPP ; + +mutex_lock (&phy->mutex); +if (phy->ops->set_speed) { + ret = phy->ops->set_speed (phy, lane, speed); +if (ret <0 ) { +dev_err (&phy->dev,"phy set speed failed --> %d\n" , + ret); + goto out; + } + } + +out: +mutex_unlock (&phy->mutex); + +return ret; +} +EXPORT_SYMBOL_GPL (phy_set_speed); +/** * of_phy_get() - lookup and obtain a reference to a phy by phandle * @dev: device that requests this phy
include/linux/phy/phy.h +8 -0
@@ -27,6 +27,7 @@ struct phy;* @exit: operation to be performed while exiting * @power_on: powering on the phy * @power_off: powering off the phy +* @set_speed: set operation speed in hz * @owner: the module owner containing the ops */ struct phy_ops {
@@ -34,6 +35,7 @@ struct phy_ops {int (*exit)(struct phy *phy);int (*power_on)(struct phy *phy);int (*power_off)(struct phy *phy); +int (*set_speed)(struct phy *phy,int lane,u64 speed);struct module *owner; };
@@ -127,6 +129,7 @@ int phy_init(struct phy *phy);int phy_exit (struct phy *phy);int phy_power_on (struct phy *phy);int phy_power_off (struct phy *phy); +int phy_set_speed (struct phy *phy,int lane,u64 speed);struct phy *phy_get (struct device *dev,const char *string);struct phy *devm_phy_get (struct device *dev,const char *string);void phy_put (struct phy *phy);
@@ -199,6 +202,11 @@ static inline int phy_power_off(struct phy *phy)return -ENOSYS ; } +static inline int phy_set_speed (struct phy *phy,int lane,u64 speed) +{ +return -ENOSYS ; +} +static inline struct phy *phy_get (struct device *dev,const char *string) {return ERR_PTR (-ENOSYS );
--
1.5.5
PATCH v4 2/4 Documentation: Add APM X-Gene SoC 15Gbps Multi-purpose PHY driver binding documentation
--- .../devicetree/bindings/ata/apm-xgene-phy.txt | 89 ++++++++++++++++++++ 1 files changed, 89 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/ata/apm-xgene-phy.txt
Documentation/devicetree/bindings/ata/apm-xgene-phy.txt new file +89 -0
@@ -0,0 +1,89 @@ +* APM X-Gene 15Gbps Multi-purpose PHY nodes + +PHY nodes are defined to describe on-chip 15Gbps Multi-purpose PHY. Each +PHY (pair of lanes) has its own node. + +Required properties: +- compatible : Shall be "apm,xgene-phy" or + "apm,xgene-phy-ext". The "apm,xgene-phy" describes + an PHY with internal reference PLL located within + the IP. The "apm,xgene-phy-ext" describes an PHY + where the internal reference PLL located outside of + the IP. +- reg : First PHY memory resource is the SDS PHY access + resource. + Second PHY memory resoruce is the clock and reset + resources. + Third PHY memory resource is the SDS PHY access + resource outside of the IP if it is type + "apm,xgene-phy-ext". +- #phy-cells : Shall be 1 as it expects one argument for setting + the mode of the PHY. Possible values are 0 (SATA), + 1 (SGMII), 2 (PCIe), or 3 (USB). + +Optional properties: +- status : Shall be "ok" if enabled or "disabled" if disabled. + Default is "ok". +- apm,tx-eye-tuning : Manual control to fine tune the capture of the serial + bit lines from the automatic calibrated position. + Two set of 3-tuple setting for Gen1, Gen2, and Gen3. + Range from 0 to 0x7f in unit of one bit period. + Default is 0xa. +- apm,tx-eye-direction : Eye tuning manual control direction. 0 means sample + data earlier than the nominal sampling point. 1 means + sample data later than the nominal sampling point. + Two set of 3-tuple setting for Gen1, Gen2, and Gen3. + Default is 0x0. +- apm,tx-boost-gain : Frequency boost AC (LSB 3-bit) and DC (2-bit) + gain control. Two set of 3-tuple setting for Gen1, + Gen2, and Gen3. Range is between 0 to 0x1f in unit + of dB. Default is 0x3. +- apm,tx-amplitude : Amplitude control. Two set of 3-tuple setting for + Gen1, Gen2, and Gen3. Range is between 0 to 0xf in + unit of 13.3mV. Default is 0xf. +- apm,tx-pre-cursor1 : 1st pre-cursor emphasis taps control. Two set of + 3-tuple setting for Gen1, Gen2, and Gen3. Range is + between 0 to 0xf in unit of 18.2mV. Default is 0x0. +- apm,tx-pre-cursor2 : 2st pre-cursor emphasis taps control. Two set of + 3-tuple setting for Gen1, Gen2, and Gen3. Range is + between 0 to 0x7 in unit of 18.2mV. Default is 0x0. +- apm,tx-post-cursor : Post-cursor emphasis taps control. Two set of + 3-tuple setting for Gen1, Gen2, and Gen3. Range is + between 0 to 0x1f in unit of 18.2mV. Default is 0xf. +- apm,tx-speed : Tx operating speed. One set of 3-tuple for + Gen1 (0x1), Gen2 (0x3), and Gen3 (0x7). Default is + 0x7. + +NOTE: PHY override parameters are board specific setting. + +Example: + phy1: phy at 1f21a000 { + compatible = "apm,xgene-phy"; + reg = <0x0 0x1f21a000 0x0 0x100>, + <0x0 0x1f21c000 0x0 0x100>; + #phy-cells = <1>; + status = "disabled"; + apm,tx-boost-gain = <0x2 0x2 0x2 0x2 0x2 0x2>; + apm,tx-eye-tuning = <0xa 0xa 0xa 0xa 0xa 0xa>; + }; + + phy2: phy at 1f22a000 { + compatible = "apm,xgene-phy"; + reg = <0x0 0x1f22a000 0x0 0x100>, + <0x0 0x1f22c000 0x0 0x100>; + #phy-cells = <1>; + status = "ok"; + apm,tx-boost-gain = <0x2 0x2 0x2 0x2 0x2 0x2>; + apm,tx-eye-tuning = <0xa 0xa 0xa 0x5 0x5 0x5>; + }; + + phy3: phy at 1f23a000 { + compatible = "apm,xgene-phy-ext"; + reg = <0x0 0x1f23a000 0x0 0x100>, + <0x0 0x1f23c000 0x0 0x100>, + <0x0 0x1f2d0000 0x0 0x100>; + #phy-cells = <1>; + status = "ok"; + apm,tx-boost-gain = <0x3 0x3 0x3 0x3 0x3 0x3>; + apm,tx-eye-tuning = <0xa 0xa 0xa 0xc 0xc 0xc>; + };
--
1.5.5
PATCH v4 3/4 PHY: add APM X-Gene SoC 15Gbps Multi-purpose PHY driver
This patch adds support for APM X-Gene SoC 15Gbps Multi-purpose PHY. This is the physical layer interface for the corresponding host controller. This driver uses the new PHY generic framework posted by Kishon Vijay Abrahm. Currently, only external clock and SATA mode are supported.
--- drivers/phy/Kconfig | 7 + drivers/phy/Makefile | 2 + drivers/phy/phy-xgene.c | 1854 +++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 1863 insertions(+), 0 deletions(-) create mode 100644 drivers/phy/phy-xgene.c
drivers/phy/Kconfig +7 -0
@@ -51,4 +51,11 @@ config PHY_EXYNOS_DP_VIDEO help Support for Display Port PHY found on Samsung EXYNOS SoCs. +config PHY_XGENE + tristate "APM X-Gene 15Gbps PHY support" + depends on ARM64 || COMPILE_TEST + select GENERIC_PHY + help + This option enables support for APM X-Gene SoC multi-purpose PHY. + endmenu
drivers/phy/Makefile +2 -0
@@ -7,3 +7,5 @@ obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o +obj-$(CONFIG_PHY_XGENE) += phy-xgene.o +
drivers/phy/phy-xgene.c new file +1854 -0
1,854 lines not on this page · raw message
--
1.5.5
PATCH v4 4/4 arm64: Add APM X-Gene SoC 15Gbps Multi-purpose PHY DTS entries
This patch adds the DTS entries for the APM X-Gene SoC 15Gbps Multi-purpose PHY driver. The PHY for SATA controller 0 and 1 are enabled by default.
--- arch/arm64/boot/dts/apm-storm.dtsi | 31 +++++++++++++++++++++++++++++++ 1 files changed, 31 insertions(+), 0 deletions(-)
arch/arm64/boot/dts/apm-storm.dtsi +31 -0
@@ -193,5 +193,36 @@ reg = <0x0 0x17000014 0x0 0x100>; mask = <0x1>; }; + + phy1: phy at 1f21a000 { + compatible = "apm,xgene-phy"; + reg = <0x0 0x1f21a000 0x0 0x100>, + <0x0 0x1f21c000 0x0 0x100>; + #phy-cells = <1>; + status = "disabled"; + apm,tx-boost-gain = <0x2 0x3 0x3 0x2 0x3 0x3>; + apm,tx-eye-tuning = <0x2 0xa 0xa 0x2 0xa 0xa>; + }; + + phy2: phy at 1f22a000 { + compatible = "apm,xgene-phy"; + reg = <0x0 0x1f22a000 0x0 0x100>, + <0x0 0x1f22c000 0x0 0x100>; + #phy-cells = <1>; + status = "ok"; + apm,tx-boost-gain = <0x2 0x3 0x2 0x2 0x3 0x2>; + apm,tx-eye-tuning = <0x1 0xa 0xa 0x2 0xa 0x5>; + }; + + phy3: phy at 1f23a000 { + compatible = "apm,xgene-phy-ext"; + reg = <0x0 0x1f23a000 0x0 0x100>, + <0x0 0x1f23c000 0x0 0x100>, + <0x0 0x1f2d0000 0x0 0x100>; + #phy-cells = <1>; + status = "ok"; + apm,tx-boost-gain = <0x2 0x3 0x3 0x2 0x3 0x3>; + apm,tx-eye-tuning = <0x2 0xa 0xa 0x2 0xa 0xc>; + }; }; };
--
1.5.5
PATCH v4 2/4 Documentation: Add APM X-Gene SoC 15Gbps Multi-purpose PHY driver binding documentation
In reply to Loc HoDocumentation/devicetree/bindings/ata/apm-xgene-phy.txt line 19
Quoted 7 lines · Loc Ho
+- reg : First PHY memory resource is the SDS PHY access
Documentation/devicetree/bindings/ata/apm-xgene-phy.txt new file +6
-0+ resource. + Second PHY memory resoruce is the clock and reset + resources. + Third PHY memory resource is the SDS PHY access + resource outside of the IP if it is type + "apm,xgene-phy-ext".
Why do the "clock and reset" resources not use a clock driver and a reset driver?
I would expect these to get replaced with
clocks : Reference to external clock input
resets : Reference to reset controller input
Documentation/devicetree/bindings/ata/apm-xgene-phy.txt line 31
Quoted 8 lines
Documentation/devicetree/bindings/ata/apm-xgene-phy.txt new file +8
-0+Optional properties: +- status : Shall be "ok" if enabled or "disabled" if disabled. + Default is "ok". +- apm,tx-eye-tuning : Manual control to fine tune the capture of the serial + bit lines from the automatic calibrated position. + Two set of 3-tuple setting for Gen1, Gen2, and Gen3. + Range from 0 to 0x7f in unit of one bit period. + Default is 0xa.
What does gen1, gen2 and gen3 refer to? Is this PCIe, SATA or serdes generations or all of them?
Why are there two sets?
Will this have to change if you add PCIe support?
I would suggest using decimal notation here instead of hexadecimal since you are dealing with numbers couting things. Same for the others.
Quoted 4 lines
+- apm,tx-eye-direction : Eye tuning manual control direction. 0 means sample
(quoted diff) +3
-0+ data earlier than the nominal sampling point. 1 means + sample data later than the nominal sampling point. + Two set of 3-tuple setting for Gen1, Gen2, and Gen3.
Review
Quoted 10 lines
(quoted diff) +10
-0+ Default is 0x0. + +- apm,tx-boost-gain : Frequency boost AC (LSB 3-bit) and DC (2-bit) + gain control. Two set of 3-tuple setting for Gen1, + Gen2, and Gen3. Range is between 0 to 0x1f in unit + of dB. Default is 0x3. + +- apm,tx-amplitude : Amplitude control. Two set of 3-tuple setting for + Gen1, Gen2, and Gen3. Range is between 0 to 0xf in + unit of 13.3mV. Default is 0xf.
Units of 13.3mV don't seem to be useful as a generic measurement. I'd recommend using milivolts or microvolts.
Documentation/devicetree/bindings/ata/apm-xgene-phy.txt line 52
Quoted 9 lines
+- apm,tx-pre-cursor1 : 1st pre-cursor emphasis taps control. Two set of
Documentation/devicetree/bindings/ata/apm-xgene-phy.txt new file +8
-0+ 3-tuple setting for Gen1, Gen2, and Gen3. Range is + between 0 to 0xf in unit of 18.2mV. Default is 0x0. +- apm,tx-pre-cursor2 : 2st pre-cursor emphasis taps control. Two set of + 3-tuple setting for Gen1, Gen2, and Gen3. Range is + between 0 to 0x7 in unit of 18.2mV. Default is 0x0. +- apm,tx-post-cursor : Post-cursor emphasis taps control. Two set of + 3-tuple setting for Gen1, Gen2, and Gen3. Range is + between 0 to 0x1f in unit of 18.2mV. Default is 0xf.
Same here.
Documentation/devicetree/bindings/ata/apm-xgene-phy.txt line 55
Quoted 3 lines
+- apm,tx-speed : Tx operating speed. One set of 3-tuple for
Documentation/devicetree/bindings/ata/apm-xgene-phy.txt new file +2
-0+ Gen1 (0x1), Gen2 (0x3), and Gen3 (0x7). Default is + 0x7.
I'm completely confused by this description. Can you rephrase this? It sounds like the only possible values are <1 3 7> for this property.
Arnd
PATCH v4 2/4 Documentation: Add APM X-Gene SoC 15Gbps Multi-purpose PHY driver binding documentation
Quoted 66 lines · Arnd Bergmann
Documentation/devicetree/bindings/ata/apm-xgene-phy.txt line 19
Quoted 7 lines · Loc Ho
+- reg : First PHY memory resource is the SDS PHY access
Documentation/devicetree/bindings/ata/apm-xgene-phy.txt new file +6
-0+ resource. + Second PHY memory resoruce is the clock and reset + resources. + Third PHY memory resource is the SDS PHY access + resource outside of the IP if it is type + "apm,xgene-phy-ext".Why do the "clock and reset" resources not use a clock driver and a reset driver?
I would expect these to get replaced with
clocks : Reference to external clock input
resets : Reference to reset controller inputDocumentation/devicetree/bindings/ata/apm-xgene-phy.txt line 31
Quoted 8 lines
Documentation/devicetree/bindings/ata/apm-xgene-phy.txt new file +8
-0+Optional properties: +- status : Shall be "ok" if enabled or "disabled" if disabled. + Default is "ok". +- apm,tx-eye-tuning : Manual control to fine tune the capture of the serial + bit lines from the automatic calibrated position. + Two set of 3-tuple setting for Gen1, Gen2, and Gen3. + Range from 0 to 0x7f in unit of one bit period. + Default is 0xa.What does gen1, gen2 and gen3 refer to? Is this PCIe, SATA or serdes generations or all of them?
Why are there two sets?
Will this have to change if you add PCIe support?
I would suggest using decimal notation here instead of hexadecimal since you are dealing with numbers couting things. Same for the others.
Quoted 4 lines
+- apm,tx-eye-direction : Eye tuning manual control direction. 0 means sample
(quoted diff) +3
-0+ data earlier than the nominal sampling point. 1 means + sample data later than the nominal sampling point. + Two set of 3-tuple setting for Gen1, Gen2, and Gen3.Review
Quoted 10 lines
(quoted diff) +10
-0+ Default is 0x0. + +- apm,tx-boost-gain : Frequency boost AC (LSB 3-bit) and DC (2-bit) + gain control. Two set of 3-tuple setting for Gen1, + Gen2, and Gen3. Range is between 0 to 0x1f in unit + of dB. Default is 0x3. + +- apm,tx-amplitude : Amplitude control. Two set of 3-tuple setting for + Gen1, Gen2, and Gen3. Range is between 0 to 0xf in + unit of 13.3mV. Default is 0xf.Units of 13.3mV don't seem to be useful as a generic measurement. I'd recommend using milivolts or microvolts.
Documentation/devicetree/bindings/ata/apm-xgene-phy.txt line 52
Quoted 9 lines
+- apm,tx-pre-cursor1 : 1st pre-cursor emphasis taps control. Two set of
Documentation/devicetree/bindings/ata/apm-xgene-phy.txt new file +8
-0+ 3-tuple setting for Gen1, Gen2, and Gen3. Range is + between 0 to 0xf in unit of 18.2mV. Default is 0x0. +- apm,tx-pre-cursor2 : 2st pre-cursor emphasis taps control. Two set of + 3-tuple setting for Gen1, Gen2, and Gen3. Range is + between 0 to 0x7 in unit of 18.2mV. Default is 0x0. +- apm,tx-post-cursor : Post-cursor emphasis taps control. Two set of + 3-tuple setting for Gen1, Gen2, and Gen3. Range is + between 0 to 0x1f in unit of 18.2mV. Default is 0xf.Same here.
Quoted 6 lines
Documentation/devicetree/bindings/ata/apm-xgene-phy.txt line 55
Quoted 3 lines
+- apm,tx-speed : Tx operating speed. One set of 3-tuple for
Documentation/devicetree/bindings/ata/apm-xgene-phy.txt new file +2
-0+ Gen1 (0x1), Gen2 (0x3), and Gen3 (0x7). Default is + 0x7.I'm completely confused by this description. Can you rephrase this? It sounds like the only possible values are <1 3 7> for this property.
Most likely Gen1, Gen2 and Gen3 are SATA-speak corresponding to SAS's G1, G2 and G3:
G1 Gen1 1.5 Gbps G2 Gen2 3 Gbps G3 Gen3 6 Gbps G4 - 12 Gbps G5 - 24 Gbps
And the "7" corresponding to Gen3 is indicating backward compatibility with Gen2 and Gen1. The SAS-3 draft only requires backward compatibility two generations. Thus you can buy a SAS 12 Gbps HBA today that will not support the original SATA 1.5 Gbps class of disks. The corresponding value would be 0xe (rather than 0xf) using the tx-speed convention above.
My explanation is a bit long winded to put in a device-tree bindings file. "RTFM: SATA drafts." should suffice.
BTW Compared to some device-tree binding explanations I have had to wade through, the above looks pretty good.
Doug Gilbert
James Bottomley
maintainerPATCH v4 2/4 Documentation: Add APM X-Gene SoC 15Gbps Multi-purpose PHY driver binding documentation
Quoted 74 lines · Douglas Gilbert
Quoted 66 lines · Arnd Bergmann
Documentation/devicetree/bindings/ata/apm-xgene-phy.txt line 19
Quoted 7 lines · Loc Ho
+- reg : First PHY memory resource is the SDS PHY access
Documentation/devicetree/bindings/ata/apm-xgene-phy.txt new file +6
-0+ resource. + Second PHY memory resoruce is the clock and reset + resources. + Third PHY memory resource is the SDS PHY access + resource outside of the IP if it is type + "apm,xgene-phy-ext".Why do the "clock and reset" resources not use a clock driver and a reset driver?
I would expect these to get replaced with
clocks : Reference to external clock input
resets : Reference to reset controller inputDocumentation/devicetree/bindings/ata/apm-xgene-phy.txt line 31
Quoted 8 lines
Documentation/devicetree/bindings/ata/apm-xgene-phy.txt new file +8
-0+Optional properties: +- status : Shall be "ok" if enabled or "disabled" if disabled. + Default is "ok". +- apm,tx-eye-tuning : Manual control to fine tune the capture of the serial + bit lines from the automatic calibrated position. + Two set of 3-tuple setting for Gen1, Gen2, and Gen3. + Range from 0 to 0x7f in unit of one bit period. + Default is 0xa.What does gen1, gen2 and gen3 refer to? Is this PCIe, SATA or serdes generations or all of them?
Why are there two sets?
Will this have to change if you add PCIe support?
I would suggest using decimal notation here instead of hexadecimal since you are dealing with numbers couting things. Same for the others.
Quoted 4 lines
+- apm,tx-eye-direction : Eye tuning manual control direction. 0 means sample
(quoted diff) +3
-0+ data earlier than the nominal sampling point. 1 means + sample data later than the nominal sampling point. + Two set of 3-tuple setting for Gen1, Gen2, and Gen3.Review
Quoted 10 lines
(quoted diff) +10
-0+ Default is 0x0. + +- apm,tx-boost-gain : Frequency boost AC (LSB 3-bit) and DC (2-bit) + gain control. Two set of 3-tuple setting for Gen1, + Gen2, and Gen3. Range is between 0 to 0x1f in unit + of dB. Default is 0x3. + +- apm,tx-amplitude : Amplitude control. Two set of 3-tuple setting for + Gen1, Gen2, and Gen3. Range is between 0 to 0xf in + unit of 13.3mV. Default is 0xf.Units of 13.3mV don't seem to be useful as a generic measurement. I'd recommend using milivolts or microvolts.
Documentation/devicetree/bindings/ata/apm-xgene-phy.txt line 52
Quoted 9 lines
+- apm,tx-pre-cursor1 : 1st pre-cursor emphasis taps control. Two set of
Documentation/devicetree/bindings/ata/apm-xgene-phy.txt new file +8
-0+ 3-tuple setting for Gen1, Gen2, and Gen3. Range is + between 0 to 0xf in unit of 18.2mV. Default is 0x0. +- apm,tx-pre-cursor2 : 2st pre-cursor emphasis taps control. Two set of + 3-tuple setting for Gen1, Gen2, and Gen3. Range is + between 0 to 0x7 in unit of 18.2mV. Default is 0x0. +- apm,tx-post-cursor : Post-cursor emphasis taps control. Two set of + 3-tuple setting for Gen1, Gen2, and Gen3. Range is + between 0 to 0x1f in unit of 18.2mV. Default is 0xf.Same here.
Quoted 6 lines
Documentation/devicetree/bindings/ata/apm-xgene-phy.txt line 55
Quoted 3 lines
+- apm,tx-speed : Tx operating speed. One set of 3-tuple for
Documentation/devicetree/bindings/ata/apm-xgene-phy.txt new file +2
-0+ Gen1 (0x1), Gen2 (0x3), and Gen3 (0x7). Default is + 0x7.I'm completely confused by this description. Can you rephrase this? It sounds like the only possible values are <1 3 7> for this property.
Quoted 8 lines
Most likely Gen1, Gen2 and Gen3 are SATA-speak corresponding to SAS's G1, G2 and G3:
G1 Gen1 1.5 Gbps G2 Gen2 3 Gbps G3 Gen3 6 Gbps G4 - 12 Gbps G5 - 24 Gbps
Electrically, SAS phys and SATA phys are identical. We already have a SAS phy abstraction in libsas ... when looking at a separable phy implementation, shouldn't we be doing something that works for both instead of just SATA?
James
PATCH v4 2/4 Documentation: Add APM X-Gene SoC 15Gbps Multi-purpose PHY driver binding documentation
Quoted 12 lines · James Bottomley
Quoted 11 lines
Quoted 2 lines
I'm completely confused by this description. Can you rephrase this? It sounds like the only possible values are <1 3 7> for this property.
Most likely Gen1, Gen2 and Gen3 are SATA-speak corresponding to SAS's G1, G2 and G3:
G1 Gen1 1.5 Gbps G2 Gen2 3 Gbps G3 Gen3 6 Gbps G4 - 12 Gbps G5 - 24 Gbps
Quoted 4 lines
Electrically, SAS phys and SATA phys are identical. We already have a SAS phy abstraction in libsas ... when looking at a separable phy implementation, shouldn't we be doing something that works for both instead of just SATA?
This PHY is also used for ethernet and for PCIe, even though the driver handles only the SATA case so far. Can the SAS abstraction deal with this?
How do you describe a SAS PHY in DT?
Arnd
PATCH v4 2/4 Documentation: Add APM X-Gene SoC 15Gbps Multi-purpose PHY driver binding documentation
In reply to Douglas GilbertQuoted 24 lines · Douglas Gilbert
Quoted 7 lines
Documentation/devicetree/bindings/ata/apm-xgene-phy.txt line 55
Quoted 4 lines
+- apm,tx-speed : Tx operating speed. One set of 3-tuple for
Documentation/devicetree/bindings/ata/apm-xgene-phy.txt new file +2
-0+ Gen1 (0x1), Gen2 (0x3), and Gen3 (0x7). Default is + 0x7.I'm completely confused by this description. Can you rephrase this? It sounds like the only possible values are <1 3 7> for this property.
Most likely Gen1, Gen2 and Gen3 are SATA-speak corresponding to SAS's G1, G2 and G3:
G1 Gen1 1.5 Gbps G2 Gen2 3 Gbps G3 Gen3 6 Gbps G4 - 12 Gbps G5 - 24 GbpsAnd the "7" corresponding to Gen3 is indicating backward compatibility with Gen2 and Gen1. The SAS-3 draft only requires backward compatibility two generations. Thus you can buy a SAS 12 Gbps HBA today that will not support the original SATA 1.5 Gbps class of disks. The corresponding value would be
0xe(rather than0xf) using the tx-speed convention above.
Quoted 7 lines
My explanation is a bit long winded to put in a device-tree bindings file. "RTFM: SATA drafts." should suffice.
BTW Compared to some device-tree binding explanations I have had to wade through, the above looks pretty good.
Well, the problem is that this is not a SATA device but a PHY device that happens to support SATA among its protocols (at least PCIe as well, possibly more but I don't have the specs). The binding document has to cover all the possibilities or allow extensions for the other protocols to be implemented later. Having the driver support SATA only initially is fine, but we shouldn't plan for breaking compatibility with an established binding just a short time later.
Arnd
PATCH v4 2/4 Documentation: Add APM X-Gene SoC 15Gbps Multi-purpose PHY driver binding documentation
Hi,
Quoted 33 lines · Arnd Bergmann
Quoted 24 lines · Douglas Gilbert
Quoted 7 lines
Documentation/devicetree/bindings/ata/apm-xgene-phy.txt line 55
Quoted 4 lines
+- apm,tx-speed : Tx operating speed. One set of 3-tuple for
Documentation/devicetree/bindings/ata/apm-xgene-phy.txt new file +2
-0+ Gen1 (0x1), Gen2 (0x3), and Gen3 (0x7). Default is + 0x7.I'm completely confused by this description. Can you rephrase this? It sounds like the only possible values are <1 3 7> for this property.
Most likely Gen1, Gen2 and Gen3 are SATA-speak corresponding to SAS's G1, G2 and G3:
G1 Gen1 1.5 Gbps G2 Gen2 3 Gbps G3 Gen3 6 Gbps G4 - 12 Gbps G5 - 24 GbpsAnd the "7" corresponding to Gen3 is indicating backward compatibility with Gen2 and Gen1. The SAS-3 draft only requires backward compatibility two generations. Thus you can buy a SAS 12 Gbps HBA today that will not support the original SATA 1.5 Gbps class of disks. The corresponding value would be
0xe(rather than0xf) using the tx-speed convention above.Quoted 7 lines
My explanation is a bit long winded to put in a device-tree bindings file. "RTFM: SATA drafts." should suffice.
BTW Compared to some device-tree binding explanations I have had to wade through, the above looks pretty good.
Quoted 9 lines
Well, the problem is that this is not a SATA device but a PHY device that happens to support SATA among its protocols (at least PCIe as well, possibly more but I don't have the specs). The binding document has to cover all the possibilities or allow extensions for the other protocols to be implemented later. Having the driver support SATA only initially is fine, but we shouldn't plan for breaking compatibility with an established binding just a short time later.
[Loc Ho]
I will document them as XXGbps and drop the term GenX. As of right now, we only have SATA and I will document on 1.5Gbps, 3.0Gbps, and 6Gbps. Also, keep in mind that these override are used for SATA. PCIe doesn't need these custom override setting per port at this time. A single value so far work just fine for PCIe, SGMII, and XFI.
Any other comments...
-Loc
PATCH v4 2/4 Documentation: Add APM X-Gene SoC 15Gbps Multi-purpose PHY driver binding documentation
In reply to Arnd BergmannHi,
Quoted 9 lines · Loc Ho
Documentation/devicetree/bindings/ata/apm-xgene-phy.txt line 19
Quoted 7 lines
+- reg : First PHY memory resource is the SDS PHY access
Documentation/devicetree/bindings/ata/apm-xgene-phy.txt new file +6
-0+ resource. + Second PHY memory resoruce is the clock and reset + resources. + Third PHY memory resource is the SDS PHY access + resource outside of the IP if it is type + "apm,xgene-phy-ext".
Quoted 7 lines
Why do the "clock and reset" resources not use a clock driver and a reset driver?
I would expect these to get replaced with
clocks : Reference to external clock input
resets : Reference to reset controller input
[Loc Ho]
The clock register has bit for the SDS interface, each sata ports, CSR, AXI interface, and the PM (power management) interface. The clock and CSR for all these are enabled by the host controller driver. Unfortunately, during calibration the SATA ports clocks must not be enable. This sequence is required by the hardware itself. Unless I separate out the two, this requirement is handled by the PHY. If you believe this is needed, I can have two separate clocks but it is over kill. You can look at function xgene_phy_sata_setup_preclk and xgene_phy_sata_setup_postclk.
Quoted 10 lines
Documentation/devicetree/bindings/ata/apm-xgene-phy.txt line 31
Quoted 9 lines
Documentation/devicetree/bindings/ata/apm-xgene-phy.txt new file +8
-0+Optional properties: +- status : Shall be "ok" if enabled or "disabled" if disabled. + Default is "ok". +- apm,tx-eye-tuning : Manual control to fine tune the capture of the serial + bit lines from the automatic calibrated position. + Two set of 3-tuple setting for Gen1, Gen2, and Gen3. + Range from 0 to 0x7f in unit of one bit period. + Default is 0xa.
Quoted 2 lines
What does gen1, gen2 and gen3 refer to? Is this PCIe, SATA or serdes generations or all of them?
[Loc Ho]
Douglas already commented on this. Gen1 in SATA term is 1.5Gbps, Gen2 is 3.0Gbps, and Gen3 is 6Gbps.
Quoted 2 lines
Why are there two sets?
[Loc Ho]
Each controller has two SATA ports - one set for each port.
Quoted 2 lines
Will this have to change if you add PCIe support?
[Loc Ho]
So far, we don't see a need to use override setting for PCIe
Quoted 3 lines
I would suggest using decimal notation here instead of hexadecimal since you are dealing with numbers couting things. Same for the others.
[Loc Ho]
Okay... for future version.
Quoted 10 lines
Quoted 10 lines
+- apm,tx-eye-direction : Eye tuning manual control direction. 0 means sample
Documentation/devicetree/bindings/ata/apm-xgene-phy.txt new file +8
-0+ data earlier than the nominal sampling point. 1 means + sample data later than the nominal sampling point. + Two set of 3-tuple setting for Gen1, Gen2, and Gen3. + Default is 0x0. + +- apm,tx-boost-gain : Frequency boost AC (LSB 3-bit) and DC (2-bit) + gain control. Two set of 3-tuple setting for Gen1, + Gen2, and Gen3. Range is between 0 to 0x1f in unit
Quoted 8 lines
Documentation/devicetree/bindings/ata/apm-xgene-phy.txt line 43
Quoted 5 lines
Documentation/devicetree/bindings/ata/apm-xgene-phy.txt new file +5
-0+ of dB. Default is 0x3. + +- apm,tx-amplitude : Amplitude control. Two set of 3-tuple setting for + Gen1, Gen2, and Gen3. Range is between 0 to 0xf in + unit of 13.3mV. Default is 0xf.Units of 13.3mV don't seem to be useful as a generic measurement. I'd recommend using milivolts or microvolts.
[Loc Ho]
Each unit is 13.3mV. If I use millivolt, then someone can set fraction which will get round up or down. If you still strongly suggest this is required, then fine.
Quoted 11 lines
Documentation/devicetree/bindings/ata/apm-xgene-phy.txt line 52
Quoted 10 lines
+- apm,tx-pre-cursor1 : 1st pre-cursor emphasis taps control. Two set of
Documentation/devicetree/bindings/ata/apm-xgene-phy.txt new file +8
-0+ 3-tuple setting for Gen1, Gen2, and Gen3. Range is + between 0 to 0xf in unit of 18.2mV. Default is 0x0. +- apm,tx-pre-cursor2 : 2st pre-cursor emphasis taps control. Two set of + 3-tuple setting for Gen1, Gen2, and Gen3. Range is + between 0 to 0x7 in unit of 18.2mV. Default is 0x0. +- apm,tx-post-cursor : Post-cursor emphasis taps control. Two set of + 3-tuple setting for Gen1, Gen2, and Gen3. Range is + between 0 to 0x1f in unit of 18.2mV. Default is 0xf.
Quoted 8 lines
Same here.
Documentation/devicetree/bindings/ata/apm-xgene-phy.txt line 55
Quoted 3 lines
+- apm,tx-speed : Tx operating speed. One set of 3-tuple for
Documentation/devicetree/bindings/ata/apm-xgene-phy.txt new file +2
-0+ Gen1 (0x1), Gen2 (0x3), and Gen3 (0x7). Default is + 0x7.I'm completely confused by this description. Can you rephrase this? It sounds like the only possible values are <1 3 7> for this property.
[Loc Ho]
Douglas already comment on this. If you believe this needs to be rephrased, then let me know.
-Loc
PATCH v4 2/4 Documentation: Add APM X-Gene SoC 15Gbps Multi-purpose PHY driver binding documentation
Quoted 18 lines · Loc Ho
Hi,
Quoted 9 lines · Loc Ho
Documentation/devicetree/bindings/ata/apm-xgene-phy.txt line 19
Quoted 7 lines
+- reg : First PHY memory resource is the SDS PHY access
Documentation/devicetree/bindings/ata/apm-xgene-phy.txt new file +6
-0+ resource. + Second PHY memory resoruce is the clock and reset + resources. + Third PHY memory resource is the SDS PHY access + resource outside of the IP if it is type + "apm,xgene-phy-ext".Quoted 7 lines
Why do the "clock and reset" resources not use a clock driver and a reset driver?
I would expect these to get replaced with
clocks : Reference to external clock input
resets : Reference to reset controller input
Quoted 10 lines
[Loc Ho]
The clock register has bit for the SDS interface, each sata ports, CSR, AXI interface, and the PM (power management) interface. The clock and CSR for all these are enabled by the host controller driver. Unfortunately, during calibration the SATA ports clocks must not be enable. This sequence is required by the hardware itself. Unless I separate out the two, this requirement is handled by the PHY. If you believe this is needed, I can have two separate clocks but it is over kill. You can look at functionxgene_phy_sata_setup_preclkandxgene_phy_sata_setup_postclk.
I'm not looking at this from the driver side but rather from the way the hardware is built. My understanding is that you have clock and reset registers in a separate register file that also handles clocks and reset lines for other devices with the same layout. If this is true, you should definitely write a clock driver and a reset driver to support the respective register layouts, and use the clock and reset APIs in the kernel to call them, rather than poking the raw registers from an unrelated driver.
Quoted 11 lines
Quoted 11 lines
Documentation/devicetree/bindings/ata/apm-xgene-phy.txt line 31
Quoted 8 lines
Documentation/devicetree/bindings/ata/apm-xgene-phy.txt new file +8
-0+Optional properties: +- status : Shall be "ok" if enabled or "disabled" if disabled. + Default is "ok". +- apm,tx-eye-tuning : Manual control to fine tune the capture of the serial + bit lines from the automatic calibrated position. + Two set of 3-tuple setting for Gen1, Gen2, and Gen3. + Range from 0 to 0x7f in unit of one bit period. + Default is 0xa.What does gen1, gen2 and gen3 refer to? Is this PCIe, SATA or serdes generations or all of them?
Quoted 8 lines
[Loc Ho]
Douglas already commented on this. Gen1 in SATA term is 1.5Gbps, Gen2 is 3.0Gbps, and Gen3 is 6Gbps.Quoted 2 lines
Why are there two sets?
[Loc Ho]
Each controller has two SATA ports - one set for each port.
Ok.
Quoted 3 lines
Quoted 1 line
Will this have to change if you add PCIe support?
[Loc Ho]
So far, we don't see a need to use override setting for PCIe
The problem is that with the encoding you have chosen, it becomes a lot harder to add that if it turns out to be needed later.
Quoted 23 lines
Quoted 2 lines
I would suggest using decimal notation here instead of hexadecimal since you are dealing with numbers couting things. Same for the others.
[Loc Ho]
Okay... for future version.Quoted 10 lines
Quoted 10 lines
+- apm,tx-eye-direction : Eye tuning manual control direction. 0 means sample
Documentation/devicetree/bindings/ata/apm-xgene-phy.txt new file +8
-0+ data earlier than the nominal sampling point. 1 means + sample data later than the nominal sampling point. + Two set of 3-tuple setting for Gen1, Gen2, and Gen3. + Default is 0x0. + +- apm,tx-boost-gain : Frequency boost AC (LSB 3-bit) and DC (2-bit) + gain control. Two set of 3-tuple setting for Gen1, + Gen2, and Gen3. Range is between 0 to 0x1f in unitQuoted 8 lines
Documentation/devicetree/bindings/ata/apm-xgene-phy.txt line 43
Quoted 5 lines
Documentation/devicetree/bindings/ata/apm-xgene-phy.txt new file +5
-0+ of dB. Default is 0x3. + +- apm,tx-amplitude : Amplitude control. Two set of 3-tuple setting for + Gen1, Gen2, and Gen3. Range is between 0 to 0xf in + unit of 13.3mV. Default is 0xf.Units of 13.3mV don't seem to be useful as a generic measurement. I'd recommend using milivolts or microvolts.
Quoted 4 lines
[Loc Ho]
Each unit is 13.3mV. If I use millivolt, then someone can set fraction which will get round up or down. If you still strongly suggest this is required, then fine.
The amplitude sounds like something that a lot of PHY drivers would need to set, and we really want everybody to use the same property definitions for describing the same things.
Quoted 16 lines
Quoted 16 lines
Documentation/devicetree/bindings/ata/apm-xgene-phy.txt line 52
Quoted 9 lines
+- apm,tx-pre-cursor1 : 1st pre-cursor emphasis taps control. Two set of
Documentation/devicetree/bindings/ata/apm-xgene-phy.txt new file +8
-0+ 3-tuple setting for Gen1, Gen2, and Gen3. Range is + between 0 to 0xf in unit of 18.2mV. Default is 0x0. +- apm,tx-pre-cursor2 : 2st pre-cursor emphasis taps control. Two set of + 3-tuple setting for Gen1, Gen2, and Gen3. Range is + between 0 to 0x7 in unit of 18.2mV. Default is 0x0. +- apm,tx-post-cursor : Post-cursor emphasis taps control. Two set of + 3-tuple setting for Gen1, Gen2, and Gen3. Range is + between 0 to 0x1f in unit of 18.2mV. Default is 0xf.Same here.
Quoted 3 lines
+- apm,tx-speed : Tx operating speed. One set of 3-tuple for
Documentation/devicetree/bindings/ata/apm-xgene-phy.txt new file +2
-0+ Gen1 (0x1), Gen2 (0x3), and Gen3 (0x7). Default is + 0x7.
Quoted 5 lines
Quoted 2 lines
I'm completely confused by this description. Can you rephrase this? It sounds like the only possible values are <1 3 7> for this property.
[Loc Ho]
Douglas already comment on this. If you believe this needs to be rephrased, then let me know.
I think it's still rather confusing to the casual reader. Let me try to rephrase what I understand and you can decide whether you want to use that text, or correct my mistakes.
apm,sata-speed : Tx operating speed for SATA mode. A 3-tuple for each
supported link speed on the host, with a bit mask of compatible device speeds, encoded as 0x0001 - SATA-I (1.5gbits/s) 0x0002 - SATA-II (3.0gbits/s) 0x0004 - SATA-6G (6.0gbits/s) Default is <0x1 0x3 0x7>. Arnd
PATCH v4 2/4 Documentation: Add APM X-Gene SoC 15Gbps Multi-purpose PHY driver binding documentation
HI,
Quoted 27 lines
Quoted 15 lines
Quoted 8 lines
Documentation/devicetree/bindings/ata/apm-xgene-phy.txt line 19
Quoted 7 lines
+- reg : First PHY memory resource is the SDS PHY access
Documentation/devicetree/bindings/ata/apm-xgene-phy.txt new file +6
-0+ resource. + Second PHY memory resoruce is the clock and reset + resources. + Third PHY memory resource is the SDS PHY access + resource outside of the IP if it is type + "apm,xgene-phy-ext".Quoted 7 lines
Why do the "clock and reset" resources not use a clock driver and a reset driver?
I would expect these to get replaced with
clocks : Reference to external clock input
resets : Reference to reset controller inputQuoted 10 lines
[Loc Ho]
The clock register has bit for the SDS interface, each sata ports, CSR, AXI interface, and the PM (power management) interface. The clock and CSR for all these are enabled by the host controller driver. Unfortunately, during calibration the SATA ports clocks must not be enable. This sequence is required by the hardware itself. Unless I separate out the two, this requirement is handled by the PHY. If you believe this is needed, I can have two separate clocks but it is over kill. You can look at functionxgene_phy_sata_setup_preclkandxgene_phy_sata_setup_postclk.
Quoted 8 lines
I'm not looking at this from the driver side but rather from the way the hardware is built. My understanding is that you have clock and reset registers in a separate register file that also handles clocks and reset lines for other devices with the same layout. If this is true, you should definitely write a clock driver and a reset driver to support the respective register layouts, and use the clock and reset APIs in the kernel to call them, rather than poking the raw registers from an unrelated driver.
The HW has one clock register and one CSR (configuration status register) for all SATA and PHY sub-HW block. Each bit corresponding to one sub-HW block. In a perfect HW, one would just enable the clock and take the CSR out of reset and then go on initialize the HW. But there is an requirement to have some sub-HW block remain in reset until it is completed. It sounds like to me that I will need to separate them out. I will separate the clock interface into two components - one for the host and one for the PHY.
Quoted 21 lines
Quoted 12 lines
Quoted 10 lines
Documentation/devicetree/bindings/ata/apm-xgene-phy.txt line 31
Quoted 9 lines
Documentation/devicetree/bindings/ata/apm-xgene-phy.txt new file +8
-0+Optional properties: +- status : Shall be "ok" if enabled or "disabled" if disabled. + Default is "ok". +- apm,tx-eye-tuning : Manual control to fine tune the capture of the serial + bit lines from the automatic calibrated position. + Two set of 3-tuple setting for Gen1, Gen2, and Gen3. + Range from 0 to 0x7f in unit of one bit period. + Default is 0xa.Quoted 2 lines
What does gen1, gen2 and gen3 refer to? Is this PCIe, SATA or serdes generations or all of them?
Quoted 8 lines
[Loc Ho]
Douglas already commented on this. Gen1 in SATA term is 1.5Gbps, Gen2 is 3.0Gbps, and Gen3 is 6Gbps.Quoted 2 lines
Why are there two sets?
[Loc Ho]
Each controller has two SATA ports - one set for each port.
Quoted 8 lines
Ok.
Quoted 3 lines
Quoted 1 line
Will this have to change if you add PCIe support?
[Loc Ho]
So far, we don't see a need to use override setting for PCIeThe problem is that with the encoding you have chosen, it becomes a lot harder to add that if it turns out to be needed later.
[Loc Ho]
PCIe also has Gen1, Gen2, and Gen3. USB has 1.1, 2.0, and 3.0. XSGMII is only 1Gbps. XFI is only 10Gbps. Let me put this in the text.
Quoted 24 lines
Quoted 24 lines
Quoted 3 lines
I would suggest using decimal notation here instead of hexadecimal since you are dealing with numbers couting things. Same for the others.
[Loc Ho]
Okay... for future version.Quoted 18 lines
Quoted 5 lines
+- apm,tx-eye-direction : Eye tuning manual control direction. 0 means sample
(quoted diff) +3
-0+ data earlier than the nominal sampling point. 1 means + sample data later than the nominal sampling point. + Two set of 3-tuple setting for Gen1, Gen2, and Gen3.Review
Quoted 10 lines
(quoted diff) +10
-0+ Default is 0x0. + +- apm,tx-boost-gain : Frequency boost AC (LSB 3-bit) and DC (2-bit) + gain control. Two set of 3-tuple setting for Gen1, + Gen2, and Gen3. Range is between 0 to 0x1f in unit + of dB. Default is 0x3. + +- apm,tx-amplitude : Amplitude control. Two set of 3-tuple setting for + Gen1, Gen2, and Gen3. Range is between 0 to 0xf in + unit of 13.3mV. Default is 0xf.Units of 13.3mV don't seem to be useful as a generic measurement. I'd recommend using milivolts or microvolts.
Quoted 8 lines
Quoted 4 lines
[Loc Ho]
Each unit is 13.3mV. If I use millivolt, then someone can set fraction which will get round up or down. If you still strongly suggest this is required, then fine.The amplitude sounds like something that a lot of PHY drivers would need to set, and we really want everybody to use the same property definitions for describing the same things.
[Loc Ho]
Okay... I understand and stay with millivolt and let the driver handle the conversion
Quoted 27 lines
Quoted 17 lines
Quoted 17 lines
Documentation/devicetree/bindings/ata/apm-xgene-phy.txt line 52
Quoted 10 lines
+- apm,tx-pre-cursor1 : 1st pre-cursor emphasis taps control. Two set of
Documentation/devicetree/bindings/ata/apm-xgene-phy.txt new file +8
-0+ 3-tuple setting for Gen1, Gen2, and Gen3. Range is + between 0 to 0xf in unit of 18.2mV. Default is 0x0. +- apm,tx-pre-cursor2 : 2st pre-cursor emphasis taps control. Two set of + 3-tuple setting for Gen1, Gen2, and Gen3. Range is + between 0 to 0x7 in unit of 18.2mV. Default is 0x0. +- apm,tx-post-cursor : Post-cursor emphasis taps control. Two set of + 3-tuple setting for Gen1, Gen2, and Gen3. Range is + between 0 to 0x1f in unit of 18.2mV. Default is 0xf.Same here.
Quoted 3 lines
+- apm,tx-speed : Tx operating speed. One set of 3-tuple for
Documentation/devicetree/bindings/ata/apm-xgene-phy.txt new file +2
-0+ Gen1 (0x1), Gen2 (0x3), and Gen3 (0x7). Default is + 0x7.Quoted 5 lines
Quoted 2 lines
I'm completely confused by this description. Can you rephrase this? It sounds like the only possible values are <1 3 7> for this property.
[Loc Ho]
Douglas already comment on this. If you believe this needs to be rephrased, then let me know.I think it's still rather confusing to the casual reader. Let me try to rephrase what I understand and you can decide whether you want to use that text, or correct my mistakes.
Quoted 8 lines
apm,sata-speed : Tx operating speed for SATA mode. A 3-tuple for each
supported link speed on the host, with a bit mask of compatible device speeds, encoded as 0x0001 - SATA-I (1.5gbits/s) 0x0002 - SATA-II (3.0gbits/s) 0x0004 - SATA-6G (6.0gbits/s) Default is <0x1 0x3 0x7>.
I got it. Why not stay with unit of Kbps and let the driver handle the conversion?
-Loc