PHY: Add APM X-Gene SoC 15Gbps Multi-purpose PHY support
Subsystems (4)
v6 cover PHY: Add APM X-Gene SoC 15Gbps Multi-purpose PHY support
This patch adds support for APM X-Gene SoC 15Gbps Multi-purpose PHY. This is the physical layer interface for the corresponding host controller. This driver uses the new PHY generic framework posted by Kishon Vijay Abrahm. In addition, the new PHY generic framework is patched to provide an function to set the speed of the PHY.
v6
* Move PHY document to Documentation/devicetree/binding/phy
* Remove _ADDR from all register defines
* Update clock-names property for sataphy1clk, sataphy2clk, and sataphy3clk
v5
* Update DTS binding documentation
* Remove direct clock access and use clock interface instead
* Change override parameters to decimal instead hex values
* Change apm,tx-amplitude, apm,tx-pre-cursor1, apm,tx-pre-cursor2, apm,tx-post-cursor to be unit of uV
v4
* Update documentation with 'apm,' instead 'apm-'
* Change DTS override parameter to have 'apm,'
* Add select GENERIC_PHY to Kconfig PHY_XGENE
* Make override parameters to be pair of three values instead one
* Some minor comment and indentation changes
* Remove error register addition offset
* Add ULL to constants
* Use module_init instead subsys_initcall
* Make DTS node based on first register address
* Update override setting values
v3
* Major re-write of the code based on various review comments
* Support external clock only at the moment
* Support SATA mode only at the moment
* No UEFI support at the moment
v2
* Remove port knowledge from functions
* Make all functions static
* Remove ID completely
* Make resource requirement based on compatible type
* Rename override PHY parameters with more descriptive name
* Add override PHY parameter for per controller, per port, and per speed
* Patch the generic PHY frame to expose set_speed operation
v1
* Initial version
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Loc Ho (4):
PHY: Add function set_speed to generic PHY framework
Documentation: Add APM X-Gene SoC 15Gbps Multi-purpose PHY driver
binding documentation
PHY: add APM X-Gene SoC 15Gbps Multi-purpose PHY driver
arm64: Add APM X-Gene SoC 15Gbps Multi-purpose PHY DTS entries
.../devicetree/bindings/phy/apm-xgene-phy.txt | 94 + arch/arm64/boot/dts/apm-storm.dtsi | 76 + drivers/phy/Kconfig | 7 + drivers/phy/Makefile | 2 + drivers/phy/phy-core.c | 21 + drivers/phy/phy-xgene.c | 1811 ++++++++++++++++++++ include/linux/phy/phy.h | 8 + 7 files changed, 2019 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/apm-xgene-phy.txt create mode 100644 drivers/phy/phy-xgene.c
PATCH v6 1/4 PHY: Add function set_speed to generic PHY framework
This patch adds function set_speed to the generic PHY framework operation structure. This function can be called to instruct the PHY underlying layer at specified lane to configure for specified speed in hertz.
--- drivers/phy/phy-core.c | 21 +++++++++++++++++++++ include/linux/phy/phy.h | 8 ++++++++ 2 files changed, 29 insertions(+), 0 deletions(-)
drivers/phy/phy-core.c +21 -0
@@ -239,6 +239,27 @@ out: }EXPORT_SYMBOL_GPL (phy_power_off); +int phy_set_speed (struct phy *phy,int lane,u64 speed) +{ +int ret = -ENOTSUPP ; + +mutex_lock (&phy->mutex); +if (phy->ops->set_speed) { + ret = phy->ops->set_speed (phy, lane, speed); +if (ret <0 ) { +dev_err (&phy->dev,"phy set speed failed --> %d\n" , + ret); + goto out; + } + } + +out: +mutex_unlock (&phy->mutex); + +return ret; +} +EXPORT_SYMBOL_GPL (phy_set_speed); +/** * of_phy_get() - lookup and obtain a reference to a phy by phandle * @dev: device that requests this phy
include/linux/phy/phy.h +8 -0
@@ -27,6 +27,7 @@ struct phy;* @exit: operation to be performed while exiting * @power_on: powering on the phy * @power_off: powering off the phy +* @set_speed: set operation speed in hz * @owner: the module owner containing the ops */ struct phy_ops {
@@ -34,6 +35,7 @@ struct phy_ops {int (*exit)(struct phy *phy);int (*power_on)(struct phy *phy);int (*power_off)(struct phy *phy); +int (*set_speed)(struct phy *phy,int lane,u64 speed);struct module *owner; };
@@ -127,6 +129,7 @@ int phy_init(struct phy *phy);int phy_exit (struct phy *phy);int phy_power_on (struct phy *phy);int phy_power_off (struct phy *phy); +int phy_set_speed (struct phy *phy,int lane,u64 speed);struct phy *phy_get (struct device *dev,const char *string);struct phy *devm_phy_get (struct device *dev,const char *string);void phy_put (struct phy *phy);
@@ -199,6 +202,11 @@ static inline int phy_power_off(struct phy *phy)return -ENOSYS ; } +static inline int phy_set_speed (struct phy *phy,int lane,u64 speed) +{ +return -ENOSYS ; +} +static inline struct phy *phy_get (struct device *dev,const char *string) {return ERR_PTR (-ENOSYS );
Signature · 1 line
1.5.5
PATCH v6 2/4 Documentation: Add APM X-Gene SoC 15Gbps Multi-purpose PHY driver binding documentation
--- .../devicetree/bindings/phy/apm-xgene-phy.txt | 94 ++++++++++++++++++++ 1 files changed, 94 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/apm-xgene-phy.txt
Documentation/devicetree/bindings/phy/apm-xgene-phy.txt new file +94 -0
@@ -0,0 +1,94 @@ +* APM X-Gene 15Gbps Multi-purpose PHY nodes + +PHY nodes are defined to describe on-chip 15Gbps Multi-purpose PHY. Each +PHY (pair of lanes) has its own node. + +Required properties: +- compatible : Shall be "apm,xgene-phy" or + "apm,xgene-phy-ext". The "apm,xgene-phy" describes + an PHY with internal reference PLL located within + the IP. The "apm,xgene-phy-ext" describes an PHY + where the internal reference PLL located outside of + the IP. +- reg : First PHY memory resource is the SDS PHY access + resource. + Second PHY memory resource is the SDS PHY access + resource outside of the IP if it is type + "apm,xgene-phy-ext". +- #phy-cells : Shall be 1 as it expects one argument for setting + the mode of the PHY. Possible values are 0 (SATA), + 1 (SGMII), 2 (PCIe), 3 (USB), and 4 (XFI). + +Optional properties: +- status : Shall be "ok" if enabled or "disabled" if disabled. + Default is "ok". +- apm,tx-eye-tuning : Manual control to fine tune the capture of the serial + bit lines from the automatic calibrated position. + Two set of 3-tuple setting for each (up to 3) + supported link speed on the host. Range from 0 to + 127 in unit of one bit period. Default is 10. +- apm,tx-eye-direction : Eye tuning manual control direction. 0 means sample + data earlier than the nominal sampling point. 1 means + sample data later than the nominal sampling point. + Two set of 3-tuple setting for each (up to 3) + supported link speed on the host. Default is 0. +- apm,tx-boost-gain : Frequency boost AC (LSB 3-bit) and DC (2-bit) + gain control. Two set of 3-tuple setting for each + (up to 3) supported link speed on the host. Range is + between 0 to 31 in unit of dB. Default is 3. +- apm,tx-amplitude : Amplitude control. Two set of 3-tuple setting for + each (up to 3) supported link speed on the host. + Range is between 0 to 199500 in unit of uV. + Default is 199500 uV. +- apm,tx-pre-cursor1 : 1st pre-cursor emphasis taps control. Two set of + 3-tuple setting for each (up to 3) supported link + speed on the host. Range is 0 to 273000 in unit of + uV. Default is 0. +- apm,tx-pre-cursor2 : 2st pre-cursor emphasis taps control. Two set of + 3-tuple setting for each (up to 3) supported link + speed on the host. Range is 0 to 127400 in unit uV. + Default is 0x0. +- apm,tx-post-cursor : Post-cursor emphasis taps control. Two set of + 3-tuple setting for Gen1, Gen2, and Gen3. Range is + between 0 to 0x1f in unit of 18.2mV. Default is 0xf. +- apm,tx-speed : Tx operating speed. One set of 3-tuple for each + supported link speed on the host. + 0 = 1-2Gbps + 1 = 2-4Gbps (1st tuple default) + 2 = 4-8Gbps + 3 = 8-15Gbps (2nd tuple default) + 4 = 2.5-4Gbps + 5 = 4-5Gbps + 6 = 5-6Gbps + 7 = 6-16Gbps (3rd tuple default) + +NOTE: PHY override parameters are board specific setting. + +Example: + phy1: phy at 1f21a000 { + compatible = "apm,xgene-phy"; + reg = <0x0 0x1f21a000 0x0 0x100>; + #phy-cells = <1>; + status = "disabled"; + apm,tx-boost-gain = <2 2 2 2 2 2>; + apm,tx-eye-tuning = <10 10 10 10 10 10>; + }; + + phy2: phy at 1f22a000 { + compatible = "apm,xgene-phy"; + reg = <0x0 0x1f22a000 0x0 0x100>; + #phy-cells = <1>; + status = "ok"; + apm,tx-boost-gain = <2 2 2 2 2 2>; + apm,tx-eye-tuning = <10 10 10 5 5 5>; + }; + + phy3: phy at 1f23a000 { + compatible = "apm,xgene-phy-ext"; + reg = <0x0 0x1f23a000 0x0 0x100>, + <0x0 0x1f2d0000 0x0 0x100>; + #phy-cells = <1>; + status = "ok"; + apm,tx-boost-gain = <3 3 3 3 3 3>; + apm,tx-eye-tuning = <10 10 10 12 12 12>; + };
Signature · 1 line
1.5.5
PATCH v6 3/4 PHY: add APM X-Gene SoC 15Gbps Multi-purpose PHY driver
This patch adds support for APM X-Gene SoC 15Gbps Multi-purpose PHY. This is the physical layer interface for the corresponding host controller. This driver uses the new PHY generic framework posted by Kishon Vijay Abrahm. Currently, only external clock and SATA mode are supported.
--- drivers/phy/Kconfig | 7 + drivers/phy/Makefile | 2 + drivers/phy/phy-xgene.c | 1811 +++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 1820 insertions(+), 0 deletions(-) create mode 100644 drivers/phy/phy-xgene.c
drivers/phy/Kconfig +7 -0
@@ -51,4 +51,11 @@ config PHY_EXYNOS_DP_VIDEO help Support for Display Port PHY found on Samsung EXYNOS SoCs. +config PHY_XGENE + tristate "APM X-Gene 15Gbps PHY support" + depends on ARM64 || COMPILE_TEST + select GENERIC_PHY + help + This option enables support for APM X-Gene SoC multi-purpose PHY. + endmenu
drivers/phy/Makefile +2 -0
@@ -7,3 +7,5 @@ obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o +obj-$(CONFIG_PHY_XGENE) += phy-xgene.o +
drivers/phy/phy-xgene.c new file +1811 -0
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Signature · 1 line
1.5.5
PATCH v6 4/4 arm64: Add APM X-Gene SoC 15Gbps Multi-purpose PHY DTS entries
This patch adds the DTS entries for the APM X-Gene SoC 15Gbps Multi-purpose PHY driver. The PHY for SATA controller 0 and 1 are enabled by default.
--- arch/arm64/boot/dts/apm-storm.dtsi | 76 ++++++++++++++++++++++++++++++++++++ 1 files changed, 76 insertions(+), 0 deletions(-)
arch/arm64/boot/dts/apm-storm.dtsi +76 -0
@@ -176,6 +176,51 @@ reg-names = "csr-reg"; clock-output-names = "eth8clk"; }; + + sataphy1clk: sataphy1clk at 1f21c000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + clock-names = "socplldiv2"; + reg = <0x0 0x1f21c000 0x0 0x1000>; + reg-names = "csr-reg"; + clock-output-names = "sataphy1clk"; + status = "disabled"; + csr-offset = <0x4>; + csr-mask = <0x00>; + enable-offset = <0x0>; + enable-mask = <0x06>; + }; + + sataphy2clk: sataphy1clk at 1f22c000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + clock-names = "socplldiv2"; + reg = <0x0 0x1f22c000 0x0 0x1000>; + reg-names = "csr-reg"; + clock-output-names = "sataphy2clk"; + status = "ok"; + csr-offset = <0x4>; + csr-mask = <0x3a>; + enable-offset = <0x0>; + enable-mask = <0x06>; + }; + + sataphy3clk: sataphy1clk at 1f23c000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + clock-names = "socplldiv2"; + reg = <0x0 0x1f23c000 0x0 0x1000>; + reg-names = "csr-reg"; + clock-output-names = "sataphy3clk"; + status = "ok"; + csr-offset = <0x4>; + csr-mask = <0x3a>; + enable-offset = <0x0>; + enable-mask = <0x06>; + }; }; serial0: serial at 1c020000 {
@@ -193,5 +238,36 @@ reg = <0x0 0x17000014 0x0 0x100>; mask = <0x1>; }; + + phy1: phy at 1f21a000 { + compatible = "apm,xgene-phy"; + reg = <0x0 0x1f21a000 0x0 0x100>; + #phy-cells = <1>; + clocks = <&sataphy1clk 0>; + status = "disabled"; + apm,tx-boost-gain = <2 3 3 2 3 3>; + apm,tx-eye-tuning = <2 10 10 2 10 10>; + }; + + phy2: phy at 1f22a000 { + compatible = "apm,xgene-phy"; + reg = <0x0 0x1f22a000 0x0 0x100>; + #phy-cells = <1>; + clocks = <&sataphy2clk 0>; + status = "ok"; + apm,tx-boost-gain = <2 3 2 2 3 2>; + apm,tx-eye-tuning = <1 10 10 2 10 5>; + }; + + phy3: phy at 1f23a000 { + compatible = "apm,xgene-phy-ext"; + reg = <0x0 0x1f23a000 0x0 0x100>, + <0x0 0x1f2d0000 0x0 0x100>; + #phy-cells = <1>; + clocks = <&sataphy3clk 0>; + status = "ok"; + apm,tx-boost-gain = <2 3 3 2 3 3>; + apm,tx-eye-tuning = <2 10 10 2 10 12>; + }; }; };
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1.5.5