mtd: spi-nor: misc. updates, de-duplication

PATCH In review Brian Norris 3 participants 17 messages Apr 11, 2014 – Apr 14, 2014

Subsystems (3)

Documentation Memory technology devices (MTD) SPI NOR

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Brian Norris

author

2014-04-11 19:00 UTC #0 lore raw

v3 cover mtd: spi-nor: misc. updates, de-duplication

A few miscellaneous updates, cleanups, and de-duplications. Mostly trivial stuff, but I had a few oversights in the first round...and in the second round too :(

v3:
- move the fsl-quadspi.c rename of

     SPINOR_OP_QUAD_READ => SPINOR_OP_READ_1_1_4

from patch 8 to patch 3, so that the series bisects properly
- add new patch 11, caught while testing with sparse

v2:
- opcode renames to fsl-quadspi.c (missed a few; I compiled it this time!)
- additional whitespace consistency cleanups
- tweak documentation wording/formatting
- additonal patch (patch 10), to allow building spi-nor as a module

Brian Norris (11):
mtd: spi-nor: drop \t after #define
mtd: spi-nor: re-name OPCODE_* to SPINOR_OP_*
mtd: spi-nor: unify read opcode variants with ST SPI FSM
Documentation: spi-nor: rewrite some portions
mtd: spi-nor: shorten Kconfig naming
mtd: st_spi_fsm: fixup Kconfig dependency
mtd: st_spi_fsm: kill duplicate CMD definitions
mtd: st_spi_fsm: replace FLACH_CMD_* with SPINOR_OP_*
mtd: st_spi_fsm: begin using spi-nor.h opcodes
mtd: spi-nor: allow to be built as module
mtd: fsl-quadspi: fix __iomem annotations, accessors

 Documentation/mtd/spi-nor.txt           |  37 ++++----
 drivers/mtd/Makefile                    |   2 +-
 drivers/mtd/devices/Kconfig             |   4 +-
 drivers/mtd/devices/m25p80.c            |   4 +-
 drivers/mtd/devices/serial_flash_cmds.h |  44 +++-------
 drivers/mtd/devices/st_spi_fsm.c        | 149 ++++++++++++--------------------
 drivers/mtd/spi-nor/Kconfig             |  11 ++-
 drivers/mtd/spi-nor/Makefile            |   2 +-
 drivers/mtd/spi-nor/fsl-quadspi.c       |  64 +++++++-------
 drivers/mtd/spi-nor/spi-nor.c           |  64 +++++++-------
 include/linux/mtd/spi-nor.h             |  80 +++++++++--------
 11 files changed, 211 insertions(+), 250 deletions(-)

Signature · 1 line

1.8.3.2

Brian Norris

author

2014-04-11 19:00 UTC #1 lore raw

PATCH v3 1/11 mtd: spi-nor: drop \t after #define

Spacing is a little non-standard here. Fix up tabs vs. spaces.

Signed-off-by Brian Norris <[email protected]>

Acked-by Huang Shijie <[email protected]>

Reviewed-by Marek Vasut <[email protected]>

---
v3: no change

 include/linux/mtd/spi-nor.h | 72 ++++++++++++++++++++++-----------------------
 1 file changed, 36 insertions(+), 36 deletions(-)

include/linux/mtd/spi-nor.h +36 ~~-36~~

index 9428d285489b..a6e87190ead1 100644
@@ -11,55 +11,55 @@
 #define __LINUX_MTD_SPI_NOR_H
 
 /* Flash opcodes. */
-#define	OPCODE_WREN		0x06	/* Write enable */
-#define	OPCODE_RDSR		0x05	/* Read status register */
-#define	OPCODE_WRSR		0x01	/* Write status register 1 byte */
-#define	OPCODE_NORM_READ	0x03	/* Read data bytes (low frequency) */
-#define	OPCODE_FAST_READ	0x0b	/* Read data bytes (high frequency) */
-#define	OPCODE_DUAL_READ        0x3b    /* Read data bytes (Dual SPI) */
-#define	OPCODE_QUAD_READ        0x6b    /* Read data bytes (Quad SPI) */
-#define	OPCODE_PP		0x02	/* Page program (up to 256 bytes) */
-#define	OPCODE_BE_4K		0x20	/* Erase 4KiB block */
-#define	OPCODE_BE_4K_PMC	0xd7	/* Erase 4KiB block on PMC chips */
-#define	OPCODE_BE_32K		0x52	/* Erase 32KiB block */
-#define	OPCODE_CHIP_ERASE	0xc7	/* Erase whole flash chip */
-#define	OPCODE_SE		0xd8	/* Sector erase (usually 64KiB) */
-#define	OPCODE_RDID		0x9f	/* Read JEDEC ID */
-#define	OPCODE_RDCR             0x35    /* Read configuration register */
+#define OPCODE_WREN		0x06	/* Write enable */
+#define OPCODE_RDSR		0x05	/* Read status register */
+#define OPCODE_WRSR		0x01	/* Write status register 1 byte */
+#define OPCODE_NORM_READ	0x03	/* Read data bytes (low frequency) */
+#define OPCODE_FAST_READ	0x0b	/* Read data bytes (high frequency) */
+#define OPCODE_DUAL_READ	0x3b	/* Read data bytes (Dual SPI) */
+#define OPCODE_QUAD_READ	0x6b	/* Read data bytes (Quad SPI) */
+#define OPCODE_PP		0x02	/* Page program (up to 256 bytes) */
+#define OPCODE_BE_4K		0x20	/* Erase 4KiB block */
+#define OPCODE_BE_4K_PMC	0xd7	/* Erase 4KiB block on PMC chips */
+#define OPCODE_BE_32K		0x52	/* Erase 32KiB block */
+#define OPCODE_CHIP_ERASE	0xc7	/* Erase whole flash chip */
+#define OPCODE_SE		0xd8	/* Sector erase (usually 64KiB) */
+#define OPCODE_RDID		0x9f	/* Read JEDEC ID */
+#define OPCODE_RDCR		0x35	/* Read configuration register */
 
 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
-#define	OPCODE_NORM_READ_4B	0x13	/* Read data bytes (low frequency) */
-#define	OPCODE_FAST_READ_4B	0x0c	/* Read data bytes (high frequency) */
-#define	OPCODE_DUAL_READ_4B	0x3c    /* Read data bytes (Dual SPI) */
-#define	OPCODE_QUAD_READ_4B	0x6c    /* Read data bytes (Quad SPI) */
-#define	OPCODE_PP_4B		0x12	/* Page program (up to 256 bytes) */
-#define	OPCODE_SE_4B		0xdc	/* Sector erase (usually 64KiB) */
+#define OPCODE_NORM_READ_4B	0x13	/* Read data bytes (low frequency) */
+#define OPCODE_FAST_READ_4B	0x0c	/* Read data bytes (high frequency) */
+#define OPCODE_DUAL_READ_4B	0x3c	/* Read data bytes (Dual SPI) */
+#define OPCODE_QUAD_READ_4B	0x6c	/* Read data bytes (Quad SPI) */
+#define OPCODE_PP_4B		0x12	/* Page program (up to 256 bytes) */
+#define OPCODE_SE_4B		0xdc	/* Sector erase (usually 64KiB) */
 
 /* Used for SST flashes only. */
-#define	OPCODE_BP		0x02	/* Byte program */
-#define	OPCODE_WRDI		0x04	/* Write disable */
-#define	OPCODE_AAI_WP		0xad	/* Auto address increment word program */
+#define OPCODE_BP		0x02	/* Byte program */
+#define OPCODE_WRDI		0x04	/* Write disable */
+#define OPCODE_AAI_WP		0xad	/* Auto address increment word program */
 
 /* Used for Macronix and Winbond flashes. */
-#define	OPCODE_EN4B		0xb7	/* Enter 4-byte mode */
-#define	OPCODE_EX4B		0xe9	/* Exit 4-byte mode */
+#define OPCODE_EN4B		0xb7	/* Enter 4-byte mode */
+#define OPCODE_EX4B		0xe9	/* Exit 4-byte mode */
 
 /* Used for Spansion flashes only. */
-#define	OPCODE_BRWR		0x17	/* Bank register write */
+#define OPCODE_BRWR		0x17	/* Bank register write */
 
 /* Status Register bits. */
-#define	SR_WIP			1	/* Write in progress */
-#define	SR_WEL			2	/* Write enable latch */
+#define SR_WIP			1	/* Write in progress */
+#define SR_WEL			2	/* Write enable latch */
 /* meaning of other SR_* bits may differ between vendors */
-#define	SR_BP0			4	/* Block protect 0 */
-#define	SR_BP1			8	/* Block protect 1 */
-#define	SR_BP2			0x10	/* Block protect 2 */
-#define	SR_SRWD			0x80	/* SR write protect */
+#define SR_BP0			4	/* Block protect 0 */
+#define SR_BP1			8	/* Block protect 1 */
+#define SR_BP2			0x10	/* Block protect 2 */
+#define SR_SRWD			0x80	/* SR write protect */
 
-#define SR_QUAD_EN_MX           0x40    /* Macronix Quad I/O */
+#define SR_QUAD_EN_MX		0x40	/* Macronix Quad I/O */
 
 /* Configuration Register bits. */
-#define CR_QUAD_EN_SPAN		0x2     /* Spansion Quad I/O */
+#define CR_QUAD_EN_SPAN		0x2	/* Spansion Quad I/O */
 
 enum read_mode {
 	SPI_NOR_NORMAL = 0,

@@ -95,7 +95,7 @@ struct spi_nor_xfer_cfg {
 	u8		dummy_cycles;
 };
 
-#define	SPI_NOR_MAX_CMD_SIZE	8
+#define SPI_NOR_MAX_CMD_SIZE	8
 enum spi_nor_ops {
 	SPI_NOR_OPS_READ = 0,
 	SPI_NOR_OPS_WRITE,

Signature · 1 line

1.8.3.2

Brian Norris

author

2014-04-11 19:00 UTC #2 lore raw

PATCH v3 2/11 mtd: spi-nor: re-name OPCODE_* to SPINOR_OP_*

In reply to Brian Norris

Qualify these with a better namespace, and prepare them for use in more drivers.

Signed-off-by Brian Norris <[email protected]>

Reviewed-by Marek Vasut <[email protected]>

Acked-by Huang Shijie <[email protected]>

---
v3: no change

 drivers/mtd/devices/m25p80.c      |  4 +--
 drivers/mtd/spi-nor/fsl-quadspi.c | 58 +++++++++++++++++------------------
 drivers/mtd/spi-nor/spi-nor.c     | 64 +++++++++++++++++++--------------------
 include/linux/mtd/spi-nor.h       | 54 ++++++++++++++++-----------------
 4 files changed, 90 insertions(+), 90 deletions(-)

drivers/mtd/devices/m25p80.c +2 -2

index 4af6400ccd95..1557d8f672c1 100644
@@ -86,7 +86,7 @@ static void m25p80_write(struct spi_nor *nor, loff_t to, size_t len,
 
 	spi_message_init(&m);
 
-	if (nor->program_opcode == OPCODE_AAI_WP && nor->sst_write_second)
+	if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
 		cmd_sz = 1;
 
 	flash->command[0] = nor->program_opcode;

@@ -171,7 +171,7 @@ static int m25p80_erase(struct spi_nor *nor, loff_t offset)
 		return ret;
 
 	/* Send write enable, then erase commands. */
-	ret = nor->write_reg(nor, OPCODE_WREN, NULL, 0, 0);
+	ret = nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0, 0);
 	if (ret)
 		return ret;

drivers/mtd/spi-nor/fsl-quadspi.c +29 ~~-29~~

154 lines not on this page · raw message

drivers/mtd/spi-nor/spi-nor.c +32 ~~-32~~

212 lines not on this page · raw message

include/linux/mtd/spi-nor.h +27 ~~-27~~

68 lines not on this page · raw message

Signature · 1 line

1.8.3.2

Brian Norris

author

2014-04-11 19:00 UTC #3 lore raw

PATCH v3 3/11 mtd: spi-nor: unify read opcode variants with ST SPI FSM

In reply to Brian Norris

serial_flash_cmds.h defines our opcodes a little differently. Let's borrow its naming, since it's borrowed from the SFDP standard, and it's more extensible.

This prepares us for merging serial_flash_cmds.h and spi-nor.h opcode listing.

Signed-off-by Brian Norris <[email protected]>

Reviewed-by Marek Vasut <[email protected]>

Acked-by Huang Shijie <[email protected]>

---
v3: changed fsl-quadspi.c too (misplaced in v2)

 drivers/mtd/spi-nor/fsl-quadspi.c |  6 +++---
 drivers/mtd/spi-nor/spi-nor.c     | 16 ++++++++--------
 include/linux/mtd/spi-nor.h       | 24 ++++++++++++++++--------
 3 files changed, 27 insertions(+), 19 deletions(-)

drivers/mtd/spi-nor/fsl-quadspi.c +3 -3

index 2977f026f39d..b41bbbc531ff 100644
@@ -294,12 +294,12 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
 	lut_base = SEQID_QUAD_READ * 4;
 
 	if (q->nor_size <= SZ_16M) {
-		cmd = SPINOR_OP_QUAD_READ;
+		cmd = SPINOR_OP_READ_1_1_4;
 		addrlen = ADDR24BIT;
 		dummy = 8;
 	} else {
 		/* use the 4-byte address */
-		cmd = SPINOR_OP_QUAD_READ;
+		cmd = SPINOR_OP_READ_1_1_4;
 		addrlen = ADDR32BIT;
 		dummy = 8;
 	}

@@ -388,7 +388,7 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
 static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
 {
 	switch (cmd) {
-	case SPINOR_OP_QUAD_READ:
+	case SPINOR_OP_READ_1_1_4:
 		return SEQID_QUAD_READ;
 	case SPINOR_OP_WREN:
 		return SEQID_WREN;

drivers/mtd/spi-nor/spi-nor.c +8 -8

index 1716f3ce9949..d6f44d527701 100644
@@ -1014,16 +1014,16 @@ int spi_nor_scan(struct spi_nor *nor, const struct spi_device_id *id,
 	/* Default commands */
 	switch (nor->flash_read) {
 	case SPI_NOR_QUAD:
-		nor->read_opcode = SPINOR_OP_QUAD_READ;
+		nor->read_opcode = SPINOR_OP_READ_1_1_4;
 		break;
 	case SPI_NOR_DUAL:
-		nor->read_opcode = SPINOR_OP_DUAL_READ;
+		nor->read_opcode = SPINOR_OP_READ_1_1_2;
 		break;
 	case SPI_NOR_FAST:
-		nor->read_opcode = SPINOR_OP_FAST_READ;
+		nor->read_opcode = SPINOR_OP_READ_FAST;
 		break;
 	case SPI_NOR_NORMAL:
-		nor->read_opcode = SPINOR_OP_NORM_READ;
+		nor->read_opcode = SPINOR_OP_READ;
 		break;
 	default:
 		dev_err(dev, "No Read opcode defined\n");

@@ -1041,16 +1041,16 @@ int spi_nor_scan(struct spi_nor *nor, const struct spi_device_id *id,
 			/* Dedicated 4-byte command set */
 			switch (nor->flash_read) {
 			case SPI_NOR_QUAD:
-				nor->read_opcode = SPINOR_OP_QUAD_READ_4B;
+				nor->read_opcode = SPINOR_OP_READ4_1_1_4;
 				break;
 			case SPI_NOR_DUAL:
-				nor->read_opcode = SPINOR_OP_DUAL_READ_4B;
+				nor->read_opcode = SPINOR_OP_READ4_1_1_2;
 				break;
 			case SPI_NOR_FAST:
-				nor->read_opcode = SPINOR_OP_FAST_READ_4B;
+				nor->read_opcode = SPINOR_OP_READ4_FAST;
 				break;
 			case SPI_NOR_NORMAL:
-				nor->read_opcode = SPINOR_OP_NORM_READ_4B;
+				nor->read_opcode = SPINOR_OP_READ4;
 				break;
 			}
 			nor->program_opcode = SPINOR_OP_PP_4B;

include/linux/mtd/spi-nor.h +16 -8

index f1fe1a6659a3..53241842a7ab 100644
@@ -10,14 +10,22 @@
 #ifndef __LINUX_MTD_SPI_NOR_H
 #define __LINUX_MTD_SPI_NOR_H
 
+/*
+ * Note on opcode nomenclature: some opcodes have a format like
+ * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number
+ * of I/O lines used for the opcode, address, and data (respectively). The
+ * FUNCTION has an optional suffix of '4', to represent an opcode which
+ * requires a 4-byte (32-bit) address.
+ */
+
 /* Flash opcodes. */
 #define SPINOR_OP_WREN		0x06	/* Write enable */
 #define SPINOR_OP_RDSR		0x05	/* Read status register */
 #define SPINOR_OP_WRSR		0x01	/* Write status register 1 byte */
-#define SPINOR_OP_NORM_READ	0x03	/* Read data bytes (low frequency) */
-#define SPINOR_OP_FAST_READ	0x0b	/* Read data bytes (high frequency) */
-#define SPINOR_OP_DUAL_READ	0x3b	/* Read data bytes (Dual SPI) */
-#define SPINOR_OP_QUAD_READ	0x6b	/* Read data bytes (Quad SPI) */
+#define SPINOR_OP_READ		0x03	/* Read data bytes (low frequency) */
+#define SPINOR_OP_READ_FAST	0x0b	/* Read data bytes (high frequency) */
+#define SPINOR_OP_READ_1_1_2	0x3b	/* Read data bytes (Dual SPI) */
+#define SPINOR_OP_READ_1_1_4	0x6b	/* Read data bytes (Quad SPI) */
 #define SPINOR_OP_PP		0x02	/* Page program (up to 256 bytes) */
 #define SPINOR_OP_BE_4K		0x20	/* Erase 4KiB block */
 #define SPINOR_OP_BE_4K_PMC	0xd7	/* Erase 4KiB block on PMC chips */

@@ -28,10 +36,10 @@
 #define SPINOR_OP_RDCR		0x35	/* Read configuration register */
 
 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
-#define SPINOR_OP_NORM_READ_4B	0x13	/* Read data bytes (low frequency) */
-#define SPINOR_OP_FAST_READ_4B	0x0c	/* Read data bytes (high frequency) */
-#define SPINOR_OP_DUAL_READ_4B	0x3c	/* Read data bytes (Dual SPI) */
-#define SPINOR_OP_QUAD_READ_4B	0x6c	/* Read data bytes (Quad SPI) */
+#define SPINOR_OP_READ4		0x13	/* Read data bytes (low frequency) */
+#define SPINOR_OP_READ4_FAST	0x0c	/* Read data bytes (high frequency) */
+#define SPINOR_OP_READ4_1_1_2	0x3c	/* Read data bytes (Dual SPI) */
+#define SPINOR_OP_READ4_1_1_4	0x6c	/* Read data bytes (Quad SPI) */
 #define SPINOR_OP_PP_4B		0x12	/* Page program (up to 256 bytes) */
 #define SPINOR_OP_SE_4B		0xdc	/* Sector erase (usually 64KiB) */

Signature · 1 line

1.8.3.2

Brian Norris

author

2014-04-11 19:00 UTC #4 lore raw

PATCH v3 4/11 Documentation: spi-nor: rewrite some portions

In reply to Brian Norris

Signed-off-by Brian Norris <[email protected]>

Reviewed-by Marek Vasut <[email protected]>

---
v3: no change
v2: a few formatting, readability edits

 Documentation/mtd/spi-nor.txt | 37 ++++++++++++++++++++-----------------
 1 file changed, 20 insertions(+), 17 deletions(-)

Documentation/mtd/spi-nor.txt +20 ~~-17~~

index 294d5b06f892..548d6306ebca 100644
@@ -1,19 +1,23 @@
                           SPI NOR framework
                ============================================
 
-Part I - why we need this framework?
--------------------------------------
+Part I - Why do we need this framework?
+---------------------------------------
 
-The SPI bus controller only deals with the byte stream.
-Some controller does not works like a SPI bus controller, it works
-like a SPI NOR controller instead, such as the Freescale's QuadSPI controller.
+SPI bus controllers (drivers/spi/) only deal with streams of bytes; the bus
+controller operates agnostic of the specific device attached. However, some
+controllers (such as Freescale's QuadSPI controller) cannot easily handle
+arbitrary streams of bytes, but rather are designed specifically for SPI NOR.
 
-The Freescale's QuadSPI controller should know the NOR commands to
-find the right LUT sequence. Unfortunately, the old code can not meet
-this requirement.
+In particular, Freescale's QuadSPI controller must know the NOR commands to
+find the right LUT sequence. Unfortunately, the SPI subsystem has no notion of
+opcodes, addresses, or data payloads; a SPI controller simply knows to send or
+receive bytes (Tx and Rx). Therefore, we must define a new layering scheme under
+which the controller driver is aware of the opcodes, addressing, and other
+details of the SPI NOR protocol.
 
 Part II - How does the framework work?
--------------------------------------
+--------------------------------------
 
 This framework just adds a new layer between the MTD and the SPI bus driver.
 With this new layer, the SPI NOR controller driver does not depend on the

@@ -40,7 +44,7 @@ m25p80 code anymore.
          ------------------------
 	       SPI NOR chip
 
-  With the SPI NOR controller driver(Freescale QuadSPI), it looks like:
+  With the SPI NOR controller driver (Freescale QuadSPI), it looks like:
                    MTD
          ------------------------
               SPI NOR framework

@@ -49,11 +53,10 @@ m25p80 code anymore.
          ------------------------
 	       SPI NOR chip
 
-Part III - How can the drivers use the framework
--------------------------------------
+Part III - How can drivers use the framework?
+---------------------------------------------
 
-The main API is the spi_nor_scan(). Before you call the hook, you should
-initialize the necessary fields for spi_nor{}.
-Please see the drivers/mtd/spi-nor/spi-nor.c for detail.
-Please also reference to the fsl-quadspi.c when you want to write a new driver
-for a SPI NOR controller.
+The main API is spi_nor_scan(). Before you call the hook, a driver should
+initialize the necessary fields for spi_nor{}. Please see
+drivers/mtd/spi-nor/spi-nor.c for detail. Please also refer to fsl-quadspi.c
+when you want to write a new driver for a SPI NOR controller.

Signature · 1 line

1.8.3.2

Brian Norris

author

2014-04-11 19:01 UTC #5 lore raw

PATCH v3 5/11 mtd: spi-nor: shorten Kconfig naming

In reply to Brian Norris

Signed-off-by Brian Norris <[email protected]>

Reviewed-by Marek Vasut <[email protected]>

Acked-by Huang Shijie <[email protected]>

---
v3: no change

 drivers/mtd/Makefile         |  2 +-
 drivers/mtd/devices/Kconfig  |  2 +-
 drivers/mtd/spi-nor/Kconfig  | 11 ++++++++---
 drivers/mtd/spi-nor/Makefile |  2 +-
 4 files changed, 11 insertions(+), 6 deletions(-)

drivers/mtd/Makefile +1 -1

index 40fd15344387..99bb9a1f6e16 100644
@@ -32,5 +32,5 @@ inftl-objs		:= inftlcore.o inftlmount.o
 
 obj-y		+= chips/ lpddr/ maps/ devices/ nand/ onenand/ tests/
 
-obj-$(CONFIG_MTD_SPI_NOR_BASE)	+= spi-nor/
+obj-$(CONFIG_MTD_SPI_NOR)	+= spi-nor/
 obj-$(CONFIG_MTD_UBI)		+= ubi/

drivers/mtd/devices/Kconfig +1 -1

index 48aa1aa5820b..f9e32b53dfc6 100644
@@ -80,7 +80,7 @@ config MTD_DATAFLASH_OTP
 
 config MTD_M25P80
 	tristate "Support most SPI Flash chips (AT26DF, M25P, W25X, ...)"
-	depends on SPI_MASTER && MTD_SPI_NOR_BASE
+	depends on SPI_MASTER && MTD_SPI_NOR
 	help
 	  This enables access to most modern SPI flash chips, used for
 	  program and data storage.   Series supported include Atmel AT26DF,

drivers/mtd/spi-nor/Kconfig +8 -3

index 64cfc39ad17e..d682fb440e06 100644
@@ -1,12 +1,17 @@
-config MTD_SPI_NOR_BASE
-	bool "the framework for SPI-NOR support"
+config MTD_SPI_NOR
+	bool "SPI-NOR device support"
 	depends on MTD
 	help
 	  This is the framework for the SPI NOR which can be used by the SPI
 	  device drivers and the SPI-NOR device driver.
+
+if MTD_SPI_NOR
+
 config SPI_FSL_QUADSPI
 	tristate "Freescale Quad SPI controller"
-	depends on ARCH_MXC && MTD_SPI_NOR_BASE
+	depends on ARCH_MXC
 	help
 	  This enables support for the Quad SPI controller in master mode.
 	  We only connect the NOR to this controller now.
+
+endif # MTD_SPI_NOR

drivers/mtd/spi-nor/Makefile +1 -1

index 51f9d8b99ab7..6a7ce1462247 100644
@@ -1,2 +1,2 @@
-obj-$(CONFIG_MTD_SPI_NOR_BASE)	+= spi-nor.o
+obj-$(CONFIG_MTD_SPI_NOR)	+= spi-nor.o
 obj-$(CONFIG_SPI_FSL_QUADSPI)	+= fsl-quadspi.o

Signature · 1 line

1.8.3.2

Brian Norris

author

2014-04-11 19:01 UTC #6 lore raw

PATCH v3 6/11 mtd: st_spi_fsm: fixup Kconfig dependency

In reply to Brian Norris

I hear that this driver should depend on ARCH_STI, and that "SH" is not actually a real symbol. At the same time, let's allow compile-testing on other ARCH'es.

Signed-off-by Brian Norris <[email protected]>

Acked-by Lee Jones <[email protected]>

Reviewed-by Marek Vasut <[email protected]>

---
v3: no change

 drivers/mtd/devices/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

drivers/mtd/devices/Kconfig +1 -1

index f9e32b53dfc6..9aae1042c14f 100644
@@ -212,7 +212,7 @@ config MTD_DOCG3
 
 config MTD_ST_SPI_FSM
 	tristate "ST Microelectronics SPI FSM Serial Flash Controller"
-	depends on ARM || SH
+	depends on ARCH_STI || COMPILE_TEST
 	help
 	  This provides an MTD device driver for the ST Microelectronics
 	  SPI Fast Sequence Mode (FSM) Serial Flash Controller and support

Signature · 1 line

1.8.3.2

Brian Norris

author

2014-04-11 19:01 UTC #7 lore raw

PATCH v3 7/11 mtd: st_spi_fsm: kill duplicate CMD definitions

In reply to Brian Norris

These are also in serial_flash_cmds.h. (FWIW, I didn't know the C preprocessor allowed redefinitions without warning like this.)

Signed-off-by Brian Norris <[email protected]>

Acked-by Lee Jones <[email protected]>

Reviewed-by Marek Vasut <[email protected]>

---
v3: no change

 drivers/mtd/devices/st_spi_fsm.c | 36 ------------------------------------
 1 file changed, 36 deletions(-)

drivers/mtd/devices/st_spi_fsm.c +0 ~~-36~~

index 30082a09f68b..122a8a14ef84 100644
@@ -201,42 +201,6 @@
 
 #define STFSM_MAX_WAIT_SEQ_MS  1000     /* FSM execution time */
 
-/* Flash Commands */
-#define FLASH_CMD_WREN         0x06
-#define FLASH_CMD_WRDI         0x04
-#define FLASH_CMD_RDID         0x9f
-#define FLASH_CMD_RDSR         0x05
-#define FLASH_CMD_RDSR2                0x35
-#define FLASH_CMD_WRSR         0x01
-#define FLASH_CMD_SE_4K                0x20
-#define FLASH_CMD_SE_32K       0x52
-#define FLASH_CMD_SE           0xd8
-#define FLASH_CMD_CHIPERASE    0xc7
-
-#define FLASH_CMD_READ         0x03    /* READ */
-#define FLASH_CMD_READ_FAST    0x0b    /* FAST READ */
-#define FLASH_CMD_READ_1_1_2   0x3b    /* DUAL OUTPUT READ */
-#define FLASH_CMD_READ_1_2_2   0xbb    /* DUAL I/O READ */
-#define FLASH_CMD_READ_1_1_4   0x6b    /* QUAD OUTPUT READ */
-#define FLASH_CMD_READ_1_4_4   0xeb    /* QUAD I/O READ */
-
-#define FLASH_CMD_WRITE                0x02    /* PAGE PROGRAM */
-#define FLASH_CMD_WRITE_1_1_2  0xa2    /* DUAL INPUT PROGRAM */
-#define FLASH_CMD_WRITE_1_2_2  0xd2    /* DUAL INPUT EXT PROGRAM */
-#define FLASH_CMD_WRITE_1_1_4  0x32    /* QUAD INPUT PROGRAM */
-#define FLASH_CMD_WRITE_1_4_4  0x12    /* QUAD INPUT EXT PROGRAM */
-
-#define FLASH_CMD_EN4B_ADDR    0xb7    /* Enter 4-byte address mode */
-#define FLASH_CMD_EX4B_ADDR    0xe9    /* Exit 4-byte address mode */
-
-/* READ commands with 32-bit addressing (N25Q256 and S25FLxxxS) */
-#define FLASH_CMD_READ4                0x13
-#define FLASH_CMD_READ4_FAST   0x0c
-#define FLASH_CMD_READ4_1_1_2  0x3c
-#define FLASH_CMD_READ4_1_2_2  0xbc
-#define FLASH_CMD_READ4_1_1_4  0x6c
-#define FLASH_CMD_READ4_1_4_4  0xec
-
 /* S25FLxxxS commands */
 #define S25FL_CMD_WRITE4_1_1_4 0x34
 #define S25FL_CMD_SE4          0xdc

Signature · 1 line

1.8.3.2

Brian Norris

author

2014-04-11 19:01 UTC #8 lore raw

PATCH v3 8/11 mtd: st_spi_fsm: replace FLACH_CMD_* with SPINOR_OP_*

In reply to Brian Norris

Begin to unify the differences between serial_flash_cmds.h and spi-nor.h.

Signed-off-by Brian Norris <[email protected]>

Acked-by Lee Jones <[email protected]>

Reviewed-by Marek Vasut <[email protected]>

---
v3: remove fsl-quadspi.c changes
v2: add changes for fsl-quadspi.c (these were incorrect; should have been in
patch 3)

 drivers/mtd/devices/serial_flash_cmds.h |  62 +++++++++---------
 drivers/mtd/devices/st_spi_fsm.c        | 112 ++++++++++++++++----------------
 2 files changed, 87 insertions(+), 87 deletions(-)

drivers/mtd/devices/serial_flash_cmds.h +31 ~~-31~~

index 4f0c2c7c898e..82fa1687a2d3 100644
@@ -13,43 +13,43 @@
 #define _MTD_SERIAL_FLASH_CMDS_H
 
 /* Generic Flash Commands/OPCODEs */
-#define FLASH_CMD_WREN		0x06
-#define FLASH_CMD_WRDI		0x04
-#define FLASH_CMD_RDID		0x9f
-#define FLASH_CMD_RDSR		0x05
-#define FLASH_CMD_RDSR2		0x35
-#define FLASH_CMD_WRSR		0x01
-#define FLASH_CMD_SE_4K		0x20
-#define FLASH_CMD_SE_32K	0x52
-#define FLASH_CMD_SE		0xd8
-#define FLASH_CMD_CHIPERASE	0xc7
-#define FLASH_CMD_WRVCR		0x81
-#define FLASH_CMD_RDVCR		0x85
+#define SPINOR_OP_WREN		0x06
+#define SPINOR_OP_WRDI		0x04
+#define SPINOR_OP_RDID		0x9f
+#define SPINOR_OP_RDSR		0x05
+#define SPINOR_OP_RDSR2		0x35
+#define SPINOR_OP_WRSR		0x01
+#define SPINOR_OP_SE_4K		0x20
+#define SPINOR_OP_SE_32K	0x52
+#define SPINOR_OP_SE		0xd8
+#define SPINOR_OP_CHIPERASE	0xc7
+#define SPINOR_OP_WRVCR		0x81
+#define SPINOR_OP_RDVCR		0x85
 
 /* JEDEC Standard - Serial Flash Discoverable Parmeters (SFDP) Commands */
-#define FLASH_CMD_READ		0x03	/* READ */
-#define FLASH_CMD_READ_FAST	0x0b	/* FAST READ */
-#define FLASH_CMD_READ_1_1_2	0x3b	/* DUAL OUTPUT READ */
-#define FLASH_CMD_READ_1_2_2	0xbb	/* DUAL I/O READ */
-#define FLASH_CMD_READ_1_1_4	0x6b	/* QUAD OUTPUT READ */
-#define FLASH_CMD_READ_1_4_4	0xeb	/* QUAD I/O READ */
+#define SPINOR_OP_READ		0x03	/* READ */
+#define SPINOR_OP_READ_FAST	0x0b	/* FAST READ */
+#define SPINOR_OP_READ_1_1_2	0x3b	/* DUAL OUTPUT READ */
+#define SPINOR_OP_READ_1_2_2	0xbb	/* DUAL I/O READ */
+#define SPINOR_OP_READ_1_1_4	0x6b	/* QUAD OUTPUT READ */
+#define SPINOR_OP_READ_1_4_4	0xeb	/* QUAD I/O READ */
 
-#define FLASH_CMD_WRITE		0x02	/* PAGE PROGRAM */
-#define FLASH_CMD_WRITE_1_1_2	0xa2	/* DUAL INPUT PROGRAM */
-#define FLASH_CMD_WRITE_1_2_2	0xd2	/* DUAL INPUT EXT PROGRAM */
-#define FLASH_CMD_WRITE_1_1_4	0x32	/* QUAD INPUT PROGRAM */
-#define FLASH_CMD_WRITE_1_4_4	0x12	/* QUAD INPUT EXT PROGRAM */
+#define SPINOR_OP_WRITE		0x02	/* PAGE PROGRAM */
+#define SPINOR_OP_WRITE_1_1_2	0xa2	/* DUAL INPUT PROGRAM */
+#define SPINOR_OP_WRITE_1_2_2	0xd2	/* DUAL INPUT EXT PROGRAM */
+#define SPINOR_OP_WRITE_1_1_4	0x32	/* QUAD INPUT PROGRAM */
+#define SPINOR_OP_WRITE_1_4_4	0x12	/* QUAD INPUT EXT PROGRAM */
 
-#define FLASH_CMD_EN4B_ADDR	0xb7	/* Enter 4-byte address mode */
-#define FLASH_CMD_EX4B_ADDR	0xe9	/* Exit 4-byte address mode */
+#define SPINOR_OP_EN4B_ADDR	0xb7	/* Enter 4-byte address mode */
+#define SPINOR_OP_EX4B_ADDR	0xe9	/* Exit 4-byte address mode */
 
 /* READ commands with 32-bit addressing */
-#define FLASH_CMD_READ4		0x13
-#define FLASH_CMD_READ4_FAST	0x0c
-#define FLASH_CMD_READ4_1_1_2	0x3c
-#define FLASH_CMD_READ4_1_2_2	0xbc
-#define FLASH_CMD_READ4_1_1_4	0x6c
-#define FLASH_CMD_READ4_1_4_4	0xec
+#define SPINOR_OP_READ4		0x13
+#define SPINOR_OP_READ4_FAST	0x0c
+#define SPINOR_OP_READ4_1_1_2	0x3c
+#define SPINOR_OP_READ4_1_2_2	0xbc
+#define SPINOR_OP_READ4_1_1_4	0x6c
+#define SPINOR_OP_READ4_1_4_4	0xec
 
 /* Configuration flags */
 #define FLASH_FLAG_SINGLE	0x000000ff

drivers/mtd/devices/st_spi_fsm.c +56 ~~-56~~

275 lines not on this page · raw message

Signature · 1 line

1.8.3.2

Brian Norris

author

2014-04-11 19:01 UTC #9 lore raw

PATCH v3 9/11 mtd: st_spi_fsm: begin using spi-nor.h opcodes

In reply to Brian Norris

Many of the serial_flash_cmds.h opcodes are duplicated with spi-nor.h. Let's begin to unify them.

Signed-off-by Brian Norris <[email protected]>

Acked-by Lee Jones <[email protected]>

Reviewed-by Marek Vasut <[email protected]>

---
v3: no change

 drivers/mtd/devices/serial_flash_cmds.h | 20 --------------------
 drivers/mtd/devices/st_spi_fsm.c        |  9 +++++----
 2 files changed, 5 insertions(+), 24 deletions(-)

drivers/mtd/devices/serial_flash_cmds.h +0 ~~-20~~

index 82fa1687a2d3..f59a125295d0 100644
@@ -13,25 +13,12 @@
 #define _MTD_SERIAL_FLASH_CMDS_H
 
 /* Generic Flash Commands/OPCODEs */
-#define SPINOR_OP_WREN		0x06
-#define SPINOR_OP_WRDI		0x04
-#define SPINOR_OP_RDID		0x9f
-#define SPINOR_OP_RDSR		0x05
 #define SPINOR_OP_RDSR2		0x35
-#define SPINOR_OP_WRSR		0x01
-#define SPINOR_OP_SE_4K		0x20
-#define SPINOR_OP_SE_32K	0x52
-#define SPINOR_OP_SE		0xd8
-#define SPINOR_OP_CHIPERASE	0xc7
 #define SPINOR_OP_WRVCR		0x81
 #define SPINOR_OP_RDVCR		0x85
 
 /* JEDEC Standard - Serial Flash Discoverable Parmeters (SFDP) Commands */
-#define SPINOR_OP_READ		0x03	/* READ */
-#define SPINOR_OP_READ_FAST	0x0b	/* FAST READ */
-#define SPINOR_OP_READ_1_1_2	0x3b	/* DUAL OUTPUT READ */
 #define SPINOR_OP_READ_1_2_2	0xbb	/* DUAL I/O READ */
-#define SPINOR_OP_READ_1_1_4	0x6b	/* QUAD OUTPUT READ */
 #define SPINOR_OP_READ_1_4_4	0xeb	/* QUAD I/O READ */
 
 #define SPINOR_OP_WRITE		0x02	/* PAGE PROGRAM */

@@ -40,15 +27,8 @@
 #define SPINOR_OP_WRITE_1_1_4	0x32	/* QUAD INPUT PROGRAM */
 #define SPINOR_OP_WRITE_1_4_4	0x12	/* QUAD INPUT EXT PROGRAM */
 
-#define SPINOR_OP_EN4B_ADDR	0xb7	/* Enter 4-byte address mode */
-#define SPINOR_OP_EX4B_ADDR	0xe9	/* Exit 4-byte address mode */
-
 /* READ commands with 32-bit addressing */
-#define SPINOR_OP_READ4		0x13
-#define SPINOR_OP_READ4_FAST	0x0c
-#define SPINOR_OP_READ4_1_1_2	0x3c
 #define SPINOR_OP_READ4_1_2_2	0xbc
-#define SPINOR_OP_READ4_1_1_4	0x6c
 #define SPINOR_OP_READ4_1_4_4	0xec
 
 /* Configuration flags */

drivers/mtd/devices/st_spi_fsm.c +5 -4

index fc193a94307d..7cc49ba78f68 100644
@@ -19,6 +19,7 @@
 #include <linux/mfd/syscon.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
+#include <linux/mtd/spi-nor.h>
 #include <linux/sched.h>
 #include <linux/delay.h>
 #include <linux/io.h>

@@ -522,7 +523,7 @@ static int stfsm_mx25_en_32bit_addr_seq(struct stfsm_seq *seq)
 {
 	seq->seq_opc[0] = (SEQ_OPC_PADS_1 |
 			   SEQ_OPC_CYCLES(8) |
-			   SEQ_OPC_OPCODE(SPINOR_OP_EN4B_ADDR) |
+			   SEQ_OPC_OPCODE(SPINOR_OP_EN4B) |
 			   SEQ_OPC_CSDEASSERT);
 
 	seq->seq[0] = STFSM_INST_CMD1;

@@ -630,7 +631,7 @@ static struct stfsm_seq stfsm_seq_erase_chip = {
 		 SEQ_OPC_OPCODE(SPINOR_OP_WREN) | SEQ_OPC_CSDEASSERT),
 
 		(SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |
-		 SEQ_OPC_OPCODE(SPINOR_OP_CHIPERASE) | SEQ_OPC_CSDEASSERT),
+		 SEQ_OPC_OPCODE(SPINOR_OP_CHIP_ERASE) | SEQ_OPC_CSDEASSERT),
 	},
 	.seq = {
 		STFSM_INST_CMD1,

@@ -665,7 +666,7 @@ static struct stfsm_seq stfsm_seq_write_status = {
 static int stfsm_n25q_en_32bit_addr_seq(struct stfsm_seq *seq)
 {
 	seq->seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |
-			   SEQ_OPC_OPCODE(SPINOR_OP_EN4B_ADDR));
+			   SEQ_OPC_OPCODE(SPINOR_OP_EN4B));
 	seq->seq_opc[1] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |
 			   SEQ_OPC_OPCODE(SPINOR_OP_WREN) |
 			   SEQ_OPC_CSDEASSERT);

@@ -788,7 +789,7 @@ static int stfsm_write_fifo(struct stfsm *fsm, const uint32_t *buf,
 static int stfsm_enter_32bit_addr(struct stfsm *fsm, int enter)
 {
 	struct stfsm_seq *seq = &fsm->stfsm_seq_en_32bit_addr;
-	uint32_t cmd = enter ? SPINOR_OP_EN4B_ADDR : SPINOR_OP_EX4B_ADDR;
+	uint32_t cmd = enter ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
 
 	seq->seq_opc[0] = (SEQ_OPC_PADS_1 |
 			   SEQ_OPC_CYCLES(8) |

Signature · 1 line

1.8.3.2

Brian Norris

author

2014-04-11 19:01 UTC #10 lore raw

PATCH v3 10/11 mtd: spi-nor: allow to be built as module

In reply to Brian Norris

There's no reason this can't be a module. Also, give SPI-NOR its own submenu.

Signed-off-by Brian Norris <[email protected]>

Reviewed-by Marek Vasut <[email protected]>

---
v3: no change
v2: new patch

 drivers/mtd/spi-nor/Kconfig | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

drivers/mtd/spi-nor/Kconfig +2 -2

index d682fb440e06..f8acfa4310ef 100644
@@ -1,5 +1,5 @@
-config MTD_SPI_NOR
-	bool "SPI-NOR device support"
+menuconfig MTD_SPI_NOR
+	tristate "SPI-NOR device support"
 	depends on MTD
 	help
 	  This is the framework for the SPI NOR which can be used by the SPI

Signature · 1 line

1.8.3.2

Brian Norris

author

2014-04-11 19:01 UTC #11 lore raw

PATCH v3 11/11 mtd: fsl-quadspi: fix __iomem annotations, accessors

In reply to Brian Norris

This corrects some sparse warnings:

drivers/mtd/spi-nor/fsl-quadspi.c:281:31: warning: incorrect type in initializer (different address spaces) [sparse]
drivers/mtd/spi-nor/fsl-quadspi.c:281:31: expected void *[noderef] <asn:2>base [sparse]
drivers/mtd/spi-nor/fsl-quadspi.c:281:31: got void [noderef] <asn:2>*iobase [sparse]
(etc.)

and

drivers/mtd/spi-nor/fsl-quadspi.c:733:53: warning: incorrect type in argument 2 (different address spaces)
drivers/mtd/spi-nor/fsl-quadspi.c:733:53: expected void const *<noident>
drivers/mtd/spi-nor/fsl-quadspi.c:733:53: got void [noderef] <asn:2>*

Signed-off-by Brian Norris <[email protected]>

---
new in v3

 drivers/mtd/spi-nor/fsl-quadspi.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

drivers/mtd/spi-nor/fsl-quadspi.c +3 -3

index b41bbbc531ff..e85046e734e4 100644
@@ -278,7 +278,7 @@ static irqreturn_t fsl_qspi_irq_handler(int irq, void *dev_id)
 
 static void fsl_qspi_init_lut(struct fsl_qspi *q)
 {
-	void *__iomem base = q->iobase;
+	void __iomem *base = q->iobase;
 	int rxfifo = q->devtype_data->rxfifo;
 	u32 lut_base;
 	u8 cmd, addrlen, dummy;

@@ -422,7 +422,7 @@ static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
 static int
 fsl_qspi_runcmd(struct fsl_qspi *q, u8 cmd, unsigned int addr, int len)
 {
-	void *__iomem base = q->iobase;
+	void __iomem *base = q->iobase;
 	int seqid;
 	u32 reg, reg2;
 	int err;

@@ -730,7 +730,7 @@ static int fsl_qspi_read(struct spi_nor *nor, loff_t from,
 		return ret;
 
 	/* Read out the data directly from the AHB buffer.*/
-	memcpy(buf, q->ahb_base + q->chip_base_addr + from, len);
+	memcpy_fromio(buf, q->ahb_base + q->chip_base_addr + from, len);
 
 	*retlen += len;
 	return 0;

Signature · 1 line

1.8.3.2

Huang Shijie

2014-04-12 04:57 UTC #12 lore raw

Re: [PATCH v3 11/11] mtd: fsl-quadspi: fix __iomem annotations, accessors

Quoted 34 lines · Brian Norris

This corrects some sparse warnings:
   drivers/mtd/spi-nor/fsl-quadspi.c:281:31: warning: incorrect type in initializer (different address spaces) [sparse]
   drivers/mtd/spi-nor/fsl-quadspi.c:281:31:    expected void *[noderef] <asn:2>base [sparse]
   drivers/mtd/spi-nor/fsl-quadspi.c:281:31:    got void [noderef] <asn:2>*iobase [sparse]
   (etc.)
and
drivers/mtd/spi-nor/fsl-quadspi.c:733:53: warning: incorrect type in argument 2 (different address spaces)
drivers/mtd/spi-nor/fsl-quadspi.c:733:53: expected void const *<noident>
drivers/mtd/spi-nor/fsl-quadspi.c:733:53: got void [noderef] <asn:2>*
Signed-off-by Brian Norris <[email protected]>
---
new in v3
 drivers/mtd/spi-nor/fsl-quadspi.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)
drivers/mtd/spi-nor/fsl-quadspi.c +1 -1
index b41bbbc531ff..e85046e734e4 100644
@@ -278,7 +278,7 @@ static irqreturn_t fsl_qspi_irq_handler(int irq, void *dev_id)
 
 static void fsl_qspi_init_lut(struct fsl_qspi *q)
 {
-	void *__iomem base = q->iobase;
+	void __iomem *base = q->iobase;
 	int rxfifo = q->devtype_data->rxfifo;
 	u32 lut_base;
 	u8 cmd, addrlen, dummy;

drivers/mtd/spi-nor/fsl-quadspi.c static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd) · line 425

Quoted 5 lines

drivers/mtd/spi-nor/fsl-quadspi.c +1 -1

@@ -422,7 +422,7 @@ static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
 static int
 fsl_qspi_runcmd(struct fsl_qspi *q, u8 cmd, unsigned int addr, int len)
 {
-	void *__iomem base = q->iobase;
+	void __iomem *base = q->iobase;

thanks for pointing this.

drivers/mtd/spi-nor/fsl-quadspi.c static int fsl_qspi_read(struct spi_nor *nor, loff_t from, · line 733

Quoted 9 lines

drivers/mtd/spi-nor/fsl-quadspi.c +1 -1

 	int seqid;
 	u32 reg, reg2;
 	int err;

@@ -730,7 +730,7 @@ static int fsl_qspi_read(struct spi_nor *nor, loff_t from,
 		return ret;
 
 	/* Read out the data directly from the AHB buffer.*/
-	memcpy(buf, q->ahb_base + q->chip_base_addr + from, len);
+	memcpy_fromio(buf, q->ahb_base + q->chip_base_addr + from, len);

ARM does some optimazation to the memcpy, please see arch/arm/lib/memcpy.S.

But the memcpy_fromio does not do optimazation, please see _memcpy_fromio.

Someone ever sent a patch to fix the issue, but Russell did not merge it.

please see:
http://lists.infradead.org/pipermail/linux-arm-kernel/2009-November/003860.html

So we'd better do not change to use memcpy_fromio.

BTW: i am okay with other patches about the spi-nor.

thanks
Huang Shijie

Brian Norris

author

2014-04-12 06:14 UTC #13 lore raw

Re: [PATCH v3 11/11] mtd: fsl-quadspi: fix __iomem annotations, accessors

Quoted 10 lines · Huang Shijie

drivers/mtd/spi-nor/fsl-quadspi.c static int fsl_qspi_read(struct spi_nor *nor, loff_t from, · line 733
Quoted 6 lines · Brian Norris
drivers/mtd/spi-nor/fsl-quadspi.c +1 -1
@@ -730,7 +730,7 @@ static int fsl_qspi_read(struct spi_nor *nor, loff_t from,
 		return ret;
 
 	/* Read out the data directly from the AHB buffer.*/
-	memcpy(buf, q->ahb_base + q->chip_base_addr + from, len);
+	memcpy_fromio(buf, q->ahb_base + q->chip_base_addr + from, len);
ARM does some optimazation to the memcpy, please see arch/arm/lib/memcpy.S.
But the memcpy_fromio does not do optimazation, please see _memcpy_fromio.

Ah, yes. I noticed this actually, but didn't think much about it.

Quoted 1 line

Someone ever sent a patch to fix the issue, but Russell did not merge it.

That's unfortunate.

Quoted 4 lines

please see:
http://lists.infradead.org/pipermail/linux-arm-kernel/2009-November/003860.html
So we'd better do not change to use memcpy_fromio.

How about the last recommendation of that thread, readsl()?

http://lists.infradead.org/pipermail/linux-arm-kernel/2009-November/003984.html

It has your optimization, and it has the type-checking we'd like.

Quoted 1 line

BTW: i am okay with other patches about the spi-nor.

Thanks. I'll probably merge the first 10 soon and see about respinning this one eventually.

Brian

Huang Shijie

2014-04-12 13:50 UTC #14 lore raw

Re: [PATCH v3 11/11] mtd: fsl-quadspi: fix __iomem annotations, accessors

Quoted 16 lines · Brian Norris

Quoted 10 lines · Huang Shijie
drivers/mtd/spi-nor/fsl-quadspi.c static int fsl_qspi_read(struct spi_nor *nor, loff_t from, · line 733
Quoted 6 lines · Brian Norris
drivers/mtd/spi-nor/fsl-quadspi.c +1 -1
@@ -730,7 +730,7 @@ static int fsl_qspi_read(struct spi_nor *nor, loff_t from,
 		return ret;
 
 	/* Read out the data directly from the AHB buffer.*/
-	memcpy(buf, q->ahb_base + q->chip_base_addr + from, len);
+	memcpy_fromio(buf, q->ahb_base + q->chip_base_addr + from, len);
ARM does some optimazation to the memcpy, please see arch/arm/lib/memcpy.S.
But the memcpy_fromio does not do optimazation, please see _memcpy_fromio.
Ah, yes. I noticed this actually, but didn't think much about it.
Quoted 1 line
Someone ever sent a patch to fix the issue, but Russell did not merge it.

Quoted 9 lines

That's unfortunate.
Quoted 4 lines
please see:
http://lists.infradead.org/pipermail/linux-arm-kernel/2009-November/003860.html
So we'd better do not change to use memcpy_fromio.
How about the last recommendation of that thread, readsl()?

[1] firstly, I think it is not an IO read actually.
We read the data from the AHB memory address in fact, a miss will make the controller to trigger a QUAD read to the NOR flash.

[2] secondly, the memcpy can work by the unit of 8 bytes (or more?), while the readsl can work by the unit of 4 bytes at most.

So use memcpy here is better then using the readsl.

Quoted 8 lines

http://lists.infradead.org/pipermail/linux-arm-kernel/2009-November/003984.html
It has your optimization, and it has the type-checking we'd like.
Quoted 1 line
BTW: i am okay with other patches about the spi-nor.
Thanks. I'll probably merge the first 10 soon and see about respinning this one eventually.

Please merge the first 10 patches as soon as possible. :)

thanks
Huang Shijie

Brian Norris

author

2014-04-14 18:49 UTC #15 lore raw

In reply to Brian Norris

Quoted 7 lines · Brian Norris

A few miscellaneous updates, cleanups, and de-duplications. Mostly trivial stuff, but I had a few oversights in the first round...and in the second round too :(
v3:
- move the fsl-quadspi.c rename of
     SPINOR_OP_QUAD_READ => SPINOR_OP_READ_1_1_4

Quoted 8 lines

from patch 8 to patch 3, so that the series bisects properly
- add new patch 11, caught while testing with sparse
v2:
- opcode renames to fsl-quadspi.c (missed a few; I compiled it this time!)
- additional whitespace consistency cleanups
- tweak documentation wording/formatting
- additonal patch (patch 10), to allow building spi-nor as a module

Pushed the first 10 to l2-mtd.git/spinor. I'll revisit #11 later.

Will rebase on 3.15-rc1 soon, and likely will merge to l2-mtd.git/master soon enough, so we can get -next coverage and begin informing others of the M25P80 -> MTD_SPI_NOR dependency.

Brian

Marek Vasut

2014-04-14 19:05 UTC #16 lore raw

Quoted 20 lines · Brian Norris

Quoted 11 lines · Brian Norris
A few miscellaneous updates, cleanups, and de-duplications. Mostly trivial stuff, but I had a few oversights in the first round...and in the second round too :(
v3:
- move the fsl-quadspi.c rename of
     SPINOR_OP_QUAD_READ => SPINOR_OP_READ_1_1_4
from patch 8 to patch 3, so that the series bisects properly
Quoted 7 lines
- add new patch 11, caught while testing with sparse
v2:
- opcode renames to fsl-quadspi.c (missed a few; I compiled it this time!) - additional whitespace consistency cleanups
- tweak documentation wording/formatting
- additonal patch (patch 10), to allow building spi-nor as a module

Quoted 5 lines

Pushed the first 10 to l2-mtd.git/spinor. I'll revisit #11 later.
Will rebase on 3.15-rc1 soon, and likely will merge to l2-mtd.git/master soon enough, so we can get -next coverage and begin informing others of the M25P80 -> MTD_SPI_NOR dependency.

Aye aye, captain ! :)

Best regards,
Marek Vasut