arm: socfpga: Add Cadence QSPI support

This driver is cloned from the Altera Rockerboard.org U-Boot repository. I used this git tag: ACDS14.0.1_REL_GSRD_RC2. With Some modification to support the U-Boot driver model (DM).

As mentioned above, in this new version I ported this driver to the new driver model (DM). One big advantage of this move is that now multiple SPI drivers can be enabled on one platform. And since the SoCFPGA also has the Designware SPI master controller integrated, this feature is really needed to support both controllers.

Because of this, this series needs the DT support for SoCFPGA to be applied. For DT based probing in the SPI DM.

Signed-off-by Stefan Roese <[email protected]>

Cc Chin Liang See <[email protected]>

Cc Dinh Nguyen <[email protected]>

Cc Vince Bridgers <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Pavel Machek <[email protected]>

Cc Simon Glass <[email protected]>

Cc Jagannadha Sutradharudu Teki <[email protected]>

drivers/spi/cadence_qspi.h new file +35 -0

new file mode 100644
index 0000000..c9a6142
@@ -0,0 +1,76 @@
+/*
+ * Copyright (C) 2012
+ * Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CADENCE_QSPI_H__
+#define __CADENCE_QSPI_H__
+
+#define CQSPI_IS_ADDR(cmd_len)		(cmd_len > 1 ? 1 : 0)
+
+#define CQSPI_NO_DECODER_MAX_CS		4
+#define CQSPI_DECODER_MAX_CS		16
+#define CQSPI_READ_CAPTURE_MAX_DELAY	16
+
+struct cadence_spi_platdata {
+	unsigned int	max_hz;
+	void		*regbase;
+	void		*ahbbase;
+
+	u32		page_size;
+	u32		block_size;
+	u32		tshsl_ns;
+	u32		tsd2d_ns;
+	u32		tchsh_ns;
+	u32		tslch_ns;
+};
+
+struct cadence_spi_priv {
+	void		*regbase;
+	void		*ahbbase;
+	size_t		cmd_len;
+	u8		cmd_buf[32];
+	size_t		data_len;

(quoted diff) +0 -0

b/drivers/spi/cadence_qspi_apb.c new file mode 100644 index 0000000..00a115f

drivers/spi/cadence_qspi_apb.c new file +6 -0

@@ -0,0 +1,898 @@
+/*
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are

met: + * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer. + *
- Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + *
- Neither the name of the Altera Corporation nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written
permission. + *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A

PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */

Quoted 26 lines

(quoted diff) +0 -0

b/drivers/spi/cadence_qspi_apb.c new file mode 100644 index 0000000..00a115f

drivers/spi/cadence_qspi_apb.c new file +6 -0

@@ -0,0 +1,898 @@
+/*
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are

met: + * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer. + *
- Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + *
- Neither the name of the Altera Corporation nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written
permission. + *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL,

Quoted 6 lines

EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */

This license is kinda iffy. What is this all about please ?

Hi Dinh, Hi Vince!

a quick question for you:

On 07.11.2014 16:04, Marek Vasut wrote:

<snip>

Quoted 26 lines

Quoted 26 lines

(quoted diff) +0 -0

b/drivers/spi/cadence_qspi_apb.c new file mode 100644 index 0000000..00a115f

drivers/spi/cadence_qspi_apb.c new file +6 -0

@@ -0,0 +1,898 @@
+/*
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are

met: + * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer. + *
- Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + *
- Neither the name of the Altera Corporation nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written
permission. + *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL,

Quoted 8 lines

Quoted 6 lines

EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */

This license is kinda iffy. What is this all about please ?

Yes, I was wondering about this as well. And in the Linux kernel (Rocketboards) this file is dual licensed. Here an extract:

<-------
/*
* Driver for Cadence QSPI Controller
*
* Copyright (C) 2012 Altera Corporation
*
* This software is available to you under a choice of one of two
* licenses. You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the
* OpenIB.org BSD license below:
*

 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.

*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
*/
<------

Could we not just use a "plain" GPL (v2) license here as well. Especially since the other files in this driver are just normal GPL files.

Comments welcome.

+CC: Graham Moore

Quoted 1 line · Stefan Roese

Hi Dinh, Hi Vince!

Quoted 5 lines

Could we not just use a "plain" GPL (v2) license here as well. Especially since the other files in this driver are just normal GPL files.

Comments welcome.

Graham recent posted to lkml a patch series for QSPI that has a plain GPLv2.

http://marc.info/?l=linux-kernel&m=141417788514196&w=2

Quoted 4 lines · Dinh Nguyen

+CC: Graham Moore

Quoted 1 line · Stefan Roese

Hi Dinh, Hi Vince!

<snip>

Quoted 10 lines

Quoted 5 lines

Could we not just use a "plain" GPL (v2) license here as well. Especially since the other files in this driver are just normal GPL files.

Comments welcome.

Graham recent posted to lkml a patch series for QSPI that has a plain GPLv2.

http://marc.info/?l=linux-kernel&m=141417788514196&w=2

Interesting. Thanks for this info. But what is the implication of this new plain GPLv2'ed driver code to the current code in this patch (based on your Rocketboard.org version)?

Frankly, I really don't have time and motivation to re-port this new Linux version to U-Boot to get the GPLv2 version. How could we solve this? Can you re-release this code under this new license (header)?

Quoted 23 lines · Stefan Roese

Quoted 4 lines · Dinh Nguyen

+CC: Graham Moore

Quoted 1 line · Stefan Roese

Hi Dinh, Hi Vince!

<snip>

Quoted 10 lines

Quoted 5 lines

Could we not just use a "plain" GPL (v2) license here as well. Especially since the other files in this driver are just normal GPL files.

Comments welcome.

Graham recent posted to lkml a patch series for QSPI that has a plain GPLv2.

http://marc.info/?l=linux-kernel&m=141417788514196&w=2

Interesting. Thanks for this info. But what is the implication of this new plain GPLv2'ed driver code to the current code in this patch (based on your Rocketboard.org version)?

Quoted 3 lines

Frankly, I really don't have time and motivation to re-port this new Linux version to U-Boot to get the GPLv2 version. How could we solve this? Can you re-release this code under this new license (header)?

Hi,

I have this one still marked as "Open Issue", any news here ?

Quoted 28 lines · Marek Vasut

Quoted 26 lines · Stefan Roese

Quoted 4 lines · Dinh Nguyen

+CC: Graham Moore

Quoted 1 line · Stefan Roese

Hi Dinh, Hi Vince!

<snip>

Quoted 10 lines

Quoted 5 lines

Could we not just use a "plain" GPL (v2) license here as well. Especially since the other files in this driver are just normal GPL files.

Comments welcome.

Graham recent posted to lkml a patch series for QSPI that has a plain GPLv2.

http://marc.info/?l=linux-kernel&m=141417788514196&w=2

Interesting. Thanks for this info. But what is the implication of this new plain GPLv2'ed driver code to the current code in this patch (based on your Rocketboard.org version)?

Frankly, I really don't have time and motivation to re-port this new Linux version to U-Boot to get the GPLv2 version. How could we solve this? Can you re-release this code under this new license (header)?

Quoted 3 lines

Hi,

I have this one still marked as "Open Issue", any news here ?

Not from my side I'm afraid. Perhaps somebody from Altera (Dinh, Graham?) could chime in and let us know, if it would be possible to license the current QSPI file under GPL?

This driver is cloned from the Altera Rockerboard.org U-Boot repository. I used this git tag: ACDS14.0.1_REL_GSRD_RC2. With Some modification to support the U-Boot driver model (DM).

As mentioned above, in this new version I ported this driver to the new driver model (DM). One big advantage of this move is that now multiple SPI drivers can be enabled on one platform. And since the SoCFPGA also has the Designware SPI master controller integrated, this feature is really needed to support both controllers.

Because of this, this series needs the DT support for SoCFPGA to be applied. For DT based probing in the SPI DM.

Signed-off-by Stefan Roese <[email protected]>

Cc Chin Liang See <[email protected]>

Cc Dinh Nguyen <[email protected]>

Cc Vince Bridgers <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Pavel Machek <[email protected]>

Cc Simon Glass <[email protected]>

Cc Jagannadha Sutradharudu Teki <[email protected]>

---
v4:
- Reworked to support driver model (DM)
- Coding-style changes to make it checkpatch clean

v3:
- Added SPDX License Indentifier
- Removed CQSPI_WRITEL / CQSPI_READL

 drivers/spi/Makefile           |   1 +
 drivers/spi/cadence_qspi.c     | 345 ++++++++++++++++
 drivers/spi/cadence_qspi.h     |  76 ++++
 drivers/spi/cadence_qspi_apb.c | 898 +++++++++++++++++++++++++++++++++++++++++
 4 files changed, 1320 insertions(+)
 create mode 100644 drivers/spi/cadence_qspi.c
 create mode 100644 drivers/spi/cadence_qspi.h
 create mode 100644 drivers/spi/cadence_qspi_apb.c

drivers/spi/Makefile +1 -0

index eabbf27..964fdc1 100644
@@ -23,6 +23,7 @@ obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
 obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
 obj-$(CONFIG_BFIN_SPI) += bfin_spi.o
 obj-$(CONFIG_BFIN_SPI6XX) += bfin_spi6xx.o
+obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o
 obj-$(CONFIG_CF_SPI) += cf_spi.o
 obj-$(CONFIG_CF_QSPI) += cf_qspi.o
 obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o

drivers/spi/cadence_qspi.c new file +292 -0

new file mode 100644
index 0000000..fa95b19
@@ -0,0 +1,345 @@
+/*
+ * Copyright (C) 2012
+ * Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <malloc.h>
+#include <spi.h>
+#include <asm/errno.h>
+#include "cadence_qspi.h"
+
+#define CQSPI_STIG_READ                        0
+#define CQSPI_STIG_WRITE               1
+#define CQSPI_INDIRECT_READ            2
+#define CQSPI_INDIRECT_WRITE           3
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int cadence_spi_write_speed(struct udevice *bus, uint hz)
+{
+       struct cadence_spi_platdata *plat = bus->platdata;
+       struct cadence_spi_priv *priv = dev_get_priv(bus);
+
+       cadence_qspi_apb_config_baudrate_div(priv->regbase,
+                                            CONFIG_CQSPI_REF_CLK, hz);
+
+       /* Reconfigure delay timing if speed is changed. */
+       cadence_qspi_apb_delay(priv->regbase, CONFIG_CQSPI_REF_CLK, hz,
+                              plat->tshsl_ns, plat->tsd2d_ns,
+                              plat->tchsh_ns, plat->tslch_ns);
+
+       return 0;
+}
+
+/* Calibration sequence to determine the read data capture delay register */
+static int spi_calibration(struct udevice *bus)
+{
+       struct cadence_spi_platdata *plat = bus->platdata;
+       struct cadence_spi_priv *priv = dev_get_priv(bus);
+       void *base = priv->regbase;
+       u8 opcode_rdid = 0x9F;
+       unsigned int idcode = 0, temp = 0;
+       int err = 0, i, range_lo = -1, range_hi = -1;
+
+       /* start with slowest clock (1 MHz) */
+       cadence_spi_write_speed(bus, 1000000);
+
+       /* configure the read data capture delay register to 0 */
+       cadence_qspi_apb_readdata_capture(base, 1, 0);
+
+       /* Enable QSPI */
+       cadence_qspi_apb_controller_enable(base);
+
+       /* read the ID which will be our golden value */
+       err = cadence_qspi_apb_command_read(base, 1, &opcode_rdid,
+               3, (u8 *)&idcode);
+       if (err) {
+               puts("SF: Calibration failed (read)\n");
+               return err;
+       }
+
+       /* use back the intended clock and find low range */
+       cadence_spi_write_speed(bus, plat->max_hz);
+       for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) {
+               /* Disable QSPI */
+               cadence_qspi_apb_controller_disable(base);
+
+               /* reconfigure the read data capture delay register */
+               cadence_qspi_apb_readdata_capture(base, 1, i);
+
+               /* Enable back QSPI */
+               cadence_qspi_apb_controller_enable(base);
+
+               /* issue a RDID to get the ID value */
+               err = cadence_qspi_apb_command_read(base, 1, &opcode_rdid,
+                       3, (u8 *)&temp);
+               if (err) {
+                       puts("SF: Calibration failed (read)\n");
+                       return err;
+               }
+
+               /* search for range lo */
+               if (range_lo == -1 && temp == idcode) {
+                       range_lo = i;
+                       continue;
+               }
+
+               /* search for range hi */
+               if (range_lo != -1 && temp != idcode) {
+                       range_hi = i - 1;
+                       break;
+               }
+               range_hi = i;
+       }
+
+       if (range_lo == -1) {
+               puts("SF: Calibration failed (low range)\n");
+               return err;
+       }
+
+       /* Disable QSPI for subsequent initialization */
+       cadence_qspi_apb_controller_disable(base);
+
+       /* configure the final value for read data capture delay register */
+       cadence_qspi_apb_readdata_capture(base, 1, (range_hi + range_lo) / 2);
+       debug("SF: Read data capture delay calibrated to %i (%i - %i)\n",
+             (range_hi + range_lo) / 2, range_lo, range_hi);
+
+       /* just to ensure we do once only when speed or chip select change */
+       priv->qspi_calibrated_hz = plat->max_hz;
+       priv->qspi_calibrated_cs = spi_chip_select(bus);
+
+       return 0;
+}
+
+static int cadence_spi_set_speed(struct udevice *bus, uint hz)
+{
+       struct cadence_spi_platdata *plat = bus->platdata;
+       struct cadence_spi_priv *priv = dev_get_priv(bus);
+       int err;
+
+       /* Disable QSPI */
+       cadence_qspi_apb_controller_disable(priv->regbase);
+
+       cadence_spi_write_speed(bus, hz);
+
+       /* Calibration required for different SCLK speed or chip select */
+       if (priv->qspi_calibrated_hz != plat->max_hz ||
+           priv->qspi_calibrated_cs != spi_chip_select(bus)) {
+               err = spi_calibration(bus);
+               if (err)
+                       return err;
+       }
+
+       /* Enable QSPI */
+       cadence_qspi_apb_controller_enable(priv->regbase);
+
+       debug("%s: speed=%d\n", __func__, hz);
+
+       return 0;
+}
+
+static int cadence_spi_probe(struct udevice *bus)
+{
+       struct cadence_spi_platdata *plat = bus->platdata;
+       struct cadence_spi_priv *priv = dev_get_priv(bus);
+
+       priv->regbase = plat->regbase;
+       priv->ahbbase = plat->ahbbase;
+
+       if (!priv->qspi_is_init) {
+               cadence_qspi_apb_controller_init(plat);
+               priv->qspi_is_init = 1;
+       }
+
+       return 0;
+}
+
+static int cadence_spi_set_mode(struct udevice *bus, uint mode)
+{
+       struct cadence_spi_priv *priv = dev_get_priv(bus);
+       unsigned int clk_pol = (mode & SPI_CPOL) ? 1 : 0;
+       unsigned int clk_pha = (mode & SPI_CPHA) ? 1 : 0;
+
+       /* Disable QSPI */
+       cadence_qspi_apb_controller_disable(priv->regbase);
+
+       /* Set SPI mode */
+       cadence_qspi_apb_set_clk_mode(priv->regbase, clk_pol, clk_pha);
+
+       /* Enable QSPI */
+       cadence_qspi_apb_controller_enable(priv->regbase);
+
+       return 0;
+}
+
+static int cadence_spi_xfer(struct udevice *dev, unsigned int bitlen,
+                           const void *dout, void *din, unsigned long flags)
+{
+       struct udevice *bus = dev->parent;
+       struct cadence_spi_platdata *plat = bus->platdata;
+       struct cadence_spi_priv *priv = dev_get_priv(bus);
+       void *base = priv->regbase;
+       u8 *cmd_buf = priv->cmd_buf;
+       size_t data_bytes;
+       int err = 0;
+       u32 mode = CQSPI_STIG_WRITE;
+
+       if (flags & SPI_XFER_BEGIN) {
+               /* copy command to local buffer */
+               priv->cmd_len = bitlen / 8;
+               memcpy(cmd_buf, dout, priv->cmd_len);
+       }
+
+       if (flags == (SPI_XFER_BEGIN | SPI_XFER_END)) {
+               /* if start and end bit are set, the data bytes is 0. */
+               data_bytes = 0;
+       } else {
+               data_bytes = bitlen / 8;
+       }
+       debug("%s: len=%d [bytes]\n", __func__, data_bytes);
+
+       /* Set Chip select */
+       cadence_qspi_apb_chipselect(base, spi_chip_select(dev),
+                                   CONFIG_CQSPI_DECODER);
+
+       if ((flags & SPI_XFER_END) || (flags == 0)) {
+               if (priv->cmd_len == 0) {
+                       printf("QSPI: Error, command is empty.\n");
+                       return -1;
+               }
+
+               if (din && data_bytes) {
+                       /* read */
+                       /* Use STIG if no address. */
+                       if (!CQSPI_IS_ADDR(priv->cmd_len))
+                               mode = CQSPI_STIG_READ;
+                       else
+                               mode = CQSPI_INDIRECT_READ;
+               } else if (dout && !(flags & SPI_XFER_BEGIN)) {
+                       /* write */
+                       if (!CQSPI_IS_ADDR(priv->cmd_len))
+                               mode = CQSPI_STIG_WRITE;
+                       else
+                               mode = CQSPI_INDIRECT_WRITE;
+               }
+
+               switch (mode) {
+               case CQSPI_STIG_READ:
+                       err = cadence_qspi_apb_command_read(
+                               base, priv->cmd_len, cmd_buf,
+                               data_bytes, din);
+
+               break;
+               case CQSPI_STIG_WRITE:
+                       err = cadence_qspi_apb_command_write(base,
+                               priv->cmd_len, cmd_buf,
+                               data_bytes, dout);
+               break;
+               case CQSPI_INDIRECT_READ:
+                       err = cadence_qspi_apb_indirect_read_setup(plat,
+                               priv->cmd_len, cmd_buf);
+                       if (!err) {
+                               err = cadence_qspi_apb_indirect_read_execute
+                               (plat, data_bytes, din);
+                       }
+               break;
+               case CQSPI_INDIRECT_WRITE:
+                       err = cadence_qspi_apb_indirect_write_setup
+                               (plat, priv->cmd_len, cmd_buf);
+                       if (!err) {
+                               err = cadence_qspi_apb_indirect_write_execute
+                               (plat, data_bytes, dout);
+                       }
+               break;
+               default:
+                       err = -1;
+                       break;
+               }
+
+               if (flags & SPI_XFER_END) {
+                       /* clear command buffer */
+                       memset(cmd_buf, 0, sizeof(priv->cmd_buf));
+                       priv->cmd_len = 0;
+               }
+       }
+
+       return err;
+}
+
+static int cadence_spi_ofdata_to_platdata(struct udevice *bus)
+{
+       struct cadence_spi_platdata *plat = bus->platdata;
+       const void *blob = gd->fdt_blob;
+       int node = bus->of_offset;
+       int subnode;
+       u32 data[4];
+       int ret;
+
+       /* 2 base addresses are needed, lets get them from the DT */
+       ret = fdtdec_get_int_array(blob, node, "reg", data, ARRAY_SIZE(data));
+       if (ret) {
+               printf("Error: Can't get base addresses (ret=%d)!\n", ret);
+               return -ENODEV;
+       }
+
+       plat->regbase = (void *)data[0];
+       plat->ahbbase = (void *)data[2];

This DT node is taken from the Rocketboard.org Linux repsitory. And is needed to enable (configure) the Cadence DM SPI driver.

Signed-off-by Stefan Roese <[email protected]>

Cc Chin Liang See <[email protected]>

Cc Dinh Nguyen <[email protected]>

Cc Vince Bridgers <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Pavel Machek <[email protected]>

Cc Simon Glass <[email protected]>

Cc Jagannadha Sutradharudu Teki <[email protected]>

---
 arch/arm/dts/socfpga.dtsi                  | 15 +++++++++++++++
 arch/arm/dts/socfpga_cyclone5_socrates.dts | 20 ++++++++++++++++++++
 2 files changed, 35 insertions(+)

arch/arm/dts/socfpga.dtsi +5 -0

index 4472fd9..4a789a9 100644
@@ -639,6 +639,21 @@
                        clock-names = "biu", "ciu";
                };
 
+               qspi: spi at ff705000 {
+                       compatible = "cadence,qspi";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0xff705000 0x1000>,

arch/arm/dts/socfpga.dtsi +0 -0

                /* Local timer */
                timer at fffec600 {
                        compatible = "arm,cortex-a9-twd-timer";

arch/arm/dts/socfpga_cyclone5_socrates.dts +20 -1

index a1814b4..9277174 100644
@@ -48,3 +48,23 @@
 &mmc {
        status = "okay";
 };
+
+&qspi {
+       status = "okay";
+
+       flash0: n25q00 at 0 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "n25q00";
+               reg = <0>;      /* chip select */
+               spi-max-frequency = <50000000>;
+               m25p,fast-read;
+               page-size = <256>;
+               block-size = <16>; /* 2^16, 64KB */
+               read-delay = <4>;  /* delay value in read data capture register */
+               tshsl-ns = <50>;
+               tsd2d-ns = <50>;
+               tchsh-ns = <4>;
+               tslch-ns = <4>;
+       };
+};
--

2.1.3

Quoted 5 lines

arch/arm/dts/socfpga.dtsi +5 -0

+               qspi: spi at ff705000 {
+                       compatible = "cadence,qspi";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0xff705000 0x1000>,

arch/arm/dts/socfpga.dtsi line 656

Quoted 10 lines

arch/arm/dts/socfpga.dtsi +10 -0

+                               <0xffa00000 0x1000>;
+                       interrupts = <0 151 4>;
+                       clocks = <&qspi_clk>;
+                       ext-decoder = <0>;  /* external decoder */
+                       num-chipselect = <4>;
+                       fifo-depth = <128>;
+                       bus-num = <2>;
+                       status = "disabled";
+               };
+

Is this the same binding as Linux? Can you please bring in the binding document too? Some of these feel like they should have a "manufacture," prefix.

Hi Simon,

Quoted 16 lines · Simon Glass

Quoted 15 lines

arch/arm/dts/socfpga.dtsi +15 -0

+               qspi: spi at ff705000 {
+                       compatible = "cadence,qspi";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0xff705000 0x1000>,
+                               <0xffa00000 0x1000>;
+                       interrupts = <0 151 4>;
+                       clocks = <&qspi_clk>;
+                       ext-decoder = <0>;  /* external decoder */
+                       num-chipselect = <4>;
+                       fifo-depth = <128>;
+                       bus-num = <2>;
+                       status = "disabled";
+               };
+

Quoted 3 lines

Is this the same binding as Linux? Can you please bring in the binding document too? Some of these feel like they should have a "manufacture," prefix.

Yes, its from Linux. But not from kernel.org but from the Altera Rocketboards.org version (v3.16). So the bindings might change if this driver would be pushed to mainline Linux.

Quoted 23 lines · Stefan Roese

Hi Simon,

Quoted 19 lines · Simon Glass

Quoted 5 lines

arch/arm/dts/socfpga.dtsi +5 -0

+               qspi: spi at ff705000 {
+                       compatible = "cadence,qspi";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0xff705000 0x1000>,

arch/arm/dts/socfpga.dtsi line 656

Quoted 10 lines

arch/arm/dts/socfpga.dtsi +10 -0

+                               <0xffa00000 0x1000>;
+                       interrupts = <0 151 4>;
+                       clocks = <&qspi_clk>;
+                       ext-decoder = <0>;  /* external decoder */
+                       num-chipselect = <4>;
+                       fifo-depth = <128>;
+                       bus-num = <2>;
+                       status = "disabled";
+               };
+

Is this the same binding as Linux? Can you please bring in the binding document too? Some of these feel like they should have a "manufacture," prefix.

Quoted 3 lines

Yes, its from Linux. But not from kernel.org but from the Altera Rocketboards.org version (v3.16). So the bindings might change if this driver would be pushed to mainline Linux.

I guess it would be good to submit the binding to Linux for review, so that we don't end up with two incompatible bindings...

Without this alias, DM based probing does not work. So lets add this alias to get the bus numbering correct.

Signed-off-by Stefan Roese <[email protected]>

Cc Chin Liang See <[email protected]>

Cc Dinh Nguyen <[email protected]>

Cc Vince Bridgers <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Pavel Machek <[email protected]>

Cc Simon Glass <[email protected]>

Cc Jagannadha Sutradharudu Teki <[email protected]>

Without this alias, DM based probing does not work. So lets add this alias to get the bus numbering correct.

Signed-off-by Stefan Roese <[email protected]>

Cc Chin Liang See <[email protected]>

Cc Dinh Nguyen <[email protected]>

Cc Vince Bridgers <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Pavel Machek <[email protected]>

Cc Simon Glass <[email protected]>

Cc Jagannadha Sutradharudu Teki <[email protected]>