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arm: socfpga: Add Designware SPI support

PATCH New Stefan Roese 4 participants 23 messages Nov 7, 2014 – Nov 16, 2014

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Arm (32-bit) SPI
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Stefan Roese

author
#0 lore raw

cover arm: socfpga: Add Designware SPI support

Hi!

This patchset adds the driver for the Designware master SPI controller. This IP core is integrated on the Altera SoCFPGA. This implementation is a driver model (DM) implementation. So multiple SPI drivers can be used. Thats necessary, since SoCFPGA also integrates the Cadence QSPI controller used to connect the SPI NOR flashes. Without DM, using multiple SPI driver is not possible.

As mentioned above, this patchset depends on the SoCFPGA DT support. And its also done on-top of the Cadence QSPI support I posted a short while ago. But it doesn't depend on it. Its just that the patch series will most likely generate merge conflicts if not applied in this sequence.

This is tested on the SoCrates SoCFPGA board using the SPI pins on the P14 header.

Thanks,
Stefan

Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Vince Bridgers <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Simon Glass <[email protected]>
Cc Jagannadha Sutradharudu Teki <[email protected]>
author
#1 lore raw

PATCH 1/6 arm: socfpga: Add DW master SPI clock to clock_manager.c

This function will be needed by the upcoming Designware master SPI driver.

Signed-off-by Stefan Roese <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Vince Bridgers <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Pavel Machek <[email protected]>
---
 arch/arm/cpu/armv7/socfpga/clock_manager.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
arch/arm/cpu/armv7/socfpga/clock_manager.c +14 -0
index d869f47..fa3b93a 100644
@@ -507,6 +507,19 @@ unsigned int cm_get_qspi_controller_clk_hz(void)
 	return clock;
 }
 
+unsigned int cm_get_spi_controller_clk_hz(void)
+{
+	uint32_t reg, clock = 0;
+
+	clock = cm_get_per_vco_clk_hz();
+
+	/* get the clock prior L4 SP divider (periph_base_clk) */
+	reg = readl(&clock_manager_base->per_pll.perbaseclk);
+	clock /= (reg + 1);
+
+	return clock;
+}
+
 static void cm_print_clock_quick_summary(void)
 {
 	printf("MPU       %10ld kHz\n", cm_get_mpu_clk_hz() / 1000);

@@ -518,6 +531,7 @@ static void cm_print_clock_quick_summary(void)
 	printf("MMC         %8d kHz\n", cm_get_mmc_controller_clk_hz() / 1000);
 	printf("QSPI        %8d kHz\n", cm_get_qspi_controller_clk_hz() / 1000);
 	printf("UART        %8d kHz\n", cm_get_l4_sp_clk_hz() / 1000);
+	printf("SPI         %8d kHz\n", cm_get_spi_controller_clk_hz() / 1000);
 }
 
 int set_cpu_clk_info(void)
Signature · 1 line
2.1.3
#2 lore raw

PATCH 1/6 arm: socfpga: Add DW master SPI clock to clock_manager.c

Quoted 9 lines · Stefan Roese

This function will be needed by the upcoming Designware master SPI driver.

Signed-off-by Stefan Roese <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Vince Bridgers <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Pavel Machek <[email protected]>

Awww, was this missing ? Thanks!

Best regards,
Marek Vasut

#3 lore raw

PATCH 1/6 arm: socfpga: Add DW master SPI clock to clock_manager.c

In reply to Stefan Roese
Quoted 8 lines · Stefan Roese

This function will be needed by the upcoming Designware master SPI driver.

Signed-off-by Stefan Roese <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Vince Bridgers <[email protected]>
Cc Marek Vasut <[email protected]>
Acked-by Pavel Machek <[email protected]>
Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
author
#4 lore raw

PATCH 2/6 arm: socfpga: Add socfpga_spim_enable() to reset_manager.c

In reply to Stefan Roese

This function will be needed by the upcoming Designware master SPI driver. As the SPI master controller is held in reset by the current Preloader implementation. So we need to release the reset for the driver to communicate with the controller.

This function is called from arch_early_init_r() if the SPI driver is enabled.

Signed-off-by Stefan Roese <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Vince Bridgers <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Pavel Machek <[email protected]>
---
 arch/arm/cpu/armv7/socfpga/misc.c                 | 6 ++++++
 arch/arm/cpu/armv7/socfpga/reset_manager.c        | 9 +++++++++
 arch/arm/include/asm/arch-socfpga/reset_manager.h | 3 +++
 3 files changed, 18 insertions(+)
arch/arm/cpu/armv7/socfpga/misc.c +6 -0
index 8c3e5f7..73cffd3 100644
@@ -202,6 +202,12 @@ int arch_early_init_r(void)
 
 	/* Add device descriptor to FPGA device table */
 	socfpga_fpga_add();
+
+#ifdef CONFIG_DESIGNWARE_SPI
+	/* Get Designware SPI controller out of reset */
+	socfpga_spim_enable();
+#endif
+
 	return 0;
 }
arch/arm/cpu/armv7/socfpga/reset_manager.c +9 -0
index 1d3a95d..af9db85 100644
@@ -104,3 +104,12 @@ void socfpga_emac_reset(int enable)
 #endif
 	}
 }
+
+/* SPI Master enable (its held in reset by the preloader) */
+void socfpga_spim_enable(void)
+{
+	const void *reset = &reset_manager_base->per_mod_reset;
+
+	clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SPIM0_LSB);
+	clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SPIM1_LSB);
+}
arch/arm/include/asm/arch-socfpga/reset_manager.h +3 -0
index 1857b80..034135b 100644
@@ -14,6 +14,7 @@ void socfpga_bridges_reset(int enable);
 
 void socfpga_emac_reset(int enable);
 void socfpga_watchdog_reset(void);
+void socfpga_spim_enable(void);
 
 struct socfpga_reset_manager {
 	u32	status;

@@ -35,5 +36,7 @@ struct socfpga_reset_manager {
 #define RSTMGR_PERMODRST_EMAC0_LSB	0
 #define RSTMGR_PERMODRST_EMAC1_LSB	1
 #define RSTMGR_PERMODRST_L4WD0_LSB	6
+#define RSTMGR_PERMODRST_SPIM0_LSB	18
+#define RSTMGR_PERMODRST_SPIM1_LSB	19
 
 #endif /* _RESET_MANAGER_H_ */
Signature · 1 line
2.1.3
#5 lore raw

PATCH 2/6 arm: socfpga: Add socfpga_spim_enable() to reset_manager.c

Quoted 8 lines · Stefan Roese

This function will be needed by the upcoming Designware master SPI driver. As the SPI master controller is held in reset by the current Preloader implementation. So we need to release the reset for the driver to communicate with the controller.

This function is called from arch_early_init_r() if the SPI driver is enabled.

arch/arm/cpu/armv7/socfpga/reset_manager.c void socfpga_emac_reset(int enable) · line 114

Quoted 10 lines
arch/arm/cpu/armv7/socfpga/reset_manager.c +8 -0
 	}
 }
+
+/* SPI Master enable (its held in reset by the preloader) */
+void socfpga_spim_enable(void)
+{
+	const void *reset = &reset_manager_base->per_mod_reset;
+
+	clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SPIM0_LSB);
+	clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SPIM1_LSB);

Actually, you can do this with one clrbits, right?

Pavel

Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
author
#6 lore raw

PATCH 2/6 arm: socfpga: Add socfpga_spim_enable() to reset_manager.c

Quoted 9 lines · Pavel Machek
Quoted 8 lines · Stefan Roese

This function will be needed by the upcoming Designware master SPI driver. As the SPI master controller is held in reset by the current Preloader implementation. So we need to release the reset for the driver to communicate with the controller.

This function is called from arch_early_init_r() if the SPI driver is enabled.

Quoted 12 lines

arch/arm/cpu/armv7/socfpga/reset_manager.c void socfpga_emac_reset(int enable) · line 114

Quoted 10 lines
  	}
  }
arch/arm/cpu/armv7/socfpga/reset_manager.c +8 -0
+
+/* SPI Master enable (its held in reset by the preloader) */
+void socfpga_spim_enable(void)
+{
+	const void *reset = &reset_manager_base->per_mod_reset;
+
+	clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SPIM0_LSB);
+	clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SPIM1_LSB);

Actually, you can do this with one clrbits, right?

Yes, will send a follow-up patch for this.

Thanks,
Stefan

author
#7 lore raw

PATCH 3/6 spi: Add designware master SPI DM driver used on SoCFPGA

In reply to Stefan Roese

This patch adds the driver for the Designware master SPI controller. This IP core is integrated on the Altera SoCFPGA. This implementation is a driver model (DM) implementation. So multiple SPI drivers can be used. Thats necessary, since SoCFPGA also integrates the Cadence QSPI controller used to connect the SPI NOR flashes. Without DM, using multiple SPI driver is not possible.

This driver is very loosly based on the Linux driver. Most of the Linux driver is removed. Only the polling loop for the transfer is really used from this driver. As we don't support interrupts and DMA right now.

This is tested on the SoCrates SoCFPGA board using the SPI pins on the P14 header.

Signed-off-by Stefan Roese <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Vince Bridgers <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Simon Glass <[email protected]>
Cc Jagannadha Sutradharudu Teki <[email protected]>
---
 drivers/spi/Makefile         |   1 +
 drivers/spi/designware_spi.c | 425 +++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 426 insertions(+)
 create mode 100644 drivers/spi/designware_spi.c
drivers/spi/Makefile +1 -0
index 964fdc1..edbd520 100644
@@ -27,6 +27,7 @@ obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o
 obj-$(CONFIG_CF_SPI) += cf_spi.o
 obj-$(CONFIG_CF_QSPI) += cf_qspi.o
 obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
+obj-$(CONFIG_DESIGNWARE_SPI) += designware_spi.o
 obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
 obj-$(CONFIG_FTSSP010_SPI) += ftssp010_spi.o
 obj-$(CONFIG_ICH_SPI) +=  ich.o
drivers/spi/designware_spi.c new file +425 -0

425 lines not on this page · raw message

Signature · 1 line
2.1.3
#8 lore raw

PATCH 3/6 spi: Add designware master SPI DM driver used on SoCFPGA

Quoted 22 lines · Stefan Roese

This patch adds the driver for the Designware master SPI controller. This IP core is integrated on the Altera SoCFPGA. This implementation is a driver model (DM) implementation. So multiple SPI drivers can be used. Thats necessary, since SoCFPGA also integrates the Cadence QSPI controller used to connect the SPI NOR flashes. Without DM, using multiple SPI driver is not possible.

This driver is very loosly based on the Linux driver. Most of the Linux driver is removed. Only the polling loop for the transfer is really used from this driver. As we don't support interrupts and DMA right now.

This is tested on the SoCrates SoCFPGA board using the SPI pins on the P14 header.

Signed-off-by Stefan Roese <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Vince Bridgers <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Simon Glass <[email protected]>
Cc Jagannadha Sutradharudu Teki <[email protected]>

[...]

Quoted 6 lines
drivers/spi/designware_spi.c new file +0 -0
new file mode 100644
index 0000000..1bc0d04

drivers/spi/designware_spi.c line 9

Quoted 9 lines
drivers/spi/designware_spi.c new file +9 -0
@@ -0,0 +1,425 @@
+/*
+ * Designware master SPI core controller driver
+ *
+ * Copyright (C) 2014 Stefan Roese <[email protected]>
+ *
+ * Very loosly based on the Linux driver version which is:
+ * Copyright (c) 2009, Intel Corporation.
+ *
+ * SPDX-License-Identifier:	GPL-2.0

What's the agreement about the licensing now, GPL-2.0 or GPL-2.0+ ?

[...]

drivers/spi/designware_spi.c line 113

Quoted 4 lines
drivers/spi/designware_spi.c new file +4 -0
+static inline u32 dw_readl(struct dw_spi_priv *priv, u32 offset)
+{
+	return __raw_readl(priv->regs + offset);
+}

Do we really need these wrappers ?

[...]

Thanks!

#9 lore raw

PATCH 3/6 spi: Add designware master SPI DM driver used on SoCFPGA

In reply to Stefan Roese

Hi Stefan,

Quoted 14 lines · Stefan Roese

This patch adds the driver for the Designware master SPI controller. This IP core is integrated on the Altera SoCFPGA. This implementation is a driver model (DM) implementation. So multiple SPI drivers can be used. Thats necessary, since SoCFPGA also integrates the Cadence QSPI controller used to connect the SPI NOR flashes. Without DM, using multiple SPI driver is not possible.

This driver is very loosly based on the Linux driver. Most of the Linux driver is removed. Only the polling loop for the transfer is really used from this driver. As we don't support interrupts and DMA right now.

This is tested on the SoCrates SoCFPGA board using the SPI pins on the P14 header.

Quoted 8 lines
Signed-off-by Stefan Roese <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Vince Bridgers <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Simon Glass <[email protected]>
Cc Jagannadha Sutradharudu Teki <[email protected]>

For driver model things:

Reviewed-by Simon Glass <[email protected]>

Regards,
Simon

#10 lore raw

PATCH 3/6 spi: Add designware master SPI DM driver used on SoCFPGA

In reply to Stefan Roese

Hi!

You tripped my spell-checker, sorry.

Quoted 6 lines

This patch adds the driver for the Designware master SPI controller. This IP core is integrated on the Altera SoCFPGA. This implementation is a driver model (DM) implementation. So multiple SPI drivers can be used. Thats necessary, since SoCFPGA also integrates the Cadence QSPI controller used to connect the SPI NOR flashes. Without DM, using multiple SPI driver is not possible.

drivers.

Quoted 1 line

This driver is very loosly based on the Linux driver. Most of the

loosely?

Quoted 2 lines

driver is removed. Only the polling loop for the transfer is really used from this driver. As we don't support interrupts and DMA right now.

, as

Quoted 1 line

+ * Very loosly based on the Linux driver version which is:

loosely. (And citing filename here might be useful.)

Quoted 17 lines
drivers/spi/designware_spi.c new file +17 -0
+
+/* Register offsets */
+#define DW_SPI_CTRL0			0x00
+#define DW_SPI_CTRL1			0x04
+#define DW_SPI_SSIENR			0x08
+#define DW_SPI_MWCR			0x0c
+#define DW_SPI_SER			0x10
+#define DW_SPI_BAUDR			0x14
+#define DW_SPI_TXFLTR			0x18
+#define DW_SPI_RXFLTR			0x1c
+#define DW_SPI_TXFLR			0x20
+#define DW_SPI_RXFLR			0x24
+#define DW_SPI_SR			0x28
+#define DW_SPI_IMR			0x2c
+#define DW_SPI_ISR			0x30
+#define DW_SPI_RISR			0x34
+#define DW_SPI_TXOICR			0x38

drivers/spi/designware_spi.c line 48

Quoted 10 lines
drivers/spi/designware_spi.c new file +10 -0
+#define DW_SPI_RXOICR			0x3c
+#define DW_SPI_RXUICR			0x40
+#define DW_SPI_MSTICR			0x44
+#define DW_SPI_ICR			0x48
+#define DW_SPI_DMACR			0x4c
+#define DW_SPI_DMATDLR			0x50
+#define DW_SPI_DMARDLR			0x54
+#define DW_SPI_IDR			0x58
+#define DW_SPI_VERSION			0x5c
+#define DW_SPI_DR			0x60

Any chance to convert this to structure?

Quoted 1 line

+#define RX_TIMEOUT 1000

comment with units would be welcome.

Quoted 7 lines
drivers/spi/designware_spi.c new file +7 -0
+
+struct dw_spi_platdata {
+	s32 frequency;		/* Default clock frequency, -1 for none */
+	void __iomem *regs;
+};
+
+struct dw_spi_priv {

drivers/spi/designware_spi.c line 101

Quoted 10 lines
drivers/spi/designware_spi.c new file +10 -0
+	void __iomem *regs;
+	unsigned int freq;		/* Default frequency */
+	unsigned int mode;
+
+	int bits_per_word;
+	u8 cs;			/* chip select pin */
+	u8 n_bytes;		/* current is a 1/2/4 byte op */
+	u8 tmode;		/* TR/TO/RO/EEPROM */
+	u8 type;		/* SPI/SSP/MicroWire */
+	int len;

Having both n_bytes and len is "interesting". Turn n_bytes into "word_size"?

drivers/spi/designware_spi.c line 188

Quoted 11 lines
drivers/spi/designware_spi.c new file +11 -0
+static int dw_spi_probe(struct udevice *bus)
+{
+	struct dw_spi_platdata *plat = dev_get_platdata(bus);
+	struct dw_spi_priv *priv = dev_get_priv(bus);
+
+	priv->regs = plat->regs;
+	priv->freq = plat->frequency;
+
+	/* Currently only bits_per_word == 8 supported */
+	priv->bits_per_word = 8;
+	priv->n_bytes = 1;

n_bytes -> bytes_per_word? Why we have two variables for same information?

drivers/spi/designware_spi.c line 208

Quoted 3 lines
drivers/spi/designware_spi.c new file +3 -0
+	/*
+	 * Another concern is about the tx/rx mismatch, we
+	 * though to use (priv->fifo_len - rxflr - txflr) as

"thought about using"?

drivers/spi/designware_spi.c line 264

Quoted 4 lines
drivers/spi/designware_spi.c new file +4 -0
+	while (max--) {
+		rxw = dw_readw(priv, DW_SPI_DR);
+		debug("%s: rx=0x%02x\n", __func__, rxw);
+		/* Care rx only if the transfer's original "rx" is not null */

"Care about"?

drivers/spi/designware_spi.c line 303

Quoted 2 lines
drivers/spi/designware_spi.c new file +2 -0
+
+	/* spi core configured to do 8 bit transfers */

"core is"?

Thanks,
Pavel

Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
#11 lore raw

PATCH 3/6 spi: Add designware master SPI DM driver used on SoCFPGA

Quoted 17 lines · Pavel Machek

Hi!

You tripped my spell-checker, sorry.

Quoted 6 lines

This patch adds the driver for the Designware master SPI controller. This IP core is integrated on the Altera SoCFPGA. This implementation is a driver model (DM) implementation. So multiple SPI drivers can be used. Thats necessary, since SoCFPGA also integrates the Cadence QSPI controller used to connect the SPI NOR flashes. Without DM, using multiple SPI driver is not possible.

drivers.

Quoted 1 line

This driver is very loosly based on the Linux driver. Most of the

loosely?

Quoted 7 lines
Quoted 2 lines

driver is removed. Only the polling loop for the transfer is really used from this driver. As we don't support interrupts and DMA right now.

, as

Quoted 1 line

+ * Very loosly based on the Linux driver version which is:

loosely. (And citing filename here might be useful.)

I fixed the text and I placed this whole driver patchset to

u-boot-socfpga:topic/drivers/spi-20141114

Can you please fix the code so I can replace that one patch ? Or just send me one which I can squash into this patch, either way works.

Thanks!

Best regards,
Marek Vasut

author
#12 lore raw

PATCH 3/6 spi: Add designware master SPI DM driver used on SoCFPGA

Quoted 24 lines · Marek Vasut
Quoted 23 lines · Pavel Machek

Hi!

You tripped my spell-checker, sorry.

Quoted 6 lines

This patch adds the driver for the Designware master SPI controller. This IP core is integrated on the Altera SoCFPGA. This implementation is a driver model (DM) implementation. So multiple SPI drivers can be used. Thats necessary, since SoCFPGA also integrates the Cadence QSPI controller used to connect the SPI NOR flashes. Without DM, using multiple SPI driver is not possible.

drivers.

Quoted 1 line

This driver is very loosly based on the Linux driver. Most of the

loosely?

Quoted 2 lines

driver is removed. Only the polling loop for the transfer is really used from this driver. As we don't support interrupts and DMA right now.

, as

Quoted 1 line

+ * Very loosly based on the Linux driver version which is:

Quoted 8 lines
Quoted 1 line

loosely. (And citing filename here might be useful.)

I fixed the text and I placed this whole driver patchset to

u-boot-socfpga:topic/drivers/spi-20141114

Can you please fix the code so I can replace that one patch ? Or just send me one which I can squash into this patch, either way works.

Yes. I'll take a look at it tomorrow or on Monday.

Thanks,
Stefan

#13 lore raw

PATCH 3/6 spi: Add designware master SPI DM driver used on SoCFPGA

Quoted 28 lines · Stefan Roese
Quoted 27 lines · Marek Vasut
Quoted 25 lines · Pavel Machek

Hi!

You tripped my spell-checker, sorry.

Quoted 6 lines

This patch adds the driver for the Designware master SPI controller. This IP core is integrated on the Altera SoCFPGA. This implementation is a driver model (DM) implementation. So multiple SPI drivers can be used. Thats necessary, since SoCFPGA also integrates the Cadence QSPI controller used to connect the SPI NOR flashes. Without DM, using multiple SPI driver is not possible.

drivers.

Quoted 1 line

This driver is very loosly based on the Linux driver. Most of the

loosely?

Quoted 3 lines

driver is removed. Only the polling loop for the transfer is really used from this driver. As we don't support interrupts and DMA right now.

, as

Quoted 1 line

+ * Very loosly based on the Linux driver version which is:

loosely. (And citing filename here might be useful.)

Quoted 8 lines
Quoted 6 lines

I fixed the text and I placed this whole driver patchset to

u-boot-socfpga:topic/drivers/spi-20141114

Can you please fix the code so I can replace that one patch ? Or just send me one which I can squash into this patch, either way works.

Yes. I'll take a look at it tomorrow or on Monday.

Thank you !

Best regards,
Marek Vasut

author
#14 lore raw

PATCH 4/6 arm: socfpga: dts: Add spi0/1 dts nodes for the Designware master SPI devices

In reply to Stefan Roese
Signed-off-by Stefan Roese <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Vince Bridgers <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Pavel Machek <[email protected]>
---
 arch/arm/dts/socfpga.dtsi | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)
arch/arm/dts/socfpga.dtsi +28 -0
index 4a789a9..9de7ca9 100644
@@ -654,6 +654,34 @@
 			status = "disabled";
 		};
 
+		spi0: spi at fff00000 {
+			compatible = "snps,dw-spi-mmio";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xfff00000 0x1000>;
+			interrupts = <0 154 4>;
+			num-chipselect = <4>;
+			bus-num = <0>;
+			tx-dma-channel = <&pdma 16>;
+			rx-dma-channel = <&pdma 17>;
+			clocks = <&per_base_clk>;
+			status = "disabled";
+		};
+
+		spi1: spi at fff01000 {
+			compatible = "snps,dw-spi-mmio";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xfff01000 0x1000>;
+			interrupts = <0 156 4>;
+			num-chipselect = <4>;
+			bus-num = <1>;
+			tx-dma-channel = <&pdma 20>;
+			rx-dma-channel = <&pdma 21>;
+			clocks = <&per_base_clk>;
+			status = "disabled";
+		};
+
 		/* Local timer */
 		timer at fffec600 {
 			compatible = "arm,cortex-a9-twd-timer";
Signature · 1 line
2.1.3
#15 lore raw

PATCH 4/6 arm: socfpga: dts: Add spi0/1 dts nodes for the Designware master SPI devices

Quoted 5 lines · Stefan Roese
Signed-off-by Stefan Roese <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Vince Bridgers <[email protected]>
Cc Marek Vasut <[email protected]>
Acked-by Pavel Machek <[email protected]>
Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
author
#16 lore raw

PATCH 5/6 arm: socfpga: dts: socrates: Add spi1/2 aliases needed DM SPI probing

In reply to Stefan Roese

Without this alias, DM based probing does not work. So lets add this alias to get the bus numbering correct for the Designware SPI controllers.

Signed-off-by Stefan Roese <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Vince Bridgers <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Pavel Machek <[email protected]>
---
 arch/arm/dts/socfpga_cyclone5_socrates.dts | 2 ++
 1 file changed, 2 insertions(+)
arch/arm/dts/socfpga_cyclone5_socrates.dts +2 -0
index 02bb8b3..4f0bfab 100644
@@ -27,6 +27,8 @@
 
  	aliases {
 		spi0 = "/spi at ff705000";		/* QSPI */
+		spi1 = "/spi at fff00000";
+		spi2 = "/spi at fff01000";
  	};
 
 	memory {
Signature · 1 line
2.1.3
#17 lore raw

PATCH 5/6 arm: socfpga: dts: socrates: Add spi1/2 aliases needed DM SPI probing

Quoted 9 lines · Stefan Roese

Without this alias, DM based probing does not work. So lets add this alias to get the bus numbering correct for the Designware SPI controllers.

Signed-off-by Stefan Roese <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Vince Bridgers <[email protected]>
Cc Marek Vasut <[email protected]>
Acked-by Pavel Machek <[email protected]>
Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
author
#18 lore raw

PATCH 6/6 arm: socfpga: Add Designware (DW) SPI support to config header

In reply to Stefan Roese

Enable support for the DW master SPI controller in the config header for the SoCFPGA. This controller can only be enabled, if DT support is enabled.

Signed-off-by Stefan Roese <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Vince Bridgers <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Pavel Machek <[email protected]>
---
 include/configs/socfpga_common.h | 12 ++++++++++++
 1 file changed, 12 insertions(+)
include/configs/socfpga_common.h +12 -0
index 9fc4212..830b956 100644
@@ -191,6 +191,18 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #define CONFIG_CMD_SF
 #endif
 
+#ifdef CONFIG_OF_CONTROL	/* DW SPI is controlled via DT */
+#define CONFIG_CMD_DM
+#define CONFIG_DM
+#define CONFIG_DM_SPI
+#define CONFIG_DESIGNWARE_SPI
+#ifndef __ASSEMBLY__
+unsigned int cm_get_spi_controller_clk_hz(void);
+#define CONFIG_DW_SPI_REF_CLK		cm_get_spi_controller_clk_hz()
+#endif
+#define CONFIG_CMD_SPI
+#endif
+
 /*
  * Serial Driver
  */
Signature · 1 line
2.1.3
#19 lore raw

PATCH 6/6 arm: socfpga: Add Designware (DW) SPI support to config header

Quoted 20 lines · Stefan Roese

Enable support for the DW master SPI controller in the config header for the SoCFPGA. This controller can only be enabled, if DT support is enabled.

Signed-off-by Stefan Roese <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Vince Bridgers <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Pavel Machek <[email protected]>
---
 include/configs/socfpga_common.h | 12 ++++++++++++
 1 file changed, 12 insertions(+)
include/configs/socfpga_common.h +0 -0
index 9fc4212..830b956 100644
@@ -191,6 +191,18 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #define CONFIG_CMD_SF

include/configs/socfpga_common.h unsigned int cm_get_qspi_controller_clk_hz(void); · line 201

Quoted 10 lines
include/configs/socfpga_common.h +8 -0
 #endif
 
+#ifdef CONFIG_OF_CONTROL	/* DW SPI is controlled via DT */
+#define CONFIG_CMD_DM
+#define CONFIG_DM
+#define CONFIG_DM_SPI
+#define CONFIG_DESIGNWARE_SPI
+#ifndef __ASSEMBLY__
+unsigned int cm_get_spi_controller_clk_hz(void);
+#define CONFIG_DW_SPI_REF_CLK		cm_get_spi_controller_clk_hz()

Putting prototypes into configuration file is ugly. Hiding function call into macro so that it looks like constant is evil. Is there better solution?
Pavel

Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
#20 lore raw

PATCH 6/6 arm: socfpga: Add Designware (DW) SPI support to config header

Quoted 25 lines · Pavel Machek
Quoted 24 lines · Stefan Roese

Enable support for the DW master SPI controller in the config header for the SoCFPGA. This controller can only be enabled, if DT support is enabled.

Signed-off-by Stefan Roese <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Vince Bridgers <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Pavel Machek <[email protected]>

---

 include/configs/socfpga_common.h | 12 ++++++++++++
 1 file changed, 12 insertions(+)
(quoted diff) +0 -0

b/include/configs/socfpga_common.h index 9fc4212..830b956 100644

include/configs/socfpga_common.h +0 -0
@@ -191,6 +191,18 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 
 #define CONFIG_CMD_SF
 #endif
Quoted 12 lines

include/configs/socfpga_common.h unsigned int cm_get_qspi_controller_clk_hz(void); · line 201

Quoted 8 lines
include/configs/socfpga_common.h +8 -0
+#ifdef CONFIG_OF_CONTROL	/* DW SPI is controlled via DT */
+#define CONFIG_CMD_DM
+#define CONFIG_DM
+#define CONFIG_DM_SPI
+#define CONFIG_DESIGNWARE_SPI
+#ifndef __ASSEMBLY__
+unsigned int cm_get_spi_controller_clk_hz(void);
+#define CONFIG_DW_SPI_REF_CLK		cm_get_spi_controller_clk_hz()

Putting prototypes into configuration file is ugly. Hiding function call into macro so that it looks like constant is evil. Is there better solution?

The SPI driver should call this function directly. Or is there a reason why such a macro is used ?

Best regards,
Marek Vasut

author
#21 lore raw

PATCH 6/6 arm: socfpga: Add Designware (DW) SPI support to config header

Quoted 39 lines · Marek Vasut
Quoted 25 lines · Pavel Machek
Quoted 24 lines · Stefan Roese

Enable support for the DW master SPI controller in the config header for the SoCFPGA. This controller can only be enabled, if DT support is enabled.

Signed-off-by Stefan Roese <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Vince Bridgers <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Pavel Machek <[email protected]>

---

  include/configs/socfpga_common.h | 12 ++++++++++++
  1 file changed, 12 insertions(+)
(quoted diff) +0 -0

b/include/configs/socfpga_common.h index 9fc4212..830b956 100644

include/configs/socfpga_common.h +0 -0
@@ -191,6 +191,18 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 
  #define CONFIG_CMD_SF
  #endif
Quoted 12 lines

include/configs/socfpga_common.h unsigned int cm_get_qspi_controller_clk_hz(void); · line 201

Quoted 8 lines
include/configs/socfpga_common.h +8 -0
+#ifdef CONFIG_OF_CONTROL	/* DW SPI is controlled via DT */
+#define CONFIG_CMD_DM
+#define CONFIG_DM
+#define CONFIG_DM_SPI
+#define CONFIG_DESIGNWARE_SPI
+#ifndef __ASSEMBLY__
+unsigned int cm_get_spi_controller_clk_hz(void);
+#define CONFIG_DW_SPI_REF_CLK		cm_get_spi_controller_clk_hz()

Putting prototypes into configuration file is ugly. Hiding function call into macro so that it looks like constant is evil. Is there better solution?

Quoted 2 lines

The SPI driver should call this function directly. Or is there a reason why such a macro is used ?

Historically. I'll check it again and will implement it differently in the next version. Tomorrow or on Monday.

Thanks,
Stefan

#22 lore raw

PATCH 6/6 arm: socfpga: Add Designware (DW) SPI support to config header

Quoted 40 lines · Stefan Roese
Quoted 39 lines · Marek Vasut
Quoted 37 lines · Pavel Machek
Quoted 22 lines · Stefan Roese

Enable support for the DW master SPI controller in the config header for the SoCFPGA. This controller can only be enabled, if DT support is enabled.

Signed-off-by Stefan Roese <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Vince Bridgers <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Pavel Machek <[email protected]>

---

  include/configs/socfpga_common.h | 12 ++++++++++++
  1 file changed, 12 insertions(+)
(quoted diff) +0 -0

b/include/configs/socfpga_common.h index 9fc4212..830b956 100644

include/configs/socfpga_common.h +0 -0
@@ -191,6 +191,18 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 
  #define CONFIG_CMD_SF

include/configs/socfpga_common.h unsigned int cm_get_qspi_controller_clk_hz(void); · line 202

Quoted 10 lines
include/configs/socfpga_common.h +8 -0
  #endif
 
+#ifdef CONFIG_OF_CONTROL	/* DW SPI is controlled via DT */
+#define CONFIG_CMD_DM
+#define CONFIG_DM
+#define CONFIG_DM_SPI
+#define CONFIG_DESIGNWARE_SPI
+#ifndef __ASSEMBLY__
+unsigned int cm_get_spi_controller_clk_hz(void);
+#define CONFIG_DW_SPI_REF_CLK		cm_get_spi_controller_clk_hz()

Putting prototypes into configuration file is ugly. Hiding function call into macro so that it looks like constant is evil. Is there better solution?

Quoted 5 lines
Quoted 2 lines

The SPI driver should call this function directly. Or is there a reason why such a macro is used ?

Historically. I'll check it again and will implement it differently in the next version. Tomorrow or on Monday.

Roger. Thank you!

Best regards,
Marek Vasut