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ARM: OMAP3-DRA7: CP15 erratum workarounds and improvements

PATCH Superseded Nishanth Menon 3 participants 17 messages Mar 6, 2015 1 message not in the archive

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Arm (32-bit) Arm/actions semi architecture

v5 of 6 Superseded Latest is v6 →

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Nishanth Menon

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v5 cover ARM: OMAP3-DRA7: CP15 erratum workarounds and improvements

The fifth incarnation should be proper, I hope. (skipping all the blurb and pointing to v1 for the blurb).

Changes since v4:
- smc is back to handassembled thanks to gcc versions
- fixes in multiple call handling within cpu_init_cp15 -> thanks to Matt Porter's test log showing fail on r1p3 cortex-a8 (where the errata must be applied)

v4: http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/213863
V3: http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/213207/focus=213307
V2: http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/213060
V1: http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/212174

This time, the series is based on u-boot master
git://git.denx.de/u-boot.git
master 694cc87b76b1 arm, da8xx: convert ipam390 board to generic board support

Git tree: https://gitorious.org/nm-kernel/u-boot-nm (at least till gitorious is around..) branch errata-v5-master-694cc87b76b1

Git link: https://gitorious.org/nm-kernel/u-boot-nm.git errata-v5-master-694cc87b76b1

Testing: with http://paste.ubuntu.org.cn/2522971 (4.0-rc1 patch)

BeagleBoard-X15:

	Before: CPUID=0x412fc0f2 L2CTLR=0x01800083 L2ACLR=0x00000000 L2PFR=0x000009b0 ACTLR=0x00000040
	After: CPUID=0x412fc0f2 L2CTLR=0x01800083 L2ACLR=0x00000198 L2PFR=0x000009b0 ACTLR=0x00000040

OMAP5uEVM:

	Before: CPUID=0x412fc0f2 L2CTLR=0x01800083 L2ACLR=0x00000000 L2PFR=0x000009b0 ACTLR=0x00000040
	After: CPUID=0x412fc0f2 L2CTLR=0x01800083 L2ACLR=0x00000198 L2PFR=0x000009b0 ACTLR=0x00000040

Beagle-XM: this is a r3p2 cortex-a8

	Before: CPUID=0x413fc082 ACR=0x000000e2 L2AUXCR=0x00000042
	After: CPUID=0x413fc082 ACR=0x00000042 L2AUXCR=0x00000042
	To emulate matt's board, I hacked u-boot to force the code flow.
	Testing with (hack http://paste.ubuntu.org.cn/2525559): CPUID=0x413fc082 ACR=0x000000e2 L2AUXCR=0x00000042

I dont have access to other omap3 platforms to give a better coverage, so, I welcome as much testing as possible.

Nishanth Menon (10):
ARM: Introduce erratum workaround for 798870
ARM: Introduce erratum workaround for 454179
ARM: Introduce erratum workaround for 430973
ARM: Introduce erratum workaround for 621766
ARM: OMAP: Change set_pl310_ctrl_reg to be generic
ARM: OMAP3: Rename omap3.h to omap.h to be generic as all SoCs
ARM: OMAP3: Get rid of omap3_gp_romcode_call and replace with
omap_smc1
ARM: OMAP5 / DRA7: Setup L2 Aux Control Register with recommended
configuration
ARM: OMAP3: Enable workaround for ARM errata 454179, 430973, 621766
ARM: OMAP3: rx51: Enable workaround for ARM errata 454179, 430973,

    621766

Praveen Rao (1):
ARM: DRA7 / OMAP5: Add workaround for ARM errata 798870

 README                                             |    8 +++
 arch/arm/cpu/armv7/Makefile                        |    2 +-
 arch/arm/cpu/armv7/cp15.c                          |   29 +++++++++
 arch/arm/cpu/armv7/omap-common/Makefile            |    2 +-
 arch/arm/cpu/armv7/omap-common/lowlevel_init.S     |   20 +++---
 arch/arm/cpu/armv7/omap3/board.c                   |   60 +++++++-----------
 arch/arm/cpu/armv7/omap3/lowlevel_init.S           |   11 ----
 arch/arm/cpu/armv7/omap4/hwinit.c                  |    4 +-
 arch/arm/cpu/armv7/omap5/hwinit.c                  |   23 +++++++
 arch/arm/cpu/armv7/start.S                         |   64 +++++++++++++++++++-
 .../arm/include/asm/arch-omap3/{omap3.h => omap.h} |    0
 arch/arm/include/asm/arch-omap3/sys_proto.h        |    3 +-
 arch/arm/include/asm/arch-omap4/sys_proto.h        |    5 +-
 arch/arm/include/asm/arch-omap5/sys_proto.h        |    4 ++
 arch/arm/include/asm/armv7.h                       |    5 ++
 board/nokia/rx51/rx51.c                            |   19 +++---
 include/configs/am3517_crane.h                     |    6 +-
 include/configs/am3517_evm.h                       |    6 +-
 include/configs/cm_t35.h                           |    6 +-
 include/configs/cm_t3517.h                         |    6 +-
 include/configs/dig297.h                           |    6 +-
 include/configs/mcx.h                              |    6 +-
 include/configs/nokia_rx51.h                       |    6 +-
 include/configs/omap3_evm.h                        |    2 +-
 include/configs/omap3_evm_common.h                 |    4 ++
 include/configs/omap3_evm_quick_mmc.h              |    2 +-
 include/configs/omap3_evm_quick_nand.h             |    2 +-
 include/configs/omap3_logic.h                      |    6 +-
 include/configs/omap3_mvblx.h                      |    6 +-
 include/configs/omap3_pandora.h                    |    6 +-
 include/configs/omap3_sdp3430.h                    |    6 +-
 include/configs/omap3_zoom1.h                      |    2 +-
 include/configs/tam3517-common.h                   |    6 +-
 include/configs/tao3530.h                          |    6 +-
 include/configs/ti_omap3_common.h                  |    7 ++-
 include/configs/ti_omap5_common.h                  |    3 +
 include/configs/tricorder.h                        |    6 +-
 37 files changed, 275 insertions(+), 90 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/cp15.c
 rename arch/arm/include/asm/arch-omap3/{omap3.h => omap.h} (100%)

Regards,
Nishanth Menon

Signature · 1 line
1.7.9.5
author
#1 lore raw

PATCH v5 1/11 ARM: Introduce erratum workaround for 798870

Add workaround for Cortex-A15 ARM erratum 798870 which says "If back-to-back speculative cache line fills (fill A and fill B) are issued from the L1 data cache of a CPU to the L2 cache, the second request (fill B) is then cancelled, and the second request would have detected a hazard against a recent write or eviction (write B) to the same cache line as fill B then the L2 logic might deadlock."

Implementations for SoC families such as Exynos, OMAP5/DRA7 etc will be widely different.

Every SoC has slightly different manner of setting up access to L2ACLR and similar registers since the Secure Monitor handling of Secure Monitor Call(smc) is diverse. Hence an weak function is introduced which may be overriden to implement SoC specific accessor implementation.

Based on ARM errata Document revision 18.0 (22 Nov 2013)

Signed-off-by Nishanth Menon <[email protected]>

---
Change since V4:
- save lr as r5 and jump off to r5
- push and pop r5
- bl to handler instead of b

 README                       |    5 +++++
 arch/arm/cpu/armv7/Makefile  |    2 +-
 arch/arm/cpu/armv7/cp15.c    |   23 +++++++++++++++++++++++
 arch/arm/cpu/armv7/start.S   |   25 ++++++++++++++++++++++++-
 arch/arm/include/asm/armv7.h |    3 +++
 5 files changed, 56 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/cp15.c
README +5 -0
index 676f41e7f09f..9a0106066b1c 100644
@@ -690,6 +690,11 @@ The following options need to be configured:
 		exists, unlike the similar options in the Linux kernel. Do not
 		set these options unless they apply!
 
+		NOTE: The following can be machine specific errata. These
+		do have ability to provide rudimentary version and machine
+		specific checks, but expect no product checks.
+		CONFIG_ARM_ERRATA_798870
+
 - Driver Model
 		Driver model is a new framework for devices in U-Boot
 		introduced in early 2014. U-Boot is being progressively
arch/arm/cpu/armv7/Makefile +1 -1
index ad22489e1a1f..1312a9db9e84 100644
@@ -9,7 +9,7 @@ extra-y	:= start.o
 
 obj-y	+= cache_v7.o
 
-obj-y	+= cpu.o
+obj-y	+= cpu.o cp15.o
 obj-y	+= syslib.o
 
 ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI),)
arch/arm/cpu/armv7/cp15.c new file +23 -0
new file mode 100644
index 000000000000..8ac81c9ba147
@@ -0,0 +1,23 @@
+/*
+ * (C) Copyright 2015 Texas Insturments
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * CP15 specific code
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/system.h>
+#include <asm/cache.h>
+#include <asm/armv7.h>
+#include <linux/compiler.h>
+
+void __weak v7_arch_cp15_set_l2aux_ctrl(u32 l2actlr, u32 cpu_midr,
+				     u32 cpu_rev_comb, u32 cpu_variant,
+				     u32 cpu_rev)
+{
+	asm volatile ("mcr p15, 1, %0, c15, c0, 0\n\t" : : "r"(l2actlr));
+}
arch/arm/cpu/armv7/start.S +24 -1
index 9b49ece2d650..89637e26395d 100644
@@ -166,7 +166,30 @@ ENTRY(cpu_init_cp15)
 	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
 #endif
 
-	mov	pc, lr			@ back to my caller
+	mov	r5, lr			@ Store my Caller
+	mrc	p15, 0, r1, c0, c0, 0	@ r1 has Read Main ID Register (MIDR)
+	mov	r3, r1, lsr #20		@ get variant field
+	and	r3, r3, #0xf		@ r3 has CPU variant
+	and	r4, r1, #0xf		@ r4 has CPU revision
+	mov	r2, r3, lsl #4		@ shift variant field for combined value
+	orr	r2, r4, r2		@ r2 has combined CPU variant + revision
+
+#ifdef CONFIG_ARM_ERRATA_798870
+	cmp	r2, #0x30		@ Applies to lower than R3p0
+	bge	skip_errata_798870      @ skip if not affected rev
+	cmp	r2, #0x20		@ Applies to including and above R2p0
+	blt	skip_errata_798870      @ skip if not affected rev
+
+	mrc	p15, 1, r0, c15, c0, 0  @ read l2 aux ctrl reg
+	orr	r0, r0, #1 << 7         @ Enable hazard-detect timeout
+	push	{r1-r5}			@ Save the cpu info registers
+	bl	v7_arch_cp15_set_l2aux_ctrl
+	isb				@ Recommended ISB after l2actlr update
+	pop	{r1-r5}			@ Restore the cpu info - fall through
+skip_errata_798870:
+#endif
+
+	mov	pc, r5			@ back to my caller
 ENDPROC(cpu_init_cp15)
 
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
arch/arm/include/asm/armv7.h +3 -0
index edb3b80015ba..69abc4791ae5 100644
@@ -138,6 +138,9 @@ extern char __secure_end[];
 
 #endif /* CONFIG_ARMV7_NONSEC || CONFIG_ARMV7_VIRT */
 
+void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
+				 u32 cpu_rev_comb, u32 cpu_variant,
+				 u32 cpu_rev);
 #endif /* ! __ASSEMBLY__ */
 
 #endif
Signature · 1 line
1.7.9.5
author
#2 lore raw

PATCH v5 2/11 ARM: Introduce erratum workaround for 454179

In reply to Nishanth Menon

454179: Stale prediction may inhibit target address misprediction on
next predicted taken branch
Impacts: Every Cortex-A8 processors with revision lower than r2p1 Work around: Set IBE and disable branch size mispredict to 1

Also provide a hook for SoC specific handling to take place if needed.

Based on ARM errata Document revision 20.0 (13 Nov 2010)

Signed-off-by Nishanth Menon <[email protected]>

---
Change since V4:
- push and pop r5 too
- bl to handler instead of b

 README                       |    1 +
 arch/arm/cpu/armv7/cp15.c    |    6 ++++++
 arch/arm/cpu/armv7/start.S   |   13 +++++++++++++
 arch/arm/include/asm/armv7.h |    2 ++
 4 files changed, 22 insertions(+)
README +1 -0
index 9a0106066b1c..259dbdbd2075 100644
@@ -693,6 +693,7 @@ The following options need to be configured:
 		NOTE: The following can be machine specific errata. These
 		do have ability to provide rudimentary version and machine
 		specific checks, but expect no product checks.
+		CONFIG_ARM_ERRATA_454179
 		CONFIG_ARM_ERRATA_798870
 
 - Driver Model
arch/arm/cpu/armv7/cp15.c +6 -0
index 8ac81c9ba147..b44c9f94a822 100644
@@ -21,3 +21,9 @@ void __weak v7_arch_cp15_set_l2aux_ctrl(u32 l2actlr, u32 cpu_midr,
 {
 	asm volatile ("mcr p15, 1, %0, c15, c0, 0\n\t" : : "r"(l2actlr));
 }
+
+void __weak v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
+				 u32 cpu_variant, u32 cpu_rev)
+{
+	asm volatile ("mcr p15, 0, %0, c1, c0, 1\n\t" : : "r"(acr));
+}
arch/arm/cpu/armv7/start.S +13 -0
index 89637e26395d..06943dc07082 100644
@@ -189,6 +189,19 @@ ENTRY(cpu_init_cp15)
 skip_errata_798870:
 #endif
 
+#ifdef CONFIG_ARM_ERRATA_454179
+	cmp	r2, #0x21		@ Only on < r2p1
+	bge	skip_errata_454179
+
+	mrc	p15, 0, r0, c1, c0, 1	@ Read ACR
+	orr	r0, r0, #(0x3 << 6)	@ Set DBSM(BIT7) and IBE(BIT6) bits
+	push	{r1-r5}			@ Save the cpu info registers
+	bl	v7_arch_cp15_set_acr
+	pop	{r1-r5}			@ Restore the cpu info - fall through
+
+skip_errata_454179:
+#endif
+
 	mov	pc, r5			@ back to my caller
 ENDPROC(cpu_init_cp15)
arch/arm/include/asm/armv7.h +2 -0
index 69abc4791ae5..e9a00e20002c 100644
@@ -141,6 +141,8 @@ extern char __secure_end[];
 void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
 				 u32 cpu_rev_comb, u32 cpu_variant,
 				 u32 cpu_rev);
+void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
+			  u32 cpu_variant, u32 cpu_rev);
 #endif /* ! __ASSEMBLY__ */
 
 #endif
Signature · 1 line
1.7.9.5
author
#3 lore raw

PATCH v5 3/11 ARM: Introduce erratum workaround for 430973

In reply to Nishanth Menon

430973: Stale prediction on replaced inter working branch causes
Cortex-A8 to execute in the wrong ARM/Thumb state
Impacts: Every Cortex-A8 processors with revision lower than r2p1 Work around: Set IBE to 1

Based on ARM errata Document revision 20.0 (13 Nov 2010)

Signed-off-by Nishanth Menon <[email protected]>

---
Change since V4:
- push and pop r5 too
- bl to handler instead of b

 README                     |    1 +
 arch/arm/cpu/armv7/start.S |   13 +++++++++++++
 2 files changed, 14 insertions(+)
README +1 -0
index 259dbdbd2075..82f7e10c71d6 100644
@@ -693,6 +693,7 @@ The following options need to be configured:
 		NOTE: The following can be machine specific errata. These
 		do have ability to provide rudimentary version and machine
 		specific checks, but expect no product checks.
+		CONFIG_ARM_ERRATA_430973
 		CONFIG_ARM_ERRATA_454179
 		CONFIG_ARM_ERRATA_798870
arch/arm/cpu/armv7/start.S +13 -0
index 06943dc07082..a5739f392bca 100644
@@ -202,6 +202,19 @@ skip_errata_798870:
 skip_errata_454179:
 #endif
 
+#ifdef CONFIG_ARM_ERRATA_430973
+	cmp	r2, #0x21		@ Only on < r2p1
+	bge	skip_errata_430973
+
+	mrc	p15, 0, r0, c1, c0, 1	@ Read ACR
+	orr	r0, r0, #(0x1 << 6)	@ Set IBE bit
+	push	{r1-r5}			@ Save the cpu info registers
+	bl	v7_arch_cp15_set_acr
+	pop	{r1-r5}			@ Restore the cpu info - fall through
+
+skip_errata_430973:
+#endif
+
 	mov	pc, r5			@ back to my caller
 ENDPROC(cpu_init_cp15)
Signature · 1 line
1.7.9.5
author
#4 lore raw

PATCH v5 4/11 ARM: Introduce erratum workaround for 621766

In reply to Nishanth Menon

621766: Under a specific set of conditions, executing a sequence of
NEON or vfp load instructions can cause processor deadlock
Impacts: Every Cortex-A8 processors with revision lower than r2p1 Work around: Set L1NEON to 1

Based on ARM errata Document revision 20.0 (13 Nov 2010)

Signed-off-by Nishanth Menon <[email protected]>

---
Change since V4:
- push and pop r5 too
- bl to handler instead of b

 README                     |    1 +
 arch/arm/cpu/armv7/start.S |   13 +++++++++++++
 2 files changed, 14 insertions(+)
README +1 -0
index 82f7e10c71d6..e7e90a08145e 100644
@@ -695,6 +695,7 @@ The following options need to be configured:
 		specific checks, but expect no product checks.
 		CONFIG_ARM_ERRATA_430973
 		CONFIG_ARM_ERRATA_454179
+		CONFIG_ARM_ERRATA_621766
 		CONFIG_ARM_ERRATA_798870
 
 - Driver Model
arch/arm/cpu/armv7/start.S +13 -0
index a5739f392bca..9b8d3cf2595a 100644
@@ -215,6 +215,19 @@ skip_errata_454179:
 skip_errata_430973:
 #endif
 
+#ifdef CONFIG_ARM_ERRATA_621766
+	cmp	r2, #0x21		@ Only on < r2p1
+	bge	skip_errata_621766
+
+	mrc	p15, 0, r0, c1, c0, 1	@ Read ACR
+	orr	r0, r0, #(0x1 << 5)	@ Set L1NEON bit
+	push	{r1-r5}			@ Save the cpu info registers
+	bl	v7_arch_cp15_set_acr
+	pop	{r1-r5}			@ Restore the cpu info - fall through
+
+skip_errata_621766:
+#endif
+
 	mov	pc, r5			@ back to my caller
 ENDPROC(cpu_init_cp15)
Signature · 1 line
1.7.9.5
author
#5 lore raw

PATCH v5 5/11 ARM: OMAP: Change set_pl310_ctrl_reg to be generic

In reply to Nishanth Menon

set_pl310_ctrl_reg does use the Secure Monitor Call (SMC) to setup PL310 control register, however, that is something that is generic enough to be used for OMAP5 generation of processors as well. The only difference being the service being invoked for the function.

So, convert the service to a macro and use a generic name (same as that used in Linux for some consistency). While at that, also add a data barrier which is necessary as per recommendation.

While at this, smc #0 is maintained as handcoded assembly thanks to various gcc version eccentricities, discussion thread:
http://marc.info/?t=142542166800001&r=1&w=2

Signed-off-by Nishanth Menon <[email protected]>

---
change since V4:
- back to handcoding smc #0

 arch/arm/cpu/armv7/omap-common/lowlevel_init.S |   18 +++++++++++-------
 arch/arm/cpu/armv7/omap4/hwinit.c              |    4 ++--
 arch/arm/include/asm/arch-omap4/sys_proto.h    |    5 ++++-
 3 files changed, 17 insertions(+), 10 deletions(-)
arch/arm/cpu/armv7/omap-common/lowlevel_init.S +11 -7
index e19c7aececdd..80619b04df5d 100644
@@ -22,11 +22,15 @@ ENTRY(save_boot_params)
 	b	save_boot_params_ret
 ENDPROC(save_boot_params)
 
-ENTRY(set_pl310_ctrl_reg)
-	PUSH	{r4-r11, lr}	@ save registers - ROM code may pollute
+ENTRY(omap_smc1)
+	PUSH	{r4-r12, lr}	@ save registers - ROM code may pollute
 				@ our registers
-	LDR	r12, =0x102	@ Set PL310 control register - value in R0
-	.word	0xe1600070	@ SMC #0 - hand assembled because -march=armv5
-				@ call ROM Code API to set control register
-	POP	{r4-r11, pc}
-ENDPROC(set_pl310_ctrl_reg)
+	MOV	r12, r0		@ Service
+	MOV	r0, r1		@ Argument
+	DSB
+	DMB
+	.word	0xe1600070	@ SMC #0 - hand assembled for GCC versions
+				@ call ROM Code API for the service requested
+
+	POP	{r4-r12, pc}
+ENDPROC(omap_smc1)
arch/arm/cpu/armv7/omap4/hwinit.c +2 -2
index db16548fac49..9792761d40a0 100644
@@ -159,11 +159,11 @@ void init_omap_revision(void)
 #ifndef CONFIG_SYS_L2CACHE_OFF
 void v7_outer_cache_enable(void)
 {
-	set_pl310_ctrl_reg(1);
+	omap_smc1(OMAP4_SERVICE_PL310_CONTROL_REG_SET, 1);
 }
 
 void v7_outer_cache_disable(void)
 {
-	set_pl310_ctrl_reg(0);
+	omap_smc1(OMAP4_SERVICE_PL310_CONTROL_REG_SET, 0);
 }
 #endif /* !CONFIG_SYS_L2CACHE_OFF */
arch/arm/include/asm/arch-omap4/sys_proto.h +4 -1
index e19975efaf50..f425e3af54f5 100644
@@ -37,7 +37,7 @@ void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
 void set_muxconf_regs_essential(void);
 u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
-void set_pl310_ctrl_reg(u32 val);
+void omap_smc1(u32 service, u32 val);
 void setup_clocks_for_console(void);
 void prcm_init(void);
 void bypass_dpll(u32 const base);

@@ -57,4 +57,7 @@ int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
 u32 warm_reset(void);
 void force_emif_self_refresh(void);
 void setup_warmreset_time(void);
+
+#define OMAP4_SERVICE_PL310_CONTROL_REG_SET	0x102
+
 #endif
Signature · 1 line
1.7.9.5
#6 lore raw

PATCH v5 5/11 ARM: OMAP: Change set_pl310_ctrl_reg to be generic

Quoted 14 lines · Nishanth Menon

set_pl310_ctrl_reg does use the Secure Monitor Call (SMC) to setup PL310 control register, however, that is something that is generic enough to be used for OMAP5 generation of processors as well. The only difference being the service being invoked for the function.

So, convert the service to a macro and use a generic name (same as that used in Linux for some consistency). While at that, also add a data barrier which is necessary as per recommendation.

While at this, smc #0 is maintained as handcoded assembly thanks to various gcc version eccentricities, discussion thread:
http://marc.info/?t=142542166800001&r=1&w=2

Signed-off-by Nishanth Menon <[email protected]>

[snip]

Quoted 11 lines
arch/arm/cpu/armv7/omap-common/lowlevel_init.S +1 -2
index e19c7aececdd..80619b04df5d 100644
@@ -22,11 +22,15 @@ ENTRY(save_boot_params)
 	b	save_boot_params_ret
 ENDPROC(save_boot_params)
 
-ENTRY(set_pl310_ctrl_reg)
-	PUSH	{r4-r11, lr}	@ save registers - ROM code may pollute
+ENTRY(omap_smc1)

[snip]

arch/arm/include/asm/arch-omap4/sys_proto.h void do_set_mux(u32 base, struct pad_conf_entry const *array, int size); · line 40

Quoted 10 lines
arch/arm/include/asm/arch-omap4/sys_proto.h +1 -1
index e19975efaf50..f425e3af54f5 100644
@@ -37,7 +37,7 @@ void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
 void set_muxconf_regs_essential(void);
 u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
-void set_pl310_ctrl_reg(u32 val);
+void omap_smc1(u32 service, u32 val);

I kinda feel we should be putting the prototype into omap_common.h as that's as close as we've got today for a header that matches up to the code in arch/arm/cpu/armv7/omap-common/, thanks!

Signature · 8 lines
Tom
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author
#7 lore raw

PATCH v5 5/11 ARM: OMAP: Change set_pl310_ctrl_reg to be generic

Quoted 29 lines · Tom Rini
Quoted 14 lines · Nishanth Menon

set_pl310_ctrl_reg does use the Secure Monitor Call (SMC) to setup PL310 control register, however, that is something that is generic enough to be used for OMAP5 generation of processors as well. The only difference being the service being invoked for the function.

So, convert the service to a macro and use a generic name (same as that used in Linux for some consistency). While at that, also add a data barrier which is necessary as per recommendation.

While at this, smc #0 is maintained as handcoded assembly thanks to various gcc version eccentricities, discussion thread:
http://marc.info/?t=142542166800001&r=1&w=2

Signed-off-by Nishanth Menon <[email protected]>

[snip]

Quoted 11 lines
arch/arm/cpu/armv7/omap-common/lowlevel_init.S +1 -2
index e19c7aececdd..80619b04df5d 100644
@@ -22,11 +22,15 @@ ENTRY(save_boot_params)
 	b	save_boot_params_ret
 ENDPROC(save_boot_params)
 
-ENTRY(set_pl310_ctrl_reg)
-	PUSH	{r4-r11, lr}	@ save registers - ROM code may pollute
+ENTRY(omap_smc1)

[snip]

Quoted 15 lines

arch/arm/include/asm/arch-omap4/sys_proto.h void do_set_mux(u32 base, struct pad_conf_entry const *array, int size); · line 40

Quoted 10 lines
arch/arm/include/asm/arch-omap4/sys_proto.h +1 -1
index e19975efaf50..f425e3af54f5 100644
@@ -37,7 +37,7 @@ void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
 void set_muxconf_regs_essential(void);
 u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
-void set_pl310_ctrl_reg(u32 val);
+void omap_smc1(u32 service, u32 val);

I kinda feel we should be putting the prototype into omap_common.h as that's as close as we've got today for a header that matches up to the code in arch/arm/cpu/armv7/omap-common/, thanks!

OK. will try to get it done. Thanks for the suggestion on this.

Signature · 2 lines
Regards,
Nishanth Menon
author
#8 lore raw

PATCH v5 6/11 ARM: OMAP3: Rename omap3.h to omap.h to be generic as all SoCs

In reply to Nishanth Menon

This is in preperation of using generic cross OMAP code.

Signed-off-by Nishanth Menon <[email protected]>
---
 .../arm/include/asm/arch-omap3/{omap3.h => omap.h} |    0
 include/configs/am3517_crane.h                     |    2 +-
 include/configs/am3517_evm.h                       |    2 +-
 include/configs/cm_t35.h                           |    2 +-
 include/configs/cm_t3517.h                         |    2 +-
 include/configs/dig297.h                           |    2 +-
 include/configs/mcx.h                              |    2 +-
 include/configs/nokia_rx51.h                       |    2 +-
 include/configs/omap3_evm.h                        |    2 +-
 include/configs/omap3_evm_quick_mmc.h              |    2 +-
 include/configs/omap3_evm_quick_nand.h             |    2 +-
 include/configs/omap3_logic.h                      |    2 +-
 include/configs/omap3_mvblx.h                      |    2 +-
 include/configs/omap3_pandora.h                    |    2 +-
 include/configs/omap3_sdp3430.h                    |    2 +-
 include/configs/omap3_zoom1.h                      |    2 +-
 include/configs/tam3517-common.h                   |    2 +-
 include/configs/tao3530.h                          |    2 +-
 include/configs/ti_omap3_common.h                  |    2 +-
 include/configs/tricorder.h                        |    2 +-
 20 files changed, 19 insertions(+), 19 deletions(-)
 rename arch/arm/include/asm/arch-omap3/{omap3.h => omap.h} (100%)
arch/arm/include/asm/arch-omap3/omap.h renamed from arch/arm/include/asm/arch-omap3/omap3.h +0 -0
similarity index 100%
rename from arch/arm/include/asm/arch-omap3/omap3.h
rename to arch/arm/include/asm/arch-omap3/omap.h
include/configs/am3517_crane.h +1 -1
index 290a6a3e0640..87c850e05df1 100644
@@ -23,7 +23,7 @@
 #define CONFIG_EMIF4	/* The chip has EMIF4 controller */
 
 #include <asm/arch/cpu.h>		/* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
 
 /*
  * Display CPU and Board information
include/configs/am3517_evm.h +1 -1
index 3de50799621e..c4e19e79b95a 100644
@@ -23,7 +23,7 @@
 #define CONFIG_EMIF4	/* The chip has EMIF4 controller */
 
 #include <asm/arch/cpu.h>		/* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
 
 /*
  * Display CPU and Board information
include/configs/cm_t35.h +1 -1
index 9feca1b47b38..e2d5bbb0955d 100644
@@ -30,7 +30,7 @@
 #define CONFIG_SDRC	/* The chip has SDRC controller */
 
 #include <asm/arch/cpu.h>		/* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
 
 /*
  * Display CPU and Board information
include/configs/cm_t3517.h +1 -1
index 918032bd753a..ee1b7a0cb5a7 100644
@@ -30,7 +30,7 @@
 #define CONFIG_EMIF4	/* The chip has EMIF4 controller */
 
 #include <asm/arch/cpu.h>		/* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
 
 /*
  * Display CPU and Board information
include/configs/dig297.h +1 -1
index c8739ed29490..8791199fc61d 100644
@@ -36,7 +36,7 @@
 #define CONFIG_SDRC	/* The chip has SDRC controller */
 
 #include <asm/arch/cpu.h>		/* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
 
 /*
  * Display CPU and Board information
include/configs/mcx.h +1 -1
index 26eb2203540f..2cf66c40d6fe 100644
@@ -26,7 +26,7 @@
 #define CONFIG_EMIF4	/* The chip has EMIF4 controller */
 
 #include <asm/arch/cpu.h>		/* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
 
 #define CONFIG_OF_LIBFDT
 #define CONFIG_FIT
include/configs/nokia_rx51.h +1 -1
index 46fc91e5e197..442e16ae686b 100644
@@ -42,7 +42,7 @@
 #define CONFIG_SDRC			/* The chip has SDRC controller */
 
 #include <asm/arch/cpu.h>		/* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
 #include <asm/arch/mem.h>
 #include <linux/stringify.h>
include/configs/omap3_evm.h +1 -1
index 8bdc08f5864c..4e587e10ffd3 100644
@@ -18,7 +18,7 @@
 #define __OMAP3EVM_CONFIG_H
 
 #include <asm/arch/cpu.h>
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
 
 /* ----------------------------------------------------------------------------
  * Supported U-boot commands
include/configs/omap3_evm_quick_mmc.h +1 -1
index 1185f425501f..a7acc1becbeb 100644
@@ -13,7 +13,7 @@
 #define __OMAP3_EVM_QUICK_MMC_H
 
 #include <asm/arch/cpu.h>
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
 
 /* ----------------------------------------------------------------------------
  * Supported U-boot commands
include/configs/omap3_evm_quick_nand.h +1 -1
index 4427e88b7e4b..c6cad9388961 100644
@@ -13,7 +13,7 @@
 #define __OMAP3_EVM_QUICK_NAND_H
 
 #include <asm/arch/cpu.h>
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
 
 /* ----------------------------------------------------------------------------
  * Supported U-boot commands
include/configs/omap3_logic.h +1 -1
index aeb385f5ff6b..fcef46735835 100644
@@ -24,7 +24,7 @@
 #define CONFIG_SDRC	/* The chip has SDRC controller */
 
 #include <asm/arch/cpu.h>	/* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
 
 /*
  * Display CPU and Board information
include/configs/omap3_mvblx.h +1 -1
index bf1d34dedb4d..20ec3ad15439 100644
@@ -27,7 +27,7 @@
 #define CONFIG_SDRC	/* The chip has SDRC controller */
 
 #include <asm/arch/cpu.h>		/* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
 
 /*
  * Display CPU and Board information
include/configs/omap3_pandora.h +1 -1
index 45feeb577320..b92d67abccf9 100644
@@ -21,7 +21,7 @@
 #define CONFIG_SDRC	/* The chip has SDRC controller */
 
 #include <asm/arch/cpu.h>	/* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
 
 /*
  * Display CPU and Board information
include/configs/omap3_sdp3430.h +1 -1
index ac307eb45629..bf5c7a8faf77 100644
@@ -27,7 +27,7 @@
 #define CONFIG_SDRC	/* The chip has SDRC controller */
 
 #include <asm/arch/cpu.h>		/* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
 
 /*
  * NOTE:  these #defines presume standard SDP jumper settings.
include/configs/omap3_zoom1.h +1 -1
index c5d742c2bd80..611cd5e1a350 100644
@@ -22,7 +22,7 @@
 #define CONFIG_NAND
 #define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
 #include <asm/arch/cpu.h>		/* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
 #include <configs/ti_omap3_common.h>
 
 /* Remove SPL boot option - we do not support that on LDP yet */
include/configs/tam3517-common.h +1 -1
index 38288f69aaa5..dea4044d9fbb 100644
@@ -25,7 +25,7 @@
 #define CONFIG_EMIF4	/* The chip has EMIF4 controller */
 
 #include <asm/arch/cpu.h>		/* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
 
 /*
  * Display CPU and Board information
include/configs/tao3530.h +1 -1
index dd69d4ebabfe..f3e0088d5a00 100644
@@ -27,7 +27,7 @@
 #define CONFIG_SDRC			/* Has an SDRC controller */
 
 #include <asm/arch/cpu.h>		/* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
 
 /*
  * Display CPU and Board information
include/configs/ti_omap3_common.h +1 -1
index 840e108e0536..4b4f10410543 100644
@@ -16,7 +16,7 @@
 
 
 #include <asm/arch/cpu.h>
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
 
 #ifndef CONFIG_SPL_BUILD
 # define CONFIG_OMAP_SERIAL
include/configs/tricorder.h +1 -1
index 10ac4a46bc4a..b105ffd9f18b 100644
@@ -32,7 +32,7 @@
 #define CONFIG_SDRC			/* The chip has SDRC controller */
 
 #include <asm/arch/cpu.h>		/* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
 
 #define CONFIG_SYS_GENERIC_BOARD
Signature · 1 line
1.7.9.5
author
#9 lore raw

PATCH v5 7/11 ARM: OMAP3: Get rid of omap3_gp_romcode_call and replace with omap_smc1

In reply to Nishanth Menon

omap_smc1 is now generic enough to remove duplicate omap3_gp_romcode_call logic that omap3 introduced.

As part of this change, move to using the generic lowlevel_init.S for omap3 as well.

Signed-off-by Nishanth Menon <[email protected]>
---
 arch/arm/cpu/armv7/omap-common/Makefile        |    2 +-
 arch/arm/cpu/armv7/omap-common/lowlevel_init.S |    2 ++
 arch/arm/cpu/armv7/omap3/board.c               |    6 ++----
 arch/arm/cpu/armv7/omap3/lowlevel_init.S       |   11 -----------
 arch/arm/include/asm/arch-omap3/sys_proto.h    |    2 +-
 5 files changed, 6 insertions(+), 17 deletions(-)
arch/arm/cpu/armv7/omap-common/Makefile +1 -1
index 7695e16d36f5..f3725b267c99 100644
@@ -28,7 +28,7 @@ endif
 
 ifeq ($(CONFIG_OMAP34XX),)
 obj-y	+= boot-common.o
-obj-y	+= lowlevel_init.o
 endif
+obj-y	+= lowlevel_init.o
 
 obj-y	+= mem-common.o
arch/arm/cpu/armv7/omap-common/lowlevel_init.S +2 -0
index 80619b04df5d..746df922c27d 100644
@@ -16,11 +16,13 @@
 #include <asm/arch/spl.h>
 #include <linux/linkage.h>
 
+#ifndef CONFIG_OMAP34XX
 ENTRY(save_boot_params)
 	ldr	r1, =OMAP_SRAM_SCRATCH_BOOT_PARAMS
 	str	r0, [r1]
 	b	save_boot_params_ret
 ENDPROC(save_boot_params)
+#endif
 
 ENTRY(omap_smc1)
 	PUSH	{r4-r12, lr}	@ save registers - ROM code may pollute
arch/arm/cpu/armv7/omap3/board.c +2 -4
index 347947c4b354..ba30ab78e007 100644
@@ -420,8 +420,7 @@ static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits)
 	acr |= set_bits;
 
 	if (get_device_type() == GP_DEVICE) {
-		omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_WRITE_ACR,
-				       acr);
+		omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_ACR, acr);
 	} else {
 		struct emu_hal_params emu_romcode_params;
 		emu_romcode_params.num_params = 1;

@@ -461,8 +460,7 @@ static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
 static void omap3_invalidate_l2_cache_secure(void)
 {
 	if (get_device_type() == GP_DEVICE) {
-		omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_L2_INVAL,
-				      0);
+		omap_smc1(OMAP3_GP_ROMCODE_API_L2_INVAL, 0);
 	} else {
 		struct emu_hal_params emu_romcode_params;
 		emu_romcode_params.num_params = 1;
arch/arm/cpu/armv7/omap3/lowlevel_init.S +0 -11
index 80cb2639f60c..7a691519bb6b 100644
@@ -27,17 +27,6 @@ ENTRY(save_boot_params)
 ENDPROC(save_boot_params)
 #endif
 
-ENTRY(omap3_gp_romcode_call)
-	PUSH {r4-r12, lr} @ Save all registers from ROM code!
-	MOV r12, r0	@ Copy the Service ID in R12
-	MOV r0, r1	@ Copy parameter to R0
-	mcr     p15, 0, r0, c7, c10, 4	@ DSB
-	mcr     p15, 0, r0, c7, c10, 5	@ DMB
-	.word	0xe1600070	@ SMC #0 to enter monitor - hand assembled
-				@ because we use -march=armv5
-	POP {r4-r12, pc}
-ENDPROC(omap3_gp_romcode_call)
-
 /*
  * Funtion for making PPA HAL API calls in secure devices
  * Input:
arch/arm/include/asm/arch-omap3/sys_proto.h +1 -1
index bcf92fbe658b..c06605d533d3 100644
@@ -73,6 +73,6 @@ void power_init_r(void);
 void dieid_num_r(void);
 void get_dieid(u32 *id);
 void do_omap3_emu_romcode_call(u32 service_id, u32 parameters);
-void omap3_gp_romcode_call(u32 service_id, u32 parameter);
+void omap_smc1(u32 service, u32 val);
 u32 warm_reset(void);
 #endif
Signature · 1 line
1.7.9.5
author
#10 lore raw

PATCH v5 8/11 ARM: DRA7 / OMAP5: Add workaround for ARM errata 798870

In reply to Nishanth Menon

From: Praveen Rao <[email protected]>

This patch enables the workaround for ARM errata 798870 for OMAP5 / DRA7 which says "If back-to-back speculative cache line fills (fill A and fill B) are issued from the L1 data cache of a CPU to the L2 cache, the second request (fill B) is then cancelled, and the second request would have detected a hazard against a recent write or eviction (write B) to the same cache line as fill B then the L2 logic might deadlock."

An l2auxctlr accessor implementation for OMAP5 and DRA7 is introduced here as well.

Signed-off-by Praveen Rao <[email protected]>
Signed-off-by Angela Stegmaier <[email protected]>
Signed-off-by Nishanth Menon <[email protected]>
---
 arch/arm/cpu/armv7/omap5/hwinit.c           |    7 +++++++
 arch/arm/include/asm/arch-omap5/sys_proto.h |    4 ++++
 include/configs/ti_omap5_common.h           |    3 +++
 3 files changed, 14 insertions(+)
arch/arm/cpu/armv7/omap5/hwinit.c +7 -0
index a8a474a88be9..f8060555b680 100644
@@ -381,3 +381,10 @@ void setup_warmreset_time(void)
 	rst_val |= rst_time;
 	writel(rst_val, (*prcm)->prm_rsttime);
 }
+
+void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
+				 u32 cpu_rev_comb, u32 cpu_variant,
+				 u32 cpu_rev)
+{
+	omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2auxctrl);
+}
arch/arm/include/asm/arch-omap5/sys_proto.h +4 -0
index 103830319a41..37dc9925eae2 100644
@@ -66,4 +66,8 @@ static inline u32 usec_to_32k(u32 usec)
 {
 	return div_round_up(32768 * usec, 1000000);
 }
+
+void omap_smc1(u32 service, u32 val);
+#define OMAP5_SERVICE_L2ACTLR_SET    0x104
+
 #endif
include/configs/ti_omap5_common.h +3 -0
index 925cb42dd38d..09f05f18a75d 100644
@@ -21,6 +21,9 @@
 #define CONFIG_DISPLAY_BOARDINFO
 #define CONFIG_ARCH_CPU_INIT
 
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_798870
+
 #define CONFIG_SYS_CACHELINE_SIZE	64
 
 /* Use General purpose timer 1 */
Signature · 1 line
1.7.9.5
author
#11 lore raw

PATCH v5 9/11 ARM: OMAP5 / DRA7: Setup L2 Aux Control Register with recommended configuration

In reply to Nishanth Menon

Update to existing recommendation for L2ACTLR configuration to prevent system instability and optimize performance.

These apply to both OMAP5 and DRA7.

Reported-by Vivek Chengalvala <[email protected]>
Signed-off-by Nishanth Menon <[email protected]>
---
 arch/arm/cpu/armv7/omap5/hwinit.c |   16 ++++++++++++++++
 1 file changed, 16 insertions(+)
arch/arm/cpu/armv7/omap5/hwinit.c +16 -0
index f8060555b680..8d6b59eeb044 100644
@@ -304,6 +304,21 @@ void config_data_eye_leveling_samples(u32 emif_base)
 		       (*ctrl)->control_emif2_sdram_config_ext);
 }
 
+void init_cpu_configuration(void)
+{
+	u32 l2actlr;
+
+	asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r"(l2actlr));
+	/*
+	 * L2ACTLR: Ensure to enable the following:
+	 * 3: Disable clean/evict push to external
+	 * 4: Disable WriteUnique and WriteLineUnique transactions from master
+	 * 8: Disable DVM/CMO message broadcast
+	 */
+	l2actlr |= 0x118;
+	omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2actlr);
+}
+
 void init_omap_revision(void)
 {
 	/*

@@ -342,6 +357,7 @@ void init_omap_revision(void)
 	default:
 		*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
 	}
+	init_cpu_configuration();
 }
 
 void reset_cpu(ulong ignored)
Signature · 1 line
1.7.9.5

A message that is not in the archive (sent off-list or not yet received): 20150306170553.GB17895@bill-the-cat

author
#13 lore raw

PATCH v5 9/11 ARM: OMAP5 / DRA7: Setup L2 Aux Control Register with recommended configuration

Quoted 33 lines · Tom Rini
Quoted 31 lines · Nishanth Menon

Update to existing recommendation for L2ACTLR configuration to prevent system instability and optimize performance.

These apply to both OMAP5 and DRA7.

Reported-by Vivek Chengalvala <[email protected]>
Signed-off-by Nishanth Menon <[email protected]>
---
 arch/arm/cpu/armv7/omap5/hwinit.c |   16 ++++++++++++++++
 1 file changed, 16 insertions(+)
arch/arm/cpu/armv7/omap5/hwinit.c +12 -0
index f8060555b680..8d6b59eeb044 100644
@@ -304,6 +304,21 @@ void config_data_eye_leveling_samples(u32 emif_base)
 		       (*ctrl)->control_emif2_sdram_config_ext);
 }
 
+void init_cpu_configuration(void)
+{
+	u32 l2actlr;
+
+	asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r"(l2actlr));
+	/*
+	 * L2ACTLR: Ensure to enable the following:
+	 * 3: Disable clean/evict push to external
+	 * 4: Disable WriteUnique and WriteLineUnique transactions from master
+	 * 8: Disable DVM/CMO message broadcast
+	 */
+	l2actlr |= 0x118;
Quoted 9 lines

arch/arm/cpu/armv7/omap5/hwinit.c void config_data_eye_leveling_samples(u32 emif_base) · line 321

Quoted 3 lines
arch/arm/cpu/armv7/omap5/hwinit.c +3 -0
+	omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2actlr);
+}
+

The function should at least be marked as static. I don't see a better place for this since we want these bits set sooner rather than later so board_late_init or whatever is probably not super awesome as there's probably some corner case where we'll get bit, right?

yeah - i did consider late_init, then realized that folks might want to turn on l2 cache, just like they did on cortex-a8 beagle, which'd mean l2actlr modifications(if done in late_init) with cache on is not really a good idea, instead stuck with init of omap revision - which is as early as I could get for a logical place on SoC code.

Signature · 2 lines
Regards,
Nishanth Menon
author
#14 lore raw

PATCH v5 10/11 ARM: OMAP3: Enable workaround for ARM errata 454179, 430973, 621766

In reply to Nishanth Menon

Enable the OMAP3 specific errata code for 454179, 430973, 621766 and while at it, remove legacy non-revision checked errata logic.

Signed-off-by Nishanth Menon <[email protected]>
---
 arch/arm/cpu/armv7/omap3/board.c   |   31 ++++++++++---------------------
 include/configs/am3517_crane.h     |    4 ++++
 include/configs/am3517_evm.h       |    4 ++++
 include/configs/cm_t35.h           |    4 ++++
 include/configs/cm_t3517.h         |    4 ++++
 include/configs/dig297.h           |    4 ++++
 include/configs/mcx.h              |    4 ++++
 include/configs/omap3_evm_common.h |    4 ++++
 include/configs/omap3_logic.h      |    4 ++++
 include/configs/omap3_mvblx.h      |    4 ++++
 include/configs/omap3_pandora.h    |    4 ++++
 include/configs/omap3_sdp3430.h    |    4 ++++
 include/configs/tam3517-common.h   |    4 ++++
 include/configs/tao3530.h          |    4 ++++
 include/configs/ti_omap3_common.h  |    5 +++++
 include/configs/tricorder.h        |    4 ++++
 16 files changed, 71 insertions(+), 21 deletions(-)
arch/arm/cpu/armv7/omap3/board.c +10 -21
index ba30ab78e007..1daac9b0c36c 100644
@@ -35,7 +35,6 @@ DECLARE_GLOBAL_DATA_PTR;
 
 /* Declarations */
 extern omap3_sysinfo sysinfo;
-static void omap3_setup_aux_cr(void);
 #ifndef CONFIG_SYS_L2CACHE_OFF
 static void omap3_invalidate_l2_cache_secure(void);
 #endif

@@ -244,9 +243,6 @@ void s_init(void)
 
 	try_unlock_memory();
 
-	/* Errata workarounds */
-	omap3_setup_aux_cr();
-
 #ifndef CONFIG_SYS_L2CACHE_OFF
 	/* Invalidate L2-cache from secure mode */
 	omap3_invalidate_l2_cache_secure();

@@ -410,15 +406,9 @@ static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
 	do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
 }
 
-static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits)
+void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
+			  u32 cpu_variant, u32 cpu_rev)
 {
-	u32 acr;
-
-	/* Read ACR */
-	asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
-	acr &= ~clear_bits;
-	acr |= set_bits;
-
 	if (get_device_type() == GP_DEVICE) {
 		omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_ACR, acr);
 	} else {

@@ -430,16 +420,15 @@ static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits)
 	}
 }
 
-static void omap3_setup_aux_cr(void)
+static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits)
 {
-	/* Workaround for Cortex-A8 errata: #454179 #430973
-	 *	Set "IBE" bit
-	 *	Set "Disable Branch Size Mispredicts" bit
-	 * Workaround for erratum #621766
-	 *	Enable L1NEON bit
-	 * ACR |= (IBE | DBSM | L1NEON) => ACR |= 0xE0
-	 */
-	omap3_update_aux_cr_secure(0xE0, 0);
+	u32 acr;
+
+	/* Read ACR */
+	asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
+	acr &= ~clear_bits;
+	acr |= set_bits;
+	v7_arch_cp15_set_acr(acr, 0, 0, 0, 0);
 }
 
 #ifndef CONFIG_SYS_L2CACHE_OFF
include/configs/am3517_crane.h +4 -0
index 87c850e05df1..c3c9169d0555 100644
@@ -19,6 +19,10 @@
 #define CONFIG_OMAP		1	/* in a TI OMAP core */
 #define CONFIG_OMAP3_AM3517CRANE	1	/* working with CRANEBOARD */
 #define CONFIG_OMAP_COMMON
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_454179
+#define CONFIG_ARM_ERRATA_430973
+#define CONFIG_ARM_ERRATA_621766
 
 #define CONFIG_EMIF4	/* The chip has EMIF4 controller */
include/configs/am3517_evm.h +4 -0
index c4e19e79b95a..31e758d81bdd 100644
@@ -19,6 +19,10 @@
 #define CONFIG_OMAP		1	/* in a TI OMAP core */
 #define CONFIG_OMAP3_AM3517EVM	1	/* working with AM3517EVM */
 #define CONFIG_OMAP_COMMON
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_454179
+#define CONFIG_ARM_ERRATA_430973
+#define CONFIG_ARM_ERRATA_621766
 
 #define CONFIG_EMIF4	/* The chip has EMIF4 controller */
include/configs/cm_t35.h +4 -0
index e2d5bbb0955d..3eb7886eb69e 100644
@@ -26,6 +26,10 @@
 #define CONFIG_CM_T3X	/* working with CM-T35 and CM-T3730 */
 #define CONFIG_OMAP_COMMON
 #define CONFIG_SYS_GENERIC_BOARD
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_454179
+#define CONFIG_ARM_ERRATA_430973
+#define CONFIG_ARM_ERRATA_621766
 
 #define CONFIG_SDRC	/* The chip has SDRC controller */
include/configs/cm_t3517.h +4 -0
index ee1b7a0cb5a7..8c6313832250 100644
@@ -17,6 +17,10 @@
 #define CONFIG_CM_T3517	/* working with CM-T3517 */
 #define CONFIG_OMAP_COMMON
 #define CONFIG_SYS_GENERIC_BOARD
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_454179
+#define CONFIG_ARM_ERRATA_430973
+#define CONFIG_ARM_ERRATA_621766
 
 #define CONFIG_SYS_TEXT_BASE	0x80008000
include/configs/dig297.h +4 -0
index 8791199fc61d..932640112b3a 100644
@@ -23,6 +23,10 @@
 #define MACH_TYPE_OMAP3_CPS 2751
 #endif
 #define CONFIG_MACH_TYPE MACH_TYPE_OMAP3_CPS
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_454179
+#define CONFIG_ARM_ERRATA_430973
+#define CONFIG_ARM_ERRATA_621766
 
 /*
  * High Level Configuration Options
include/configs/mcx.h +4 -0
index 2cf66c40d6fe..3fd31842451d 100644
@@ -16,6 +16,10 @@
 #define CONFIG_OMAP3_MCX		/* working with mcx */
 #define CONFIG_OMAP_GPIO
 #define CONFIG_OMAP_COMMON
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_454179
+#define CONFIG_ARM_ERRATA_430973
+#define CONFIG_ARM_ERRATA_621766
 
 #define MACH_TYPE_MCX			3656
 #define CONFIG_MACH_TYPE	MACH_TYPE_MCX
include/configs/omap3_evm_common.h +4 -0
index e7df15400d37..370f21e3ee6d 100644
@@ -15,6 +15,10 @@
 #define CONFIG_OMAP			/* This is TI OMAP core */
 #define CONFIG_OMAP_GPIO
 #define CONFIG_OMAP_COMMON
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_454179
+#define CONFIG_ARM_ERRATA_430973
+#define CONFIG_ARM_ERRATA_621766
 
 #define CONFIG_SDRC			/* The chip has SDRC controller */
include/configs/omap3_logic.h +4 -0
index fcef46735835..13cd35b16a03 100644
@@ -18,6 +18,10 @@
 #define CONFIG_OMAP3_LOGIC		/* working with Logic OMAP boards */
 #define CONFIG_OMAP_GPIO
 #define CONFIG_OMAP_COMMON
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_454179
+#define CONFIG_ARM_ERRATA_430973
+#define CONFIG_ARM_ERRATA_621766
 
 #define CONFIG_SYS_TEXT_BASE	0x80400000
include/configs/omap3_mvblx.h +4 -0
index 20ec3ad15439..b61297f9ee94 100644
@@ -23,6 +23,10 @@
 #define CONFIG_MACH_TYPE	MACH_TYPE_MVBLX
 #define CONFIG_OMAP_GPIO
 #define CONFIG_OMAP_COMMON
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_454179
+#define CONFIG_ARM_ERRATA_430973
+#define CONFIG_ARM_ERRATA_621766
 
 #define CONFIG_SDRC	/* The chip has SDRC controller */
include/configs/omap3_pandora.h +4 -0
index b92d67abccf9..11d7b86eb10d 100644
@@ -17,6 +17,10 @@
 #define CONFIG_OMAP3_PANDORA	1	/* working with pandora */
 #define CONFIG_OMAP_GPIO
 #define CONFIG_OMAP_COMMON
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_454179
+#define CONFIG_ARM_ERRATA_430973
+#define CONFIG_ARM_ERRATA_621766
 
 #define CONFIG_SDRC	/* The chip has SDRC controller */
include/configs/omap3_sdp3430.h +4 -0
index bf5c7a8faf77..1ca79d4ee4dd 100644
@@ -23,6 +23,10 @@
 #define CONFIG_OMAP		1	/* in a TI OMAP core */
 #define CONFIG_OMAP3_3430SDP	1	/* working with SDP Rev2 */
 #define CONFIG_OMAP_COMMON
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_454179
+#define CONFIG_ARM_ERRATA_430973
+#define CONFIG_ARM_ERRATA_621766
 
 #define CONFIG_SDRC	/* The chip has SDRC controller */
include/configs/tam3517-common.h +4 -0
index dea4044d9fbb..2d12e86566cd 100644
@@ -17,6 +17,10 @@
 #define CONFIG_OMAP_GPIO
 #define CONFIG_OMAP_COMMON
 #define CONFIG_SYS_GENERIC_BOARD
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_454179
+#define CONFIG_ARM_ERRATA_430973
+#define CONFIG_ARM_ERRATA_621766
 
 #define CONFIG_SYS_TEXT_BASE 0x80008000
include/configs/tao3530.h +4 -0
index f3e0088d5a00..49ed79ffbc0b 100644
@@ -21,6 +21,10 @@
 #define CONFIG_OMAP_GPIO
 #define CONFIG_OMAP_COMMON
 #define CONFIG_SYS_GENERIC_BOARD
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_454179
+#define CONFIG_ARM_ERRATA_430973
+#define CONFIG_ARM_ERRATA_621766
 
 #define MACH_TYPE_OMAP3_TAO3530		2836
include/configs/ti_omap3_common.h +5 -0
index 4b4f10410543..429b109afa23 100644
@@ -22,6 +22,11 @@
 # define CONFIG_OMAP_SERIAL
 #endif
 
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_454179
+#define CONFIG_ARM_ERRATA_430973
+#define CONFIG_ARM_ERRATA_621766
+
 /* The chip has SDRC controller */
 #define CONFIG_SDRC
include/configs/tricorder.h +4 -0
index b105ffd9f18b..7426bde8a0c2 100644
@@ -19,6 +19,10 @@
 /* High Level Configuration Options */
 #define CONFIG_OMAP			/* in a TI OMAP core */
 #define CONFIG_OMAP_COMMON
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_454179
+#define CONFIG_ARM_ERRATA_430973
+#define CONFIG_ARM_ERRATA_621766
 
 #define CONFIG_MACH_TYPE		MACH_TYPE_TRICORDER
 /*
Signature · 1 line
1.7.9.5
author
#15 lore raw

PATCH v5 11/11 ARM: OMAP3: rx51: Enable workaround for ARM errata 454179, 430973, 621766

In reply to Nishanth Menon

RX51 has a secure logic which uses different parameters compared to traditional implementation. So, make the generic secure acr write over-ride-able by board file and refactor rx51 code to use this.

While at it, enable the OMAP3 specific errata code for 454179, 430973, 621766.

Signed-off-by Nishanth Menon <[email protected]>
---
 arch/arm/cpu/armv7/omap3/board.c            |   45 ++++++++++++---------------
 arch/arm/include/asm/arch-omap3/sys_proto.h |    1 +
 board/nokia/rx51/rx51.c                     |   19 ++++++-----
 include/configs/nokia_rx51.h                |    4 +++
 4 files changed, 37 insertions(+), 32 deletions(-)
arch/arm/cpu/armv7/omap3/board.c +20 -25
index 1daac9b0c36c..c45c9a9f0154 100644
@@ -406,31 +406,30 @@ static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
 	do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
 }
 
-void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
-			  u32 cpu_variant, u32 cpu_rev)
+void __weak omap3_set_aux_cr_secure(u32 acr)
 {
-	if (get_device_type() == GP_DEVICE) {
-		omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_ACR, acr);
-	} else {
-		struct emu_hal_params emu_romcode_params;
-		emu_romcode_params.num_params = 1;
-		emu_romcode_params.param1 = acr;
-		omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
-				       (u32 *)&emu_romcode_params);
-	}
+	struct emu_hal_params emu_romcode_params;
+
+	emu_romcode_params.num_params = 1;
+	emu_romcode_params.param1 = acr;
+	omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
+			       (u32 *)&emu_romcode_params);
 }
 
-static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits)
+void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
+			  u32 cpu_variant, u32 cpu_rev)
 {
-	u32 acr;
+	/* Write ACR - affects secure banked bits */
+	if (get_device_type() == GP_DEVICE)
+		omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_ACR, acr);
+	else
+		omap3_set_aux_cr_secure(acr);
 
-	/* Read ACR */
-	asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
-	acr &= ~clear_bits;
-	acr |= set_bits;
-	v7_arch_cp15_set_acr(acr, 0, 0, 0, 0);
+	/* Write ACR - affects non-secure banked bits - some erratas need it */
+	asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
 }
 
+
 #ifndef CONFIG_SYS_L2CACHE_OFF
 static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
 {

@@ -440,9 +439,8 @@ static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
 	asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
 	acr &= ~clear_bits;
 	acr |= set_bits;
+	v7_arch_cp15_set_acr(acr, 0, 0, 0, 0);
 
-	/* Write ACR - affects non-secure banked bits */
-	asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
 }
 
 /* Invalidate the entire L2 cache from secure mode */

@@ -461,10 +459,9 @@ static void omap3_invalidate_l2_cache_secure(void)
 
 void v7_outer_cache_enable(void)
 {
-	/* Set L2EN */
-	omap3_update_aux_cr_secure(0x2, 0);
 
 	/*
+	 * Set L2EN
 	 * On some revisions L2EN bit is banked on some revisions it's not
 	 * No harm in setting both banked bits(in fact this is required
 	 * by an erratum)

@@ -474,10 +471,8 @@ void v7_outer_cache_enable(void)
 
 void omap3_outer_cache_disable(void)
 {
-	/* Clear L2EN */
-	omap3_update_aux_cr_secure(0, 0x2);
-
 	/*
+	 * Clear L2EN
 	 * On some revisions L2EN bit is banked on some revisions it's not
 	 * No harm in clearing both banked bits(in fact this is required
 	 * by an erratum)
arch/arm/include/asm/arch-omap3/sys_proto.h +1 -0
index c06605d533d3..ff1bf736cf06 100644
@@ -74,5 +74,6 @@ void dieid_num_r(void);
 void get_dieid(u32 *id);
 void do_omap3_emu_romcode_call(u32 service_id, u32 parameters);
 void omap_smc1(u32 service, u32 val);
+void omap3_set_aux_cr_secure(u32 acr);
 u32 warm_reset(void);
 #endif
board/nokia/rx51/rx51.c +12 -7
index 08fcaf21b3c6..3d019b01428b 100644
@@ -341,6 +341,17 @@ static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
 	do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
 }
 
+void omap3_set_aux_cr_secure(u32 acr)
+{
+	struct emu_hal_params_rx51 emu_romcode_params = { 0, };
+
+	emu_romcode_params.num_params = 2;
+	emu_romcode_params.param1 = acr;
+
+	omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
+			       (u32 *)&emu_romcode_params);
+}
+
 /*
  * Routine: omap3_update_aux_cr_secure_rx51
  * Description: Modify the contents Auxiliary Control Register.

@@ -350,19 +361,13 @@ static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
  */
 static void omap3_update_aux_cr_secure_rx51(u32 set_bits, u32 clear_bits)
 {
-	struct emu_hal_params_rx51 emu_romcode_params = { 0, };
 	u32 acr;
 
 	/* Read ACR */
 	asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
 	acr &= ~clear_bits;
 	acr |= set_bits;
-
-	emu_romcode_params.num_params = 2;
-	emu_romcode_params.param1 = acr;
-
-	omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
-				(u32 *)&emu_romcode_params);
+	omap3_set_aux_cr_secure(acr);
 }
 
 /*
include/configs/nokia_rx51.h +4 -0
index 442e16ae686b..152a6e564b00 100644
@@ -29,6 +29,10 @@
 #define CONFIG_SYS_L2CACHE_OFF		/* pretend there is no L2 CACHE */
 #define CONFIG_OMAP_COMMON
 #define CONFIG_SYS_GENERIC_BOARD
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_454179
+#define CONFIG_ARM_ERRATA_430973
+#define CONFIG_ARM_ERRATA_621766
 
 #define CONFIG_MACH_TYPE		MACH_TYPE_NOKIA_RX51
Signature · 1 line
1.7.9.5
author
#16 lore raw

v5 cover ARM: OMAP3-DRA7: CP15 erratum workarounds and improvements

In reply to Nishanth Menon
Quoted 16 lines · Nishanth Menon

The fifth incarnation should be proper, I hope. (skipping all the blurb and pointing to v1 for the blurb).

Changes since v4:
- smc is back to handassembled thanks to gcc versions
- fixes in multiple call handling within cpu_init_cp15 -> thanks to Matt Porter's test log showing fail on r1p3 cortex-a8 (where the errata must be applied)

v4: http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/213863
V3: http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/213207/focus=213307
V2: http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/213060
V1: http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/212174

This time, the series is based on u-boot master
git://git.denx.de/u-boot.git
master 694cc87b76b1 arm, da8xx: convert ipam390 board to generic board support

Quoted 6 lines

Git tree: https://gitorious.org/nm-kernel/u-boot-nm (at least till gitorious is around..) branch errata-v5-master-694cc87b76b1

Git link: https://gitorious.org/nm-kernel/u-boot-nm.git errata-v5-master-694cc87b76b1

Testing: with http://paste.ubuntu.org.cn/2522971 (4.0-rc1 patch)

If folks have a older beagle around and dont want to startup the kernel for this, http://paste.ubuntu.org.cn/2525810 is a trivial patch to dump the same from the bootloader.

Quoted 17 lines

BeagleBoard-X15:

	Before: CPUID=0x412fc0f2 L2CTLR=0x01800083 L2ACLR=0x00000000 L2PFR=0x000009b0 ACTLR=0x00000040
	After: CPUID=0x412fc0f2 L2CTLR=0x01800083 L2ACLR=0x00000198 L2PFR=0x000009b0 ACTLR=0x00000040

OMAP5uEVM:

	Before: CPUID=0x412fc0f2 L2CTLR=0x01800083 L2ACLR=0x00000000 L2PFR=0x000009b0 ACTLR=0x00000040
	After: CPUID=0x412fc0f2 L2CTLR=0x01800083 L2ACLR=0x00000198 L2PFR=0x000009b0 ACTLR=0x00000040

Beagle-XM: this is a r3p2 cortex-a8

	Before: CPUID=0x413fc082 ACR=0x000000e2 L2AUXCR=0x00000042
	After: CPUID=0x413fc082 ACR=0x00000042 L2AUXCR=0x00000042
	To emulate matt's board, I hacked u-boot to force the code flow.
	Testing with (hack http://paste.ubuntu.org.cn/2525559): CPUID=0x413fc082 ACR=0x000000e2 L2AUXCR=0x00000042

I dont have access to other omap3 platforms to give a better coverage, so, I welcome as much testing as possible.

[...]

Signature · 2 lines
Regards,
Nishanth Menon
#17 lore raw

v5 cover ARM: OMAP3-DRA7: CP15 erratum workarounds and improvements

In reply to Nishanth Menon
Quoted 31 lines · Nishanth Menon

The fifth incarnation should be proper, I hope. (skipping all the blurb and pointing to v1 for the blurb).

Changes since v4:
- smc is back to handassembled thanks to gcc versions
- fixes in multiple call handling within cpu_init_cp15 -> thanks to Matt Porter's test log showing fail on r1p3 cortex-a8 (where the errata must be applied)

v4: http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/213863
V3: http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/213207/focus=213307
V2: http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/213060
V1: http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/212174

This time, the series is based on u-boot master
git://git.denx.de/u-boot.git
master 694cc87b76b1 arm, da8xx: convert ipam390 board to generic board support

Git tree: https://gitorious.org/nm-kernel/u-boot-nm (at least till gitorious is around..) branch errata-v5-master-694cc87b76b1

Git link: https://gitorious.org/nm-kernel/u-boot-nm.git errata-v5-master-694cc87b76b1

Testing: with http://paste.ubuntu.org.cn/2522971 (4.0-rc1 patch)

BeagleBoard-X15:

	Before: CPUID=0x412fc0f2 L2CTLR=0x01800083 L2ACLR=0x00000000 L2PFR=0x000009b0 ACTLR=0x00000040
	After: CPUID=0x412fc0f2 L2CTLR=0x01800083 L2ACLR=0x00000198 L2PFR=0x000009b0 ACTLR=0x00000040

OMAP5uEVM:

	Before: CPUID=0x412fc0f2 L2CTLR=0x01800083 L2ACLR=0x00000000 L2PFR=0x000009b0 ACTLR=0x00000040
	After: CPUID=0x412fc0f2 L2CTLR=0x01800083 L2ACLR=0x00000198 L2PFR=0x000009b0 ACTLR=0x00000040
Quoted 8 lines

Beagle-XM: this is a r3p2 cortex-a8

	Before: CPUID=0x413fc082 ACR=0x000000e2 L2AUXCR=0x00000042
	After: CPUID=0x413fc082 ACR=0x00000042 L2AUXCR=0x00000042
	To emulate matt's board, I hacked u-boot to force the code flow.
	Testing with (hack http://paste.ubuntu.org.cn/2525559): CPUID=0x413fc082 ACR=0x000000e2 L2AUXCR=0x00000042

I dont have access to other omap3 platforms to give a better coverage, so, I welcome as much testing as possible.

Also verified again here on my r1p2 Beagle. No more build issues on any of my toolchains, thanks.

Tested-by Matt Porter <[email protected]>
Quoted 68 lines

Nishanth Menon (10):
ARM: Introduce erratum workaround for 798870
ARM: Introduce erratum workaround for 454179
ARM: Introduce erratum workaround for 430973
ARM: Introduce erratum workaround for 621766
ARM: OMAP: Change set_pl310_ctrl_reg to be generic
ARM: OMAP3: Rename omap3.h to omap.h to be generic as all SoCs
ARM: OMAP3: Get rid of omap3_gp_romcode_call and replace with
omap_smc1
ARM: OMAP5 / DRA7: Setup L2 Aux Control Register with recommended
configuration
ARM: OMAP3: Enable workaround for ARM errata 454179, 430973, 621766
ARM: OMAP3: rx51: Enable workaround for ARM errata 454179, 430973,

    621766

Praveen Rao (1):
ARM: DRA7 / OMAP5: Add workaround for ARM errata 798870

 README                                             |    8 +++
 arch/arm/cpu/armv7/Makefile                        |    2 +-
 arch/arm/cpu/armv7/cp15.c                          |   29 +++++++++
 arch/arm/cpu/armv7/omap-common/Makefile            |    2 +-
 arch/arm/cpu/armv7/omap-common/lowlevel_init.S     |   20 +++---
 arch/arm/cpu/armv7/omap3/board.c                   |   60 +++++++-----------
 arch/arm/cpu/armv7/omap3/lowlevel_init.S           |   11 ----
 arch/arm/cpu/armv7/omap4/hwinit.c                  |    4 +-
 arch/arm/cpu/armv7/omap5/hwinit.c                  |   23 +++++++
 arch/arm/cpu/armv7/start.S                         |   64 +++++++++++++++++++-
 .../arm/include/asm/arch-omap3/{omap3.h => omap.h} |    0
 arch/arm/include/asm/arch-omap3/sys_proto.h        |    3 +-
 arch/arm/include/asm/arch-omap4/sys_proto.h        |    5 +-
 arch/arm/include/asm/arch-omap5/sys_proto.h        |    4 ++
 arch/arm/include/asm/armv7.h                       |    5 ++
 board/nokia/rx51/rx51.c                            |   19 +++---
 include/configs/am3517_crane.h                     |    6 +-
 include/configs/am3517_evm.h                       |    6 +-
 include/configs/cm_t35.h                           |    6 +-
 include/configs/cm_t3517.h                         |    6 +-
 include/configs/dig297.h                           |    6 +-
 include/configs/mcx.h                              |    6 +-
 include/configs/nokia_rx51.h                       |    6 +-
 include/configs/omap3_evm.h                        |    2 +-
 include/configs/omap3_evm_common.h                 |    4 ++
 include/configs/omap3_evm_quick_mmc.h              |    2 +-
 include/configs/omap3_evm_quick_nand.h             |    2 +-
 include/configs/omap3_logic.h                      |    6 +-
 include/configs/omap3_mvblx.h                      |    6 +-
 include/configs/omap3_pandora.h                    |    6 +-
 include/configs/omap3_sdp3430.h                    |    6 +-
 include/configs/omap3_zoom1.h                      |    2 +-
 include/configs/tam3517-common.h                   |    6 +-
 include/configs/tao3530.h                          |    6 +-
 include/configs/ti_omap3_common.h                  |    7 ++-
 include/configs/ti_omap5_common.h                  |    3 +
 include/configs/tricorder.h                        |    6 +-
 37 files changed, 275 insertions(+), 90 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/cp15.c
 rename arch/arm/include/asm/arch-omap3/{omap3.h => omap.h} (100%)

Regards,
Nishanth Menon

Signature · 6 lines
1.7.9.5

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