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Add support for QCOM GDSCs

PATCH Superseded Rajendra Nayak 3 participants 12 messages Mar 20, 2015 – Mar 24, 2015

Subsystems (4)
Device tree bindings Arm Qualcomm mailing list Common clk Qualcomm clock drivers

v3 of 8 Superseded Latest is v8 →

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Rajendra Nayak

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#0 lore raw

v3 cover Add support for QCOM GDSCs

GDSCs (Global Distributed Switch Controllers) control switches that supply power to an on-chip power domain and hence can be programmed in SW to safely power collapse and restore power to the respective PDs. They are part of a considerable number of recent QCOM SoCs (This series adds support for msm8974, msm8916 and apq8084 devices) and are part of the Clock control block.

The series implements support for GDSC using the genpd framework modelling these as SW controllable power domains.

* Patch 3/6 has a dependency on 8916 GCC support series [1]
* Client drivers which plan to use GDSC can refer to Documentation/devicetree/bindings/power/power_domain.txt to know how to hook up the power domain for the device through DT
* Runtime PM specific documentation can be found in Documentation/power/runtime_pm.txt

Changes since v2:
* gdsc_unregister added
* gdsc_register/unregister introduced in patch 1/6

Changes since v1:
* added err checks for regmap apis
* added gdsc_register() in gdsc.c

[1] https://lkml.org/lkml/2015/3/18/408

Rajendra Nayak (3):
clk: qcom: gdsc: Prepare common clk probe to register gdscs
clk: qcom: gdsc: Add GDSCs in msm8916 GCC
clk: qcom: gdsc: Add GDSCs in apq8084 GCC

Stephen Boyd (3):
clk: qcom: Add support for GDSCs
clk: qcom: gdsc: Add GDSCs in msm8974 GCC
clk: qcom: gdsc: Add GDSCs in msm8974 MMCC

 arch/arm/boot/dts/qcom-apq8084.dtsi           |   1 +
 arch/arm/boot/dts/qcom-msm8974.dtsi           |   2 +
 drivers/clk/qcom/Kconfig                      |   9 ++
 drivers/clk/qcom/Makefile                     |   1 +
 drivers/clk/qcom/common.c                     |  14 ++-
 drivers/clk/qcom/common.h                     |   2 +
 drivers/clk/qcom/gcc-apq8084.c                |  38 ++++++
 drivers/clk/qcom/gcc-msm8916.c                |  46 +++++++
 drivers/clk/qcom/gcc-msm8974.c                |  14 +++
 drivers/clk/qcom/gdsc.c                       | 166 ++++++++++++++++++++++++++
 drivers/clk/qcom/gdsc.h                       |  46 +++++++
 drivers/clk/qcom/mmcc-msm8974.c               |  54 +++++++++
 include/dt-bindings/clock/qcom,gcc-apq8084.h  |   6 +
 include/dt-bindings/clock/qcom,gcc-msm8916.h  |   8 ++
 include/dt-bindings/clock/qcom,gcc-msm8974.h  |   3 +
 include/dt-bindings/clock/qcom,mmcc-msm8974.h |   8 ++
 16 files changed, 417 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/qcom/gdsc.c
 create mode 100644 drivers/clk/qcom/gdsc.h
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
author
#1 lore raw

PATCH v3 1/6 clk: qcom: Add support for GDSCs

From: Stephen Boyd <[email protected]>

GDSCs (Global Distributed Switch Controllers) are responsible for safely collapsing and restoring power to peripherals in the SoC. These are best modelled as power domains using genpd and given the registers are scattered throughout the clock controller register space, its best to have the support added through the clock driver.

Signed-off-by Stephen Boyd <[email protected]>
Signed-off-by Rajendra Nayak <[email protected]>
---
 drivers/clk/qcom/Kconfig  |   5 ++
 drivers/clk/qcom/Makefile |   1 +
 drivers/clk/qcom/gdsc.c   | 166 ++++++++++++++++++++++++++++++++++++++++++++++
 drivers/clk/qcom/gdsc.h   |  46 +++++++++++++
 4 files changed, 218 insertions(+)
 create mode 100644 drivers/clk/qcom/gdsc.c
 create mode 100644 drivers/clk/qcom/gdsc.h
drivers/clk/qcom/Kconfig +5 -0
index 48d5151..f436bcf 100644
@@ -38,6 +38,11 @@ config IPQ_LCC_806X
 	  Say Y if you want to use audio devices such as i2s, pcm,
 	  S/PDIF, etc.
 
+config QCOM_GDSC
+	bool
+	select PM_GENERIC_DOMAINS if PM
+	depends on COMMON_CLK_QCOM
+
 config MSM_GCC_8660
 	tristate "MSM8660 Global Clock Controller"
 	depends on COMMON_CLK_QCOM
drivers/clk/qcom/Makefile +1 -0
index 50b337a..fe62523 100644
@@ -9,6 +9,7 @@ clk-qcom-y += clk-branch.o
 clk-qcom-y += clk-regmap-divider.o
 clk-qcom-y += clk-regmap-mux.o
 clk-qcom-y += reset.o
+clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o
 
 obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o
 obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o
drivers/clk/qcom/gdsc.c new file +166 -0

166 lines not on this page · raw message

drivers/clk/qcom/gdsc.h new file +46 -0

46 lines not on this page · raw message

Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
#2 lore raw

PATCH v3 1/6 clk: qcom: Add support for GDSCs

Minor Nit picks,

Quoted 19 lines · Rajendra Nayak

From: Stephen Boyd <[email protected]>

GDSCs (Global Distributed Switch Controllers) are responsible for safely collapsing and restoring power to peripherals in the SoC. These are best modelled as power domains using genpd and given the registers are scattered throughout the clock controller register space, its best to have the support added through the clock driver.

Signed-off-by Stephen Boyd <[email protected]>
Signed-off-by Rajendra Nayak <[email protected]>
---
  drivers/clk/qcom/Kconfig  |   5 ++
  drivers/clk/qcom/Makefile |   1 +
  drivers/clk/qcom/gdsc.c   | 166 ++++++++++++++++++++++++++++++++++++++++++++++
  drivers/clk/qcom/gdsc.h   |  46 +++++++++++++
  4 files changed, 218 insertions(+)

create mode 100644 drivers/clk/qcom/gdsc.c
create mode 100644 drivers/clk/qcom/gdsc.h

...

drivers/clk/qcom/gdsc.c line 16

Quoted 4 lines
drivers/clk/qcom/gdsc.c new file +4 -0
+
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/export.h>

?? Do you need this?

Quoted 18 lines
drivers/clk/qcom/gdsc.c new file +18 -0
+#include <linux/jiffies.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+#include "gdsc.h"
+
+#define PWR_ON_MASK		BIT(31)
+#define EN_REST_WAIT_MASK	GENMASK(23, 20)
+#define EN_FEW_WAIT_MASK	GENMASK(19, 16)
+#define CLK_DIS_WAIT_MASK	GENMASK(15, 12)
+#define SW_OVERRIDE_MASK	BIT(2)
+#define HW_CONTROL_MASK		BIT(1)
+#define SW_COLLAPSE_MASK	BIT(0)
+
+/* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */
+#define EN_REST_WAIT_VAL	(0x2 << 20)
+#define EN_FEW_WAIT_VAL		(0x8 << 16)
+#define CLK_DIS_WAIT_VAL	(0x2 << 12)
+

drivers/clk/qcom/gdsc.c line 44

Quoted 10 lines
drivers/clk/qcom/gdsc.c new file +10 -0
+#define TIMEOUT_US		100
+
+static int gdsc_is_enabled(struct gdsc *sc)
+{
+	u32 val;
+	int ret;
+
+	ret = regmap_read(sc->regmap, sc->gdscr, &val);
+	if (ret)
+		return ret;

Line after this would be good.

Quoted 16 lines
drivers/clk/qcom/gdsc.c new file +16 -0
+	return !!(val & PWR_ON_MASK);
+}
+
+static int gdsc_toggle_logic(struct gdsc *sc, bool en)
+{
+	int ret;
+	u32 val = en ? 0 : SW_COLLAPSE_MASK;
+	u32 check = en ? PWR_ON_MASK : 0;
+	unsigned long timeout;
+
+	ret = regmap_update_bits(sc->regmap, sc->gdscr, SW_COLLAPSE_MASK, val);
+	if (ret)
+		return ret;
+
+	timeout = jiffies + usecs_to_jiffies(TIMEOUT_US);
+	do {

drivers/clk/qcom/gdsc.c line 70

Quoted 10 lines
drivers/clk/qcom/gdsc.c new file +10 -0
+		ret = regmap_read(sc->regmap, sc->gdscr, &val);
+		if (ret)
+			return ret;
+		if ((val & PWR_ON_MASK) == check)
+			return 0;
+	} while (time_before(jiffies, timeout));
+
+	ret =  regmap_read(sc->regmap, sc->gdscr, &val);
+	if (ret)
+		return ret;

New line here.

Quoted 6 lines
drivers/clk/qcom/gdsc.c new file +6 -0
+	if ((val & PWR_ON_MASK) == check)
+		return 0;
+
+	return -ETIMEDOUT;
+}
+

...

drivers/clk/qcom/gdsc.c line 139

Quoted 9 lines
drivers/clk/qcom/gdsc.c new file +9 -0
+
+int gdsc_register(struct device *dev, struct gdsc **scs, size_t num,
+		  struct regmap *regmap)
+{
+	int i, ret;
+	struct genpd_onecell_data *data;
+
+	if (!num || !scs || !dev || !dev->of_node)
+		return 0;

Should it not return -EINVAL here?

Quoted 10 lines
drivers/clk/qcom/gdsc.c new file +10 -0
+
+	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
+
+	data->domains = devm_kzalloc(dev, sizeof(*data->domains) * num,
+				     GFP_KERNEL);
+	if (!data->domains)
+		return -ENOMEM;
+

drivers/clk/qcom/gdsc.c line 159

Quoted 10 lines
drivers/clk/qcom/gdsc.c new file +10 -0
+	data->num_domains = num;
+	for (i = 0; i < num; i++) {
+		if (!scs[i])
+			continue;
+		scs[i]->regmap = regmap;
+		ret = gdsc_init(scs[i]);
+		if (ret)
+			return ret;
+		data->domains[i] = &scs[i]->pd;
+	}

New line?

Quoted 42 lines
drivers/clk/qcom/gdsc.c new file +7 -0
+	return of_genpd_add_provider_onecell(dev->of_node, data);
+}
+
+void gdsc_unregister(struct device *dev)
+{
+	of_genpd_del_provider(dev->of_node);
+}
drivers/clk/qcom/gdsc.h new file +29 -0
new file mode 100644
index 0000000..02e2990
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __QCOM_GDSC_H__
+#define __QCOM_GDSC_H__
+
+#include <linux/pm_domain.h>
+
+struct regmap;
+
+/**
+ * struct gdsc - Globally Distributed Switch Controller
+ * @pd: generic power domain
+ * @regmap: regmap for MMIO accesses
+ * @gdscr: gsdc control register
+ */
+struct gdsc {
+	struct generic_pm_domain	pd;
+	struct regmap			*regmap;

drivers/clk/qcom/gdsc.h line 39

Quoted 10 lines
drivers/clk/qcom/gdsc.h new file +10 -0
+	unsigned int			gdscr;
+};
+
+#define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)
+
+#ifdef CONFIG_QCOM_GDSC
+int gdsc_register(struct device *, struct gdsc **, size_t n, struct regmap *);
+void gdsc_unregister(struct device *);
+#else
+int gdsc_register(struct device *d, struct gdsc **g, size_t n, struct regmap *r)

static inline here??? else it would result in muliple definitions?

drivers/clk/qcom/gdsc.h line 41

Quoted 2 lines
drivers/clk/qcom/gdsc.h new file +2 -0
+{
+	return 0;

return -ENOSYS; I

drivers/clk/qcom/gdsc.h line 44

Quoted 3 lines
drivers/clk/qcom/gdsc.h new file +3 -0
+}
+
+void gdsc_unregister(struct device *d) {};

same static inline...
Braces should be in next line too.

drivers/clk/qcom/gdsc.h line 46

Quoted 3 lines
drivers/clk/qcom/gdsc.h new file +2 -0
+#endif /* CONFIG_QCOM_GDSC */
+#endif /* __QCOM_GDSC_H__ */

--srini

author
#3 lore raw

PATCH v3 1/6 clk: qcom: Add support for GDSCs

Quoted 6 lines

...

drivers/clk/qcom/gdsc.c line 16

Quoted 4 lines
drivers/clk/qcom/gdsc.c new file +4 -0
+
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/export.h>

?? Do you need this?

Maybe not, now that the EXPORT_SYMBOL() is gone.
I will remove it.

Quoted 66 lines
Quoted 19 lines
drivers/clk/qcom/gdsc.c new file +18 -0
+#include <linux/jiffies.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+#include "gdsc.h"
+
+#define PWR_ON_MASK        BIT(31)
+#define EN_REST_WAIT_MASK    GENMASK(23, 20)
+#define EN_FEW_WAIT_MASK    GENMASK(19, 16)
+#define CLK_DIS_WAIT_MASK    GENMASK(15, 12)
+#define SW_OVERRIDE_MASK    BIT(2)
+#define HW_CONTROL_MASK        BIT(1)
+#define SW_COLLAPSE_MASK    BIT(0)
+
+/* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */
+#define EN_REST_WAIT_VAL    (0x2 << 20)
+#define EN_FEW_WAIT_VAL        (0x8 << 16)
+#define CLK_DIS_WAIT_VAL    (0x2 << 12)
+

drivers/clk/qcom/gdsc.c line 44

Quoted 10 lines
drivers/clk/qcom/gdsc.c new file +10 -0
+#define TIMEOUT_US        100
+
+static int gdsc_is_enabled(struct gdsc *sc)
+{
+    u32 val;
+    int ret;
+
+    ret = regmap_read(sc->regmap, sc->gdscr, &val);
+    if (ret)
+        return ret;

Line after this would be good.

Quoted 17 lines
drivers/clk/qcom/gdsc.c new file +11 -0
+    return !!(val & PWR_ON_MASK);
+}
+
+static int gdsc_toggle_logic(struct gdsc *sc, bool en)
+{
+    int ret;
+    u32 val = en ? 0 : SW_COLLAPSE_MASK;
+    u32 check = en ? PWR_ON_MASK : 0;
+    unsigned long timeout;
+
+    ret = regmap_update_bits(sc->regmap, sc->gdscr, SW_COLLAPSE_MASK,

val);

drivers/clk/qcom/gdsc.c new file +5 -0
+    if (ret)
+        return ret;
+
+    timeout = jiffies + usecs_to_jiffies(TIMEOUT_US);
+    do {

drivers/clk/qcom/gdsc.c line 70

Quoted 10 lines
drivers/clk/qcom/gdsc.c new file +10 -0
+        ret = regmap_read(sc->regmap, sc->gdscr, &val);
+        if (ret)
+            return ret;
+        if ((val & PWR_ON_MASK) == check)
+            return 0;
+    } while (time_before(jiffies, timeout));
+
+    ret =  regmap_read(sc->regmap, sc->gdscr, &val);
+    if (ret)
+        return ret;

New line here.

Quoted 6 lines
drivers/clk/qcom/gdsc.c new file +6 -0
+    if ((val & PWR_ON_MASK) == check)
+        return 0;
+
+    return -ETIMEDOUT;
+}
+

...

Quoted 10 lines

drivers/clk/qcom/gdsc.c line 139

Quoted 9 lines
drivers/clk/qcom/gdsc.c new file +9 -0
+
+int gdsc_register(struct device *dev, struct gdsc **scs, size_t num,
+          struct regmap *regmap)
+{
+    int i, ret;
+    struct genpd_onecell_data *data;
+
+    if (!num || !scs || !dev || !dev->of_node)
+        return 0;

Should it not return -EINVAL here?

so we have gdsc_register() getting called from qcom_cc_really_probe() and we might have devices with no gdscs as part of gcc. So the way to identify those is the num and scs aren't really initialized. I should probably move this check into the common clk probe function and not call gdsc_register() if these are not inited, and return a -EINVAL for (!dev || !dev->of_node) here.

Quoted 70 lines
Quoted 11 lines
drivers/clk/qcom/gdsc.c new file +10 -0
+
+    data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
+    if (!data)
+        return -ENOMEM;
+
+    data->domains = devm_kzalloc(dev, sizeof(*data->domains) * num,
+                     GFP_KERNEL);
+    if (!data->domains)
+        return -ENOMEM;
+

drivers/clk/qcom/gdsc.c line 159

Quoted 10 lines
drivers/clk/qcom/gdsc.c new file +10 -0
+    data->num_domains = num;
+    for (i = 0; i < num; i++) {
+        if (!scs[i])
+            continue;
+        scs[i]->regmap = regmap;
+        ret = gdsc_init(scs[i]);
+        if (ret)
+            return ret;
+        data->domains[i] = &scs[i]->pd;
+    }

New line?

Quoted 48 lines
drivers/clk/qcom/gdsc.c new file +7 -0
+    return of_genpd_add_provider_onecell(dev->of_node, data);
+}
+
+void gdsc_unregister(struct device *dev)
+{
+    of_genpd_del_provider(dev->of_node);
+}
drivers/clk/qcom/gdsc.h new file +35 -0
new file mode 100644
index 0000000..02e2990
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __QCOM_GDSC_H__
+#define __QCOM_GDSC_H__
+
+#include <linux/pm_domain.h>
+
+struct regmap;
+
+/**
+ * struct gdsc - Globally Distributed Switch Controller
+ * @pd: generic power domain
+ * @regmap: regmap for MMIO accesses
+ * @gdscr: gsdc control register
+ */
+struct gdsc {
+    struct generic_pm_domain    pd;
+    struct regmap            *regmap;
+    unsigned int            gdscr;
+};
+
+#define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)
+
+#ifdef CONFIG_QCOM_GDSC
Quoted 8 lines
Quoted 6 lines
drivers/clk/qcom/gdsc.h new file +1 -0
+int gdsc_register(struct device *, struct gdsc **, size_t n, struct

regmap *);

drivers/clk/qcom/gdsc.h new file +3 -0
+void gdsc_unregister(struct device *);
+#else
+int gdsc_register(struct device *d, struct gdsc **g, size_t n, struct

regmap *r)

static inline here??? else it would result in muliple definitions?

It shouldn't result in mutiple defs, but static inline would be good. I will fix it.

Quoted 4 lines

drivers/clk/qcom/gdsc.h

Quoted 3 lines
drivers/clk/qcom/gdsc.h new file +2 -0
+{
+    return 0;

return -ENOSYS;

This should work once I put checks for non inited desc->num_gdscs as part of qcom_cc_really_probe().

Thanks for the review. I'll post a v4 with the changes. regards,
Rajendra

Quoted 11 lines

drivers/clk/qcom/gdsc.h line 44

Quoted 3 lines
drivers/clk/qcom/gdsc.h new file +3 -0
+}
+
+void gdsc_unregister(struct device *d) {};

same static inline...
Braces should be in next line too.

drivers/clk/qcom/gdsc.h line 46

Quoted 3 lines
drivers/clk/qcom/gdsc.h new file +2 -0
+#endif /* CONFIG_QCOM_GDSC */
+#endif /* __QCOM_GDSC_H__ */

--srini

Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation
author
#4 lore raw

PATCH v3 1/6 clk: qcom: Add support for GDSCs

[]...

Quoted 12 lines
Quoted 12 lines
Quoted 12 lines
drivers/clk/qcom/gdsc.c new file +11 -0
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
Quoted 8 lines
Quoted 8 lines

drivers/clk/qcom/gdsc.h line 19

Quoted 8 lines
drivers/clk/qcom/gdsc.h new file +8 -0
+ */
+
+#ifndef __QCOM_GDSC_H__
+#define __QCOM_GDSC_H__
+
+#include <linux/pm_domain.h>
+
+struct regmap;

I realized, after Srini pointed out on irc that this fwd declaration is a complete waste. I'll remove it when I do a repost.

Quoted 22 lines
Quoted 22 lines
Quoted 22 lines
drivers/clk/qcom/gdsc.h new file +17 -0
+
+/**
+ * struct gdsc - Globally Distributed Switch Controller
+ * @pd: generic power domain
+ * @regmap: regmap for MMIO accesses
+ * @gdscr: gsdc control register
+ */
+struct gdsc {
+    struct generic_pm_domain    pd;
+    struct regmap            *regmap;
+    unsigned int            gdscr;
+};
+
+#define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)
+
+#ifdef CONFIG_QCOM_GDSC
+int gdsc_register(struct device *, struct gdsc **, size_t n, struct

regmap *);

drivers/clk/qcom/gdsc.h new file +3 -0
+void gdsc_unregister(struct device *);
+#else
+int gdsc_register(struct device *d, struct gdsc **g, size_t n, struct

regmap *r)

#5 lore raw

PATCH v3 1/6 clk: qcom: Add support for GDSCs

Quoted 16 lines · Rajendra Nayak

[]...

Quoted 15 lines
Quoted 15 lines
Quoted 15 lines
drivers/clk/qcom/gdsc.h new file +14 -0
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __QCOM_GDSC_H__
Quoted 9 lines
Quoted 5 lines
Quoted 5 lines

drivers/clk/qcom/gdsc.h line 19

Quoted 5 lines
drivers/clk/qcom/gdsc.h new file +5 -0
+#define __QCOM_GDSC_H__
+
+#include <linux/pm_domain.h>
+
+struct regmap;

I realized, after Srini pointed out on irc that this fwd declaration is a complete waste. I'll remove it when I do a repost.

Why? It's there so that struct regmap is declared instead of being declared inside struct gdsc.

Quoted 22 lines
Quoted 22 lines
Quoted 22 lines
Quoted 22 lines
drivers/clk/qcom/gdsc.h new file +17 -0
+
+/**
+ * struct gdsc - Globally Distributed Switch Controller
+ * @pd: generic power domain
+ * @regmap: regmap for MMIO accesses
+ * @gdscr: gsdc control register
+ */
+struct gdsc {
+    struct generic_pm_domain    pd;
+    struct regmap            *regmap;
+    unsigned int            gdscr;
+};
+
+#define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)
+
+#ifdef CONFIG_QCOM_GDSC
+int gdsc_register(struct device *, struct gdsc **, size_t n, struct

regmap *);

drivers/clk/qcom/gdsc.h new file +3 -0
+void gdsc_unregister(struct device *);
+#else
+int gdsc_register(struct device *d, struct gdsc **g, size_t n, struct

regmap *r)

Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
author
#6 lore raw

PATCH v3 1/6 clk: qcom: Add support for GDSCs

Quoted 27 lines · Stephen Boyd
Quoted 16 lines · Rajendra Nayak

[]...

Quoted 15 lines
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drivers/clk/qcom/gdsc.h new file +14 -0
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __QCOM_GDSC_H__
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drivers/clk/qcom/gdsc.h line 19

Quoted 5 lines
drivers/clk/qcom/gdsc.h new file +5 -0
+#define __QCOM_GDSC_H__
+
+#include <linux/pm_domain.h>
+
+struct regmap;

I realized, after Srini pointed out on irc that this fwd declaration is a complete waste. I'll remove it when I do a repost.

Quoted 2 lines

Why? It's there so that struct regmap is declared instead of being declared inside struct gdsc.

ah, sorry. I completely overlooked the fact that there isn;t a #include <linux/regmap.h>

Quoted 24 lines
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drivers/clk/qcom/gdsc.h new file +17 -0
+
+/**
+ * struct gdsc - Globally Distributed Switch Controller
+ * @pd: generic power domain
+ * @regmap: regmap for MMIO accesses
+ * @gdscr: gsdc control register
+ */
+struct gdsc {
+    struct generic_pm_domain    pd;
+    struct regmap            *regmap;
+    unsigned int            gdscr;
+};
+
+#define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)
+
+#ifdef CONFIG_QCOM_GDSC
+int gdsc_register(struct device *, struct gdsc **, size_t n, struct

regmap *);

drivers/clk/qcom/gdsc.h new file +3 -0
+void gdsc_unregister(struct device *);
+#else
+int gdsc_register(struct device *d, struct gdsc **g, size_t n, struct

regmap *r)

Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation
author
#7 lore raw

PATCH v3 2/6 clk: qcom: gdsc: Prepare common clk probe to register gdscs

In reply to Rajendra Nayak

The common clk probe registers a clk provider and a reset controller. Update it to register a genpd provider using the gdsc data provided by each platform.

Signed-off-by Rajendra Nayak <[email protected]>
---
 drivers/clk/qcom/common.c | 14 +++++++++++++-
 drivers/clk/qcom/common.h |  2 ++
 2 files changed, 15 insertions(+), 1 deletion(-)
drivers/clk/qcom/common.c +13 -1
index a946b48..0c9fbc7 100644
@@ -21,6 +21,7 @@
 #include "clk-rcg.h"
 #include "clk-regmap.h"
 #include "reset.h"
+#include "gdsc.h"
 
 struct qcom_cc {
 	struct qcom_reset_controller reset;

@@ -125,8 +126,18 @@ int qcom_cc_really_probe(struct platform_device *pdev,
 
 	ret = reset_controller_register(&reset->rcdev);
 	if (ret)
-		of_clk_del_provider(dev->of_node);
+		goto err_reset;
 
+	ret = gdsc_register(dev, desc->gdscs, desc->num_gdscs, regmap);
+	if (ret)
+		goto err_pd;
+
+	return 0;
+err_pd:
+	dev_err(dev, "Failed to register power domains\n");
+	reset_controller_unregister(&reset->rcdev);
+err_reset:
+	of_clk_del_provider(dev->of_node);
 	return ret;
 }
 EXPORT_SYMBOL_GPL(qcom_cc_really_probe);

@@ -145,6 +156,7 @@ EXPORT_SYMBOL_GPL(qcom_cc_probe);
 
 void qcom_cc_remove(struct platform_device *pdev)
 {
+	gdsc_unregister(&pdev->dev);
 	of_clk_del_provider(pdev->dev.of_node);
 	reset_controller_unregister(platform_get_drvdata(pdev));
 }
drivers/clk/qcom/common.h +2 -0
index b3d7e57..480fdbe 100644
@@ -27,6 +27,8 @@ struct qcom_cc_desc {
 	size_t num_clks;
 	const struct qcom_reset_map *resets;
 	size_t num_resets;
+	struct gdsc **gdscs;
+	size_t num_gdscs;
 };
 
 extern const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f,
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
author
#8 lore raw

PATCH v3 3/6 clk: qcom: gdsc: Add GDSCs in msm8916 GCC

In reply to Rajendra Nayak

Add all data for the GDSCs which are part of msm8916 GCC block.

Signed-off-by Rajendra Nayak <[email protected]>
---
 drivers/clk/qcom/Kconfig                     |  1 +
 drivers/clk/qcom/gcc-msm8916.c               | 46 ++++++++++++++++++++++++++++
 include/dt-bindings/clock/qcom,gcc-msm8916.h |  8 +++++
 3 files changed, 55 insertions(+)
drivers/clk/qcom/Kconfig +1 -0
index f436bcf..2fe1b30 100644
@@ -53,6 +53,7 @@ config MSM_GCC_8660
 
 config MSM_GCC_8916
 	tristate "MSM8916 Global Clock Controller"
+	select QCOM_GDSC
 	depends on COMMON_CLK_QCOM
 	help
 	  Support for the global clock controller on msm8916 devices.
drivers/clk/qcom/gcc-msm8916.c +46 -0

70 lines not on this page · raw message

include/dt-bindings/clock/qcom,gcc-msm8916.h +8 -0
index e430f64..11566c5 100644
@@ -153,4 +153,12 @@
 #define GCC_VENUS0_AXI_CLK			136
 #define GCC_VENUS0_VCODEC0_CLK			137
 
+/* Indexes for GDSCs */
+#define BIMC_GDSC				0
+#define VENUS_GDSC				1
+#define MDSS_GDSC				2
+#define JPEG_GDSC				3
+#define VFE_GDSC				4
+#define OXILI_GDSC				5
+
 #endif
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
author
#9 lore raw

PATCH v3 4/6 clk: qcom: gdsc: Add GDSCs in msm8974 GCC

In reply to Rajendra Nayak

From: Stephen Boyd <[email protected]>

Theres just one GDSC as part of the msm8974 GCC block.

Signed-off-by Stephen Boyd <[email protected]>
Signed-off-by Rajendra Nayak <[email protected]>
---
 arch/arm/boot/dts/qcom-msm8974.dtsi          |  1 +
 drivers/clk/qcom/Kconfig                     |  1 +
 drivers/clk/qcom/gcc-msm8974.c               | 14 ++++++++++++++
 include/dt-bindings/clock/qcom,gcc-msm8974.h |  3 +++
 4 files changed, 19 insertions(+)
arch/arm/boot/dts/qcom-msm8974.dtsi +1 -0
index e265ec1..12d17c2 100644
@@ -179,6 +179,7 @@
 			compatible = "qcom,gcc-msm8974";
 			#clock-cells = <1>;
 			#reset-cells = <1>;
+			#power-domain-cells = <1>;
 			reg = <0xfc400000 0x4000>;
 		};
drivers/clk/qcom/Kconfig +1 -0
index 2fe1b30..77568bd 100644
@@ -88,6 +88,7 @@ config MSM_MMCC_8960
 
 config MSM_GCC_8974
 	tristate "MSM8974 Global Clock Controller"
+	select QCOM_GDSC
 	depends on COMMON_CLK_QCOM
 	help
 	  Support for the global clock controller on msm8974 devices.
drivers/clk/qcom/gcc-msm8974.c +14 -0
index a714114..c0f4e62 100644
@@ -31,6 +31,7 @@
 #include "clk-rcg.h"
 #include "clk-branch.h"
 #include "reset.h"
+#include "gdsc.h"
 
 enum {
 	P_XO,

@@ -2434,6 +2435,13 @@ static struct clk_branch gcc_usb_hsic_system_clk = {
 	},
 };
 
+static struct gdsc usb_hs_hsic_gdsc = {
+	.gdscr = 0x404,
+	.pd = {
+		.name = "usb_hs_hsic",
+	},
+};
+
 static struct clk_regmap *gcc_msm8974_clocks[] = {
 	[GPLL0] = &gpll0.clkr,
 	[GPLL0_VOTE] = &gpll0_vote,

@@ -2663,6 +2671,10 @@ static const struct qcom_reset_map gcc_msm8974_resets[] = {
 	[GCC_VENUS_RESTART] = { 0x1740 },
 };
 
+static struct gdsc *gcc_msm8974_gdscs[] = {
+	[USB_HS_HSIC_GDSC] = &usb_hs_hsic_gdsc,
+};
+
 static const struct regmap_config gcc_msm8974_regmap_config = {
 	.reg_bits	= 32,
 	.reg_stride	= 4,

@@ -2677,6 +2689,8 @@ static const struct qcom_cc_desc gcc_msm8974_desc = {
 	.num_clks = ARRAY_SIZE(gcc_msm8974_clocks),
 	.resets = gcc_msm8974_resets,
 	.num_resets = ARRAY_SIZE(gcc_msm8974_resets),
+	.gdscs = gcc_msm8974_gdscs,
+	.num_gdscs = ARRAY_SIZE(gcc_msm8974_gdscs),
 };
 
 static const struct of_device_id gcc_msm8974_match_table[] = {
include/dt-bindings/clock/qcom,gcc-msm8974.h +3 -0
index 51e51c8..81d32f6 100644
@@ -321,4 +321,7 @@
 #define GCC_SDCC1_CDCCAL_SLEEP_CLK				304
 #define GCC_SDCC1_CDCCAL_FF_CLK					305
 
+/* gdscs */
+#define USB_HS_HSIC_GDSC					0
+
 #endif
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
author
#10 lore raw

PATCH v3 5/6 clk: qcom: gdsc: Add GDSCs in msm8974 MMCC

In reply to Rajendra Nayak

From: Stephen Boyd <[email protected]>

Add the GDSC instances that exist as part of msm8974 MMCC block

Signed-off-by Stephen Boyd <[email protected]>
Signed-off-by Rajendra Nayak <[email protected]>
---
 arch/arm/boot/dts/qcom-msm8974.dtsi           |  1 +
 drivers/clk/qcom/Kconfig                      |  1 +
 drivers/clk/qcom/mmcc-msm8974.c               | 54 +++++++++++++++++++++++++++
 include/dt-bindings/clock/qcom,mmcc-msm8974.h |  8 ++++
 4 files changed, 64 insertions(+)
arch/arm/boot/dts/qcom-msm8974.dtsi +1 -0
index 12d17c2..6184d32 100644
@@ -187,6 +187,7 @@
 			compatible = "qcom,mmcc-msm8974";
 			#clock-cells = <1>;
 			#reset-cells = <1>;
+			#power-domain-cells = <1>;
 			reg = <0xfd8c0000 0x6000>;
 		};
drivers/clk/qcom/Kconfig +1 -0
index 77568bd..104ec0c 100644
@@ -98,6 +98,7 @@ config MSM_GCC_8974
 config MSM_MMCC_8974
 	tristate "MSM8974 Multimedia Clock Controller"
 	select MSM_GCC_8974
+	select QCOM_GDSC
 	depends on COMMON_CLK_QCOM
 	help
 	  Support for the multimedia clock controller on msm8974 devices.
drivers/clk/qcom/mmcc-msm8974.c +54 -0

78 lines not on this page · raw message

include/dt-bindings/clock/qcom,mmcc-msm8974.h +8 -0
index 032ed87..28651e5 100644
@@ -158,4 +158,12 @@
 #define SPDM_RM_AXI					141
 #define SPDM_RM_OCMEMNOC				142
 
+/* gdscs */
+#define VENUS0_GDSC					0
+#define MDSS_GDSC					1
+#define CAMSS_JPEG_GDSC					2
+#define CAMSS_VFE_GDSC					3
+#define OXILI_GDSC					4
+#define OXILICX_GDSC					5
+
 #endif
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
author
#11 lore raw

PATCH v3 6/6 clk: qcom: gdsc: Add GDSCs in apq8084 GCC

In reply to Rajendra Nayak

Add the GDSC instances that exist as part of apq8084 GCC block

Signed-off-by Rajendra Nayak <[email protected]>
---
 arch/arm/boot/dts/qcom-apq8084.dtsi          |  1 +
 drivers/clk/qcom/Kconfig                     |  1 +
 drivers/clk/qcom/gcc-apq8084.c               | 38 ++++++++++++++++++++++++++++
 include/dt-bindings/clock/qcom,gcc-apq8084.h |  6 +++++
 4 files changed, 46 insertions(+)
arch/arm/boot/dts/qcom-apq8084.dtsi +1 -0
index 1f130bc..55c281c 100644
@@ -183,6 +183,7 @@
 			compatible = "qcom,gcc-apq8084";
 			#clock-cells = <1>;
 			#reset-cells = <1>;
+			#power-domain-cells = <1>;
 			reg = <0xfc400000 0x4000>;
 		};
drivers/clk/qcom/Kconfig +1 -0
index 104ec0c..c246417 100644
@@ -6,6 +6,7 @@ config COMMON_CLK_QCOM
 
 config APQ_GCC_8084
 	tristate "APQ8084 Global Clock Controller"
+	select QCOM_GDSC
 	depends on COMMON_CLK_QCOM
 	help
 	  Support for the global clock controller on apq8084 devices.
drivers/clk/qcom/gcc-apq8084.c +38 -0
index f75b505..6fafc2a 100644
@@ -31,6 +31,7 @@
 #include "clk-rcg.h"
 #include "clk-branch.h"
 #include "reset.h"
+#include "gdsc.h"
 
 enum {
 	P_XO,

@@ -3259,6 +3260,34 @@ static struct clk_branch gcc_usb_hsic_system_clk = {
 	},
 };
 
+static struct gdsc usb_hs_hsic_gdsc = {
+	.gdscr = 0x404,
+	.pd = {
+		.name = "usb_hs_hsic",
+	},
+};
+
+static struct gdsc pcie0_gdsc = {
+	.gdscr = 0x1ac4,
+	.pd = {
+		.name = "pcie0",
+	},
+};
+
+static struct gdsc pcie1_gdsc = {
+	.gdscr = 0x1b44,
+	.pd = {
+		.name = "pcie1",
+	},
+};
+
+static struct gdsc usb30_gdsc = {
+	.gdscr = 0x1e84,
+	.pd = {
+		.name = "usb30",
+	},
+};
+
 static struct clk_regmap *gcc_apq8084_clocks[] = {
 	[GPLL0] = &gpll0.clkr,
 	[GPLL0_VOTE] = &gpll0_vote,

@@ -3452,6 +3481,13 @@ static struct clk_regmap *gcc_apq8084_clocks[] = {
 	[GCC_USB_HSIC_SYSTEM_CLK] = &gcc_usb_hsic_system_clk.clkr,
 };
 
+static struct gdsc *gcc_apq8084_gdscs[] = {
+	[USB_HS_HSIC_GDSC] = &usb_hs_hsic_gdsc,
+	[PCIE0_GDSC] = &pcie0_gdsc,
+	[PCIE1_GDSC] = &pcie1_gdsc,
+	[USB30_GDSC] = &usb30_gdsc,
+};
+
 static const struct qcom_reset_map gcc_apq8084_resets[] = {
 	[GCC_SYSTEM_NOC_BCR] = { 0x0100 },
 	[GCC_CONFIG_NOC_BCR] = { 0x0140 },

@@ -3560,6 +3596,8 @@ static const struct qcom_cc_desc gcc_apq8084_desc = {
 	.num_clks = ARRAY_SIZE(gcc_apq8084_clocks),
 	.resets = gcc_apq8084_resets,
 	.num_resets = ARRAY_SIZE(gcc_apq8084_resets),
+	.gdscs = gcc_apq8084_gdscs,
+	.num_gdscs = ARRAY_SIZE(gcc_apq8084_gdscs),
 };
 
 static const struct of_device_id gcc_apq8084_match_table[] = {
include/dt-bindings/clock/qcom,gcc-apq8084.h +6 -0
index 2c0da56..5aa7ebe 100644
@@ -348,4 +348,10 @@
 #define GCC_PCIE_1_PIPE_CLK				331
 #define GCC_PCIE_1_SLV_AXI_CLK				332
 
+/* gdscs */
+#define USB_HS_HSIC_GDSC				0
+#define PCIE0_GDSC					1
+#define PCIE1_GDSC					2
+#define USB30_GDSC					3
+
 #endif
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation