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gpio/xilinx: Use correct address when setting initial values.

PATCH In review Raphaël Teysseyre 4 participants 4 messages Jun 24, 2015 – Jul 16, 2015

Subsystems (3)
GPIO Arm/Zynq architecture Xilinx GPIO driver
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Raphaël Teysseyre

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#0 lore raw

PATCH v2 1/1 gpio/xilinx: Use correct address when setting initial values.

xgpio_save_regs() is used in this driver to setup the initial values of the registers in the hardware.

The relevant registers at that time are:
0x0 -> channel 0 data (32 bits, one for each GPIO on this channel). 0x4 -> channel 0 tri, controls in/out status for each GPIO of this channel. 0x8 -> channel 1 data
0xC -> channel 1 tri

gpio-xilinx.c defines these:
XGPIO_DATA_OFFSET (0x0)
XGPIO_TRI_OFFSET (0x4)
XGPIO_CHANNEL_OFFSET 0x8

Before this patch, the "data" register value of channel 1 was written at 0x4 intead of 0x8 (overwriting the channel 0 "tri" register), and the "tri" register value for channel 1 was written at 0x8 instead of 0xC.

Signed-off-by Rapha?l Teysseyre <[email protected]>
---
 drivers/gpio/gpio-xilinx.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)
drivers/gpio/gpio-xilinx.c +2 -2
index 61243d1..e544b7a 100644
@@ -220,9 +220,9 @@ static void xgpio_save_regs(struct of_mm_gpio_chip *mm_gc)
 	if (!chip->gpio_width[1])
 		return;
 
-	xgpio_writereg(mm_gc->regs + XGPIO_DATA_OFFSET + XGPIO_TRI_OFFSET,
+	xgpio_writereg(mm_gc->regs + XGPIO_DATA_OFFSET + XGPIO_CHANNEL_OFFSET,
 		       chip->gpio_state[1]);
-	xgpio_writereg(mm_gc->regs + XGPIO_TRI_OFFSET + XGPIO_TRI_OFFSET,
+	xgpio_writereg(mm_gc->regs + XGPIO_TRI_OFFSET + XGPIO_CHANNEL_OFFSET,
 		       chip->gpio_dir[1]);
 }
Signature · 1 line
1.7.1
Reviewed-by on v2 1/1
#1 lore raw
Quoted 28 lines · Rapha?l Teysseyre

xgpio_save_regs() is used in this driver to setup the initial values of the registers in the hardware.

The relevant registers at that time are:
0x0 -> channel 0 data (32 bits, one for each GPIO on this channel). 0x4 -> channel 0 tri, controls in/out status for each GPIO of this channel. 0x8 -> channel 1 data
0xC -> channel 1 tri

gpio-xilinx.c defines these:
XGPIO_DATA_OFFSET (0x0)
XGPIO_TRI_OFFSET (0x4)
XGPIO_CHANNEL_OFFSET 0x8

Before this patch, the "data" register value of channel 1 was written at 0x4 intead of 0x8 (overwriting the channel 0 "tri" register), and the "tri" register value for channel 1 was written at 0x8 instead of 0xC.

Signed-off-by Rapha?l Teysseyre <[email protected]>
---
 drivers/gpio/gpio-xilinx.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)
drivers/gpio/gpio-xilinx.c +0 -0
index 61243d1..e544b7a 100644

drivers/gpio/gpio-xilinx.c static void xgpio_save_regs(struct of_mm_gpio_chip *mm_gc) · line 227

Quoted 10 lines
drivers/gpio/gpio-xilinx.c +2 -2
@@ -220,9 +220,9 @@ static void xgpio_save_regs(struct of_mm_gpio_chip *mm_gc)
 	if (!chip->gpio_width[1])
 		return;
 
-	xgpio_writereg(mm_gc->regs + XGPIO_DATA_OFFSET + XGPIO_TRI_OFFSET,
+	xgpio_writereg(mm_gc->regs + XGPIO_DATA_OFFSET + XGPIO_CHANNEL_OFFSET,
 		       chip->gpio_state[1]);
-	xgpio_writereg(mm_gc->regs + XGPIO_TRI_OFFSET + XGPIO_TRI_OFFSET,
+	xgpio_writereg(mm_gc->regs + XGPIO_TRI_OFFSET + XGPIO_CHANNEL_OFFSET,
 		       chip->gpio_dir[1]);
 }
Reviewed-by Michal Simek <[email protected]>

Thanks,
Michal

Reviewed-by on v2 1/1
#2 lore raw
In reply to Raphaël Teysseyre
Quoted 9 lines · Rapha?l Teysseyre

xgpio_save_regs() is used in this driver to setup the initial values of the registers in the hardware.

The relevant registers at that time are:
0x0 -> channel 0 data (32 bits, one for each GPIO on this channel). 0x4 -> channel 0 tri, controls in/out status for each GPIO of this channel. 0x8 -> channel 1 data
0xC -> channel 1 tri

Quoted 8 lines

gpio-xilinx.c defines these:
XGPIO_DATA_OFFSET (0x0)
XGPIO_TRI_OFFSET (0x4)
XGPIO_CHANNEL_OFFSET 0x8

Before this patch, the "data" register value of channel 1 was written at 0x4 intead of 0x8 (overwriting the channel 0 "tri" register), and the "tri" register value for channel 1 was written at 0x8 instead of 0xC.

Nice, descriptive commit log. ;)

Reviewed-by Alexandre Courbot <[email protected]>
Quoted 11 lines
Signed-off-by Rapha?l Teysseyre <[email protected]>
---
 drivers/gpio/gpio-xilinx.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)
drivers/gpio/gpio-xilinx.c +0 -0
index 61243d1..e544b7a 100644

drivers/gpio/gpio-xilinx.c static void xgpio_save_regs(struct of_mm_gpio_chip *mm_gc) · line 226

Quoted 9 lines
drivers/gpio/gpio-xilinx.c +2 -2
@@ -220,9 +220,9 @@ static void xgpio_save_regs(struct of_mm_gpio_chip *mm_gc)
        if (!chip->gpio_width[1])
                return;
 
-       xgpio_writereg(mm_gc->regs + XGPIO_DATA_OFFSET + XGPIO_TRI_OFFSET,
+       xgpio_writereg(mm_gc->regs + XGPIO_DATA_OFFSET + XGPIO_CHANNEL_OFFSET,
                       chip->gpio_state[1]);
-       xgpio_writereg(mm_gc->regs + XGPIO_TRI_OFFSET + XGPIO_TRI_OFFSET,
+       xgpio_writereg(mm_gc->regs + XGPIO_TRI_OFFSET + XGPIO_CHANNEL_OFFSET,
                       chip->gpio_dir[1]);

Nit: Maybe XGPIO_CHANNEL_OFFSET should have come before the other offset for clarity, but that's no big deal.

#3 lore raw
In reply to Raphaël Teysseyre
Quoted 14 lines · Rapha?l Teysseyre

xgpio_save_regs() is used in this driver to setup the initial values of the registers in the hardware.

The relevant registers at that time are:
0x0 -> channel 0 data (32 bits, one for each GPIO on this channel). 0x4 -> channel 0 tri, controls in/out status for each GPIO of this channel. 0x8 -> channel 1 data
0xC -> channel 1 tri

gpio-xilinx.c defines these:
XGPIO_DATA_OFFSET (0x0)
XGPIO_TRI_OFFSET (0x4)
XGPIO_CHANNEL_OFFSET 0x8

Quoted 5 lines

Before this patch, the "data" register value of channel 1 was written at 0x4 intead of 0x8 (overwriting the channel 0 "tri" register), and the "tri" register value for channel 1 was written at 0x8 instead of 0xC.

Signed-off-by Rapha?l Teysseyre <[email protected]>

Patch applied with review tags.

Yours,
Linus Walleij