qcom: Add support for GDSCs
Subsystems (5)
v6 cover qcom: Add support for GDSCs
GDSCs (Global Distributed Switch Controllers) control switches that supply power to an on-chip power domain and hence can be programmed in SW to safely power collapse and restore power to the respective PDs. They are part of a considerable number of recent QCOM SoCs (This series adds support for msm8974, msm8916 and apq8084 devices) and are part of the Clock control block.
The series implements support for GDSC using the genpd framework modelling these as SW controllable power domains and uses PM clocks to control clocks within the gdsc.
* Client drivers which plan to use GDSC can refer to Documentation/devicetree/bindings/power/power_domain.txt to know how to hook up the power domain for the device through DT
* Runtime PM specific documentation can be found in Documentation/power/runtime_pm.txt
* Patches are based of 4.2-rc3
Changes since v5:
* Added support to manage clocks with !CONFIG_PM
* Added RET/OFF support
* Added support to assert/deassert reset while the GDSC is ON
Changes since v4:
* Added clock control support using PM clocks
* Included WA to enable an RCG (needed for Oxili gdsc in 8916)
Changes since v3:
* static inline'd gdsc_register/unregister stubs
* error check fixes in gdsc_register
* dropped oxili_gdsc for 8916 as its broken and needs additional WA's not part of this series
* split dts and driver changes into seperate patches
* Updated and included Stephanes patch to add gdscs to apq8084 mmcc in the series
Changes since v2:
* gdsc_unregister added
* gdsc_register/unregister introduced in patch 1/6
Changes since v1:
* added err checks for regmap apis
* added gdsc_register() in gdsc.c
Rajendra Nayak (9):
clk: qcom: gdsc: Prepare common clk probe to register gdscs
clk: qcom: gdsc: Use PM clocks to control gdsc clocks
clk: qcom: gdsc: Manage clocks with !CONFIG_PM
clk: qcom: gdsc: Enable an RCG before turing on the gdsc
clk: qcom: gdsc: Add support for Memory RET/OFF
clk: qcom: gdsc: Add support for ON only state
clk: qcom: gdsc: Add GDSCs in msm8916 GCC
clk: qcom: gdsc: Add GDSCs in apq8084 GCC
arm: dts: qcom: Add #power-domain-cells property
Stephane Viau (1):
clk: qcom: gdsc: Add GDSCs in apq8084 MMCC
Stephen Boyd (3):
clk: qcom: Add support for GDSCs
clk: qcom: gdsc: Add GDSCs in msm8974 GCC
clk: qcom: gdsc: Add GDSCs in msm8974 MMCC
arch/arm/boot/dts/qcom-apq8084.dtsi | 1 + arch/arm/boot/dts/qcom-msm8974.dtsi | 2 + arch/arm64/boot/dts/qcom/msm8916.dtsi | 1 + drivers/clk/qcom/Kconfig | 10 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/common.c | 17 +- drivers/clk/qcom/common.h | 2 + drivers/clk/qcom/gcc-apq8084.c | 42 ++++ drivers/clk/qcom/gcc-msm8916.c | 52 ++++ drivers/clk/qcom/gcc-msm8974.c | 15 ++ drivers/clk/qcom/gdsc.c | 343 ++++++++++++++++++++++++++ drivers/clk/qcom/gdsc.h | 72 ++++++ drivers/clk/qcom/mmcc-apq8084.c | 68 ++++- drivers/clk/qcom/mmcc-msm8974.c | 72 ++++++ include/dt-bindings/clock/qcom,gcc-apq8084.h | 6 + include/dt-bindings/clock/qcom,gcc-msm8916.h | 8 + include/dt-bindings/clock/qcom,gcc-msm8974.h | 3 + include/dt-bindings/clock/qcom,mmcc-apq8084.h | 8 + include/dt-bindings/clock/qcom,mmcc-msm8974.h | 8 + 19 files changed, 729 insertions(+), 2 deletions(-) create mode 100644 drivers/clk/qcom/gdsc.c create mode 100644 drivers/clk/qcom/gdsc.h
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
PATCH v6 1/13 clk: qcom: Add support for GDSCs
From: Stephen Boyd <[email protected]>
GDSCs (Global Distributed Switch Controllers) are responsible for safely collapsing and restoring power to peripherals in the SoC. These are best modelled as power domains using genpd and given the registers are scattered throughout the clock controller register space, its best to have the support added through the clock driver.
--- drivers/clk/qcom/Kconfig | 5 ++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gdsc.c | 167 ++++++++++++++++++++++++++++++++++++++++++++++ drivers/clk/qcom/gdsc.h | 45 +++++++++++++ 4 files changed, 218 insertions(+) create mode 100644 drivers/clk/qcom/gdsc.c create mode 100644 drivers/clk/qcom/gdsc.h
drivers/clk/qcom/Kconfig +5 -0
@@ -39,6 +39,11 @@ config IPQ_LCC_806X Say Y if you want to use audio devices such as i2s, pcm, S/PDIF, etc. +config QCOM_GDSC + bool + select PM_GENERIC_DOMAINS if PM + depends on COMMON_CLK_QCOM + config MSM_GCC_8660 tristate "MSM8660 Global Clock Controller" depends on COMMON_CLK_QCOM
drivers/clk/qcom/Makefile +1 -0
@@ -9,6 +9,7 @@ clk-qcom-y += clk-branch.o clk-qcom-y += clk-regmap-divider.o clk-qcom-y += clk-regmap-mux.o clk-qcom-y += reset.o +clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o
drivers/clk/qcom/gdsc.c new file +167 -0
167 lines not on this page · raw message
drivers/clk/qcom/gdsc.h new file +45 -0
45 lines not on this page · raw message
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
PATCH v6 1/13 clk: qcom: Add support for GDSCs
drivers/clk/qcom/Kconfig config IPQ_LCC_806X · line 46
Quoted 13 lines · Rajendra Nayak
drivers/clk/qcom/Kconfig +4
-0@@ -39,6 +39,11 @@ config IPQ_LCC_806X Say Y if you want to use audio devices such as i2s, pcm, S/PDIF, etc. +config QCOM_GDSC + bool + select PM_GENERIC_DOMAINS if PM + depends on COMMON_CLK_QCOM
We can drop this depends because it should only be selected if COMMON_CLK_QCOM anyway.
Quoted 17 lines
drivers/clk/qcom/Kconfig +1
-0+ config MSM_GCC_8660 tristate "MSM8660 Global Clock Controller"depends on
COMMON_CLK_QCOMdrivers/clk/qcom/gdsc.c new file +7
-0@@ -0,0 +1,167 @@ +/* +* Copyright (c) 2015, The Linux Foundation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 and +* only version 2 as published by the Free Software Foundation. +*
drivers/clk/qcom/gdsc.c line 17
Quoted 10 lines
drivers/clk/qcom/gdsc.c new file +10
-0+* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/jiffies.h> +#include <linux/slab.h>
#include <linux/bitops.h> for BIT?
#include <linux/kernel.h> for container_of?
Please include linux/pm_domain.h here and linux/regmap.h as well for completeness even though gdsc.h includes it.
Quoted 23 lines
drivers/clk/qcom/gdsc.c new file +22
-0+#include "gdsc.h" + +#define PWR_ON_MASK BIT(31) +#define EN_REST_WAIT_MASK GENMASK(23, 20) +#define EN_FEW_WAIT_MASK GENMASK(19, 16) +#define CLK_DIS_WAIT_MASK GENMASK(15, 12) +#define SW_OVERRIDE_MASK BIT(2) +#define HW_CONTROL_MASK BIT(1) +#define SW_COLLAPSE_MASK BIT(0) + +static int gdsc_toggle_logic (struct gdsc *sc,bool en) +{ +int ret; +u32 val = en ?0 :SW_COLLAPSE_MASK ; +u32 check = en ?PWR_ON_MASK :0 ; +unsigned long timeout; + + ret =regmap_update_bits (sc->regmap, sc->gdscr,SW_COLLAPSE_MASK , val); +if (ret) +return ret; + + timeout = jiffies +usecs_to_jiffies (TIMEOUT_US );
drivers/clk/qcom/gdsc.c line 70
Quoted 10 lines
drivers/clk/qcom/gdsc.c new file +10
-0+do { + ret =regmap_read (sc->regmap, sc->gdscr, &val); +if (ret) +return ret; + +if ((val &PWR_ON_MASK ) == check) +return 0 ; + }while (time_before (jiffies, timeout)); + + ret =regmap_read (sc->regmap, sc->gdscr, &val);
Weird double space here.
Quoted 29 lines
drivers/clk/qcom/gdsc.c new file +28
-0+if (ret) +return ret; + +if ((val &PWR_ON_MASK ) == check) +return 0 ; + +return -ETIMEDOUT ; +} + + +int gdsc_register (struct device *dev,struct gdsc **scs,size_t num, +struct regmap *regmap) +{ +int i, ret; +struct genpd_onecell_data *data; + + data =devm_kzalloc (dev,sizeof (*data),GFP_KERNEL ); +if (!data) +return -ENOMEM ; + + data->domains =devm_kcalloc (dev, num,sizeof (*data->domains), +GFP_KERNEL ); +if (!data->domains) +return -ENOMEM ; + + data->num_domains = num; +for (i =0 ; i < num; i++) { +if (!scs[i])
drivers/clk/qcom/gdsc.c line 162
Quoted 10 lines
drivers/clk/qcom/gdsc.c new file +10
-0+continue ; + scs[i]->regmap = regmap; + ret =gdsc_init (scs[i]); +if (ret) +return ret; + data->domains[i] = &scs[i]->pd; + } + +return of_genpd_add_provider_onecell (dev->of_node, data); +}
EXPORT_SYMBOL?
drivers/clk/qcom/gdsc.c line 167
Quoted 5 lines
drivers/clk/qcom/gdsc.c new file +5
-0+ +void gdsc_unregister (struct device *dev) +{ +of_genpd_del_provider (dev->of_node); +}
EXPORT_SYMBOL?
Quoted 14 lines
drivers/clk/qcom/gdsc.h new file +8
-0@@ -0,0 +1,45 @@ +/* +* Copyright (c) 2015, The Linux Foundation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 and +* only version 2 as published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful,
drivers/clk/qcom/gdsc.h line 18
Quoted 10 lines
drivers/clk/qcom/gdsc.h new file +10
-0+* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +#ifndef __QCOM_GDSC_H__ +#define __QCOM_GDSC_H__ + +#include <linux/pm_domain.h> +#include <linux/regmap.h>
Drop this include and forward declare struct regmap.
Quoted 11 lines
drivers/clk/qcom/gdsc.h new file +11
-0+ +/** +* struct gdsc - Globally Distributed Switch Controller +* @pd: generic power domain +* @regmap: regmap for MMIO accesses +* @gdscr: gsdc control register +*/ +struct gdsc { +struct generic_pm_domain pd; +struct regmap *regmap; +unsigned int gdscr;
drivers/clk/qcom/gdsc.h line 39
Quoted 10 lines
drivers/clk/qcom/gdsc.h new file +10
-0+}; + +#ifdef CONFIG_QCOM_GDSC +int gdsc_register (struct device *,struct gdsc **,size_t n,struct regmap *); +void gdsc_unregister (struct device *); +#else +static inline int gdsc_register (struct device *d,struct gdsc **g,size_t n, +struct regmap *r) +{ +return -ENOSYS ;
We need err.h for this one...
drivers/clk/qcom/gdsc.h line 43
Quoted 4 lines
drivers/clk/qcom/gdsc.h new file +4
-0+} + +static inline void gdsc_unregister (struct device *d) +{};
one line instead of two for this?
Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH v6 1/13 clk: qcom: Add support for GDSCs
Quoted 16 lines · Stephen Boyd
drivers/clk/qcom/Kconfig config IPQ_LCC_806X · line 45
Quoted 12 lines · Rajendra Nayak
drivers/clk/qcom/Kconfig +4
-0@@ -39,6 +39,11 @@ config IPQ_LCC_806X Say Y if you want to use audio devices such as i2s, pcm, S/PDIF, etc. +config QCOM_GDSC + bool + select PM_GENERIC_DOMAINS if PM + depends on COMMON_CLK_QCOMWe can drop this depends because it should only be selected if
COMMON_CLK_QCOManyway.
Stephen, thanks for the review. I'll fix up this and others you pointed to in this patch and others in the series.
PATCH v6 1/13 clk: qcom: Add support for GDSCs
In reply to Stephen Boyd<snip>
Quoted 32 lines
Quoted 19 lines
drivers/clk/qcom/gdsc.c new file +19
-0+ +int gdsc_register (struct device *dev,struct gdsc **scs,size_t num, +struct regmap *regmap) +{ +int i, ret; +struct genpd_onecell_data *data; + + data =devm_kzalloc (dev,sizeof (*data),GFP_KERNEL ); +if (!data) +return -ENOMEM ; + + data->domains =devm_kcalloc (dev, num,sizeof (*data->domains), +GFP_KERNEL ); +if (!data->domains) +return -ENOMEM ; + + data->num_domains = num; +for (i =0 ; i < num; i++) { +if (!scs[i])drivers/clk/qcom/gdsc.c line 162
Quoted 10 lines
drivers/clk/qcom/gdsc.c new file +10
-0+continue ; + scs[i]->regmap = regmap; + ret =gdsc_init (scs[i]); +if (ret) +return ret; + data->domains[i] = &scs[i]->pd; + } + +return of_genpd_add_provider_onecell (dev->of_node, data); +}
EXPORT_SYMBOL?
Quoted 7 lines
drivers/clk/qcom/gdsc.c line 167
Quoted 5 lines
drivers/clk/qcom/gdsc.c new file +5
-0+ +void gdsc_unregister (struct device *dev) +{ +of_genpd_del_provider (dev->of_node); +}
EXPORT_SYMBOL?
Stephen, gdsc_register/unregister are internal to the qcom clk driver why to export them?
Signature · 2 lines
regards, Stan
PATCH v6 1/13 clk: qcom: Add support for GDSCs
Quoted 12 lines · Stanimir Varbanov
<snip>
Quoted 7 lines
drivers/clk/qcom/gdsc.c new file +5
-0+ +void gdsc_unregister (struct device *dev) +{ +of_genpd_del_provider (dev->of_node); +}
EXPORT_SYMBOL?Stephen, gdsc_register/unregister are internal to the qcom clk driver why to export them?
Ah, I thought this was being called from outside the clk-qcom.ko module. As long as we don't call them from a SoC specific driver then it should be ok to leave them unexported. Perhaps we should remove the export on qcom_find_freq() too?
Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH v6 2/13 clk: qcom: gdsc: Prepare common clk probe to register gdscs
In reply to Rajendra NayakThe common clk probe registers a clk provider and a reset controller. Update it to register a genpd provider using the gdsc data provided by each platform.
--- drivers/clk/qcom/common.c | 16 +++++++++++++++- drivers/clk/qcom/common.h | 2 ++ 2 files changed, 17 insertions(+), 1 deletion(-)
drivers/clk/qcom/common.c +15 -1
@@ -21,6 +21,7 @@#include "clk-rcg.h" #include "clk-regmap.h" #include "reset.h" +#include "gdsc.h" struct qcom_cc {struct qcom_reset_controller reset;
@@ -120,8 +121,20 @@ int qcom_cc_really_probe(struct platform_device *pdev, ret =reset_controller_register (&reset->rcdev);if (ret) -of_clk_del_provider (dev->of_node); + goto err_reset; +if (desc->gdscs && desc->num_gdscs) { + ret =gdsc_register (dev, desc->gdscs, desc->num_gdscs, regmap); +if (ret) + goto err_pd; + } + +return 0 ; +err_pd: +dev_err (dev,"Failed to register power domains\n" ); +reset_controller_unregister (&reset->rcdev); +err_reset: +of_clk_del_provider (dev->of_node);return ret; }EXPORT_SYMBOL_GPL (qcom_cc_really_probe);
@@ -140,6 +153,7 @@ EXPORT_SYMBOL_GPL(qcom_cc_probe);void qcom_cc_remove (struct platform_device *pdev) { +gdsc_unregister (&pdev->dev);of_clk_del_provider (pdev->dev.of_node);reset_controller_unregister (platform_get_drvdata (pdev)); }
drivers/clk/qcom/common.h +2 -0
@@ -28,6 +28,8 @@ struct qcom_cc_desc {size_t num_clks;const struct qcom_reset_map *resets;size_t num_resets; +struct gdsc **gdscs; +size_t num_gdscs; }; extern const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f,
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
PATCH v6 2/13 clk: qcom: gdsc: Prepare common clk probe to register gdscs
Quoted 6 lines · Rajendra Nayak
drivers/clk/qcom/common.c +1
-1@@ -120,8 +121,20 @@ int qcom_cc_really_probe(struct platform_device *pdev, ret =reset_controller_register (&reset->rcdev);if (ret) -of_clk_del_provider (dev->of_node); + goto err_reset;
drivers/clk/qcom/common.c int qcom_cc_really_probe(struct platform_device *pdev, · line 134
Quoted 10 lines
drivers/clk/qcom/common.c +9
-0+if (desc->gdscs && desc->num_gdscs) { + ret =gdsc_register (dev, desc->gdscs, desc->num_gdscs, regmap); +if (ret) + goto err_pd; + } + +return 0 ; +err_pd: +dev_err (dev,"Failed to register power domains\n" );
Let's just stay silent like we've been doing before.
Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH v6 3/13 clk: qcom: gdsc: Use PM clocks to control gdsc clocks
In reply to Rajendra NayakThe devices within a gdsc power domain, quite often have additional clocks to be turned on/off along with the power domain itself. Once the drivers for these devices are converted to use runtime PM, it would be possible to remove all clock handling from the drivers if the gdsc driver can handle it.
Use PM clocks to add support for this. A list of con_ids[] specified per gdsc would be the clocks turned on/off on every device start/stop callbacks.
--- drivers/clk/qcom/gdsc.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+)
drivers/clk/qcom/gdsc.c +35 -0
@@ -14,6 +14,7 @@#include <linux/delay.h> #include <linux/err.h> #include <linux/jiffies.h> +#include <linux/pm_clock.h> #include <linux/slab.h> #include "gdsc.h"
@@ -104,6 +105,37 @@ static int gdsc_disable(struct generic_pm_domain *domain)return gdsc_toggle_logic (sc, false); } +static int gdsc_attach (struct generic_pm_domain *domain,struct device *dev) +{ +int ret; +struct gdsc *sc =domain_to_gdsc (domain); +char **con_id, *con_ids[] = {"core" ,"iface" ,NULL }; + + ret =pm_clk_create (dev); +if (ret) { +dev_err (dev,"pm_clk_create failed %d\n" , ret); +return ret; + } + +for (con_id = con_ids; *con_id; con_id++) { + ret =pm_clk_add (dev, *con_id); +if (ret) { +dev_err (dev,"pm_clk_add failed %d\n" , ret); + goto fail; + } + } +return 0 ; +fail: +pm_clk_destroy (dev); +return ret; +}; + +static void gdsc_detach (struct generic_pm_domain *domain,struct device *dev) +{ +pm_clk_destroy (dev); +return ; +}; +static int gdsc_init (struct gdsc *sc) {u32 mask, val;
@@ -127,6 +159,9 @@ static int gdsc_init(struct gdsc *sc) sc->pd.power_off = gdsc_disable; sc->pd.power_on = gdsc_enable; + sc->pd.attach_dev = gdsc_attach; + sc->pd.detach_dev = gdsc_detach; + sc->pd.flags =GENPD_FLAG_PM_CLK ;pm_genpd_init (&sc->pd,NULL , !on);return 0 ;
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
PATCH v6 3/13 clk: qcom: gdsc: Use PM clocks to control gdsc clocks
drivers/clk/qcom/gdsc.c static int gdsc_disable(struct generic_pm_domain *domain) · line 112
Quoted 9 lines · Rajendra Nayak
drivers/clk/qcom/gdsc.c +5
-0@@ -104,6 +105,37 @@ static int gdsc_disable(struct generic_pm_domain *domain)return gdsc_toggle_logic (sc, false); } +static int gdsc_attach (struct generic_pm_domain *domain,struct device *dev) +{ +int ret; +struct gdsc *sc =domain_to_gdsc (domain); +char **con_id, *con_ids[] = {"core" ,"iface" ,NULL };
const?
This is where I get scared of sniffing too much SoC glue. What's to enforce the "core", and "iface" naming scheme? What's to enforce there being two clocks vs. one? Maybe a better approach would be to use of_clk_get() and iterate through all clocks of the device, or to encode the clock names in the gdsc structure.
The problem I'm getting at is that we're going through the consumer struct device's mapping of names to clks when we're inside this SoC glue code that has to know about what the consumer has decided to do. This code becomes tightly coupled with that decision that doesn't seem to be under the glue code's control. Using of_clk_get() sidesteps that problem, with the loss of flexibility of deciding which clock does what so at least it's a step in the right direction. But if we want to control individual clocks then we have to know which clock is which. Maybe we should associate clk_hw pointers with the gdscs and then export __clk_hw_create_clk() so that drivers can turn clk_hw pointers into clocks?
drivers/clk/qcom/gdsc.c static int gdsc_disable(struct generic_pm_domain *domain) · line 116
Quoted 4 lines
drivers/clk/qcom/gdsc.c +4
-0+ + ret =pm_clk_create (dev); +if (ret) { +dev_err (dev,"pm_clk_create failed %d\n" , ret);
Who cares? debug?
drivers/clk/qcom/gdsc.c static int gdsc_disable(struct generic_pm_domain *domain) · line 123
Quoted 7 lines
drivers/clk/qcom/gdsc.c +7
-0+return ret; + } + +for (con_id = con_ids; *con_id; con_id++) { + ret =pm_clk_add (dev, *con_id); +if (ret) { +dev_err (dev,"pm_clk_add failed %d\n" , ret);
Who cares? debug?
drivers/clk/qcom/gdsc.c static int gdsc_disable(struct generic_pm_domain *domain) · line 136
Quoted 13 lines
drivers/clk/qcom/gdsc.c +13
-0+ goto fail; + } + } +return 0 ; +fail: +pm_clk_destroy (dev); +return ret; +}; + +static void gdsc_detach (struct generic_pm_domain *domain,struct device *dev) +{ +pm_clk_destroy (dev); +return ;
useless return
Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH v6 3/13 clk: qcom: gdsc: Use PM clocks to control gdsc clocks
Quoted 14 lines · Stephen Boyd
drivers/clk/qcom/gdsc.c static int gdsc_disable(struct generic_pm_domain · line 113
Quoted 10 lines · Rajendra Nayak
drivers/clk/qcom/gdsc.c +5
-0@@ -104,6 +105,37 @@ static int gdsc_disable(struct generic_pm_domain *domain)return gdsc_toggle_logic (sc, false); } +static int gdsc_attach (struct generic_pm_domain *domain,struct device *dev) +{ +int ret; +struct gdsc *sc =domain_to_gdsc (domain); +char **con_id, *con_ids[] = {"core" ,"iface" ,NULL };const?
Quoted 5 lines
This is where I get scared of sniffing too much SoC glue. What's to enforce the "core", and "iface" naming scheme? What's to enforce there being two clocks vs. one? Maybe a better approach would be to use
of_clk_get()and iterate through all clocks of the device, or to encode the clock names in the gdsc structure.
I had the clock names in the gdsc structure in v5. I should probably go back to having it that way.
PATCH v6 3/13 clk: qcom: gdsc: Use PM clocks to control gdsc clocks
Quoted 15 lines · Rajendra Nayak
Quoted 14 lines · Stephen Boyd
drivers/clk/qcom/gdsc.c static int gdsc_disable(struct generic_pm_domain · line 113
Quoted 10 lines · Rajendra Nayak
drivers/clk/qcom/gdsc.c +5
-0@@ -104,6 +105,37 @@ static int gdsc_disable(struct generic_pm_domain *domain)return gdsc_toggle_logic (sc, false); } +static int gdsc_attach (struct generic_pm_domain *domain,struct device *dev) +{ +int ret; +struct gdsc *sc =domain_to_gdsc (domain); +char **con_id, *con_ids[] = {"core" ,"iface" ,NULL };const?
Quoted 8 lines
Quoted 5 lines
This is where I get scared of sniffing too much SoC glue. What's to enforce the "core", and "iface" naming scheme? What's to enforce there being two clocks vs. one? Maybe a better approach would be to use
of_clk_get()and iterate through all clocks of the device, or to encode the clock names in the gdsc structure.I had the clock names in the gdsc structure in v5. I should probably go back to having it that way.
Rajendra, If you decide to go back please look at that comment [1], as well.
Signature · 4 lines
regards, Stan [1] http://www.spinics.net/lists/linux-arm-msm/msg15040.html
PATCH v6 3/13 clk: qcom: gdsc: Use PM clocks to control gdsc clocks
Quoted 22 lines · Stanimir Varbanov
Quoted 21 lines · Rajendra Nayak
Quoted 19 lines · Stephen Boyd
drivers/clk/qcom/gdsc.c static int gdsc_disable(struct generic_pm_domain · line 113
Quoted 10 lines · Rajendra Nayak
drivers/clk/qcom/gdsc.c +5
-0@@ -104,6 +105,37 @@ static int gdsc_disable(struct generic_pm_domain *domain)return gdsc_toggle_logic (sc, false); } +static int gdsc_attach (struct generic_pm_domain *domain,struct device *dev) +{ +int ret; +struct gdsc *sc =domain_to_gdsc (domain); +char **con_id, *con_ids[] = {"core" ,"iface" ,NULL };const?
This is where I get scared of sniffing too much SoC glue. What's to enforce the "core", and "iface" naming scheme? What's to enforce there being two clocks vs. one? Maybe a better approach would be to use
of_clk_get()and iterate through all clocks of the device, or to encode the clock names in the gdsc structure.
Quoted 4 lines
Quoted 2 lines
I had the clock names in the gdsc structure in v5. I should probably go back to having it that way.
Rajendra, If you decide to go back please look at that comment [1], as well.
yes, thanks, I will.
PATCH v6 4/13 clk: qcom: gdsc: Manage clocks with !CONFIG_PM
In reply to Rajendra NayakWith CONFIG_PM disabled, turn the devices clocks on during driver binding to the device, and turn them off when the driver is unbound from the device.
--- drivers/clk/qcom/gdsc.c | 59 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+)
drivers/clk/qcom/gdsc.c +59 -0
@@ -16,6 +16,7 @@#include <linux/jiffies.h> #include <linux/pm_clock.h> #include <linux/slab.h> +#include <linux/platform_device.h> #include "gdsc.h" #define PWR_ON_MASK BIT(31)
@@ -200,3 +201,61 @@ void gdsc_unregister(struct device *dev) {of_genpd_del_provider (dev->of_node); } + +#ifndef CONFIG_PM +static void enable_clock (struct device *dev,const char *con_id) +{ +struct clk *clk; + + clk =clk_get (dev, con_id); +if (!IS_ERR (clk)) { +clk_prepare_enable (clk); +clk_put (clk); + } +} + +static void disable_clock (struct device *dev,const char *con_id) +{ +struct clk *clk; + + clk =clk_get (dev, con_id); +if (!IS_ERR (clk)) { +clk_disable_unprepare (clk); +clk_put (clk); + } +} + +static int clk_notify (struct notifier_block *nb,unsigned long action, +void *data) +{ +int sz; +struct device *dev = data; +char **con_id, *con_ids[] = {"core" ,"iface" ,NULL }; + +if (!of_find_property (dev->of_node,"power-domains" , &sz)) +return 0 ; + +switch (action) { +case BUS_NOTIFY_BIND_DRIVER : +for (con_id = con_ids; *con_id; con_id++) +enable_clock (dev, *con_id); +break ; +case BUS_NOTIFY_UNBOUND_DRIVER : +for (con_id = con_ids; *con_id; con_id++) +disable_clock (dev, *con_id); +break ; + } +return 0 ; +} + +struct notifier_block nb = { + .notifier_call = clk_notify, +}; + +int qcom_pm_runtime_init (void ) +{ +bus_register_notifier (&platform_bus_type, &nb); +return 0 ; +} +core_initcall (qcom_pm_runtime_init); +#endif
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PATCH v6 4/13 clk: qcom: gdsc: Manage clocks with !CONFIG_PM
Quoted 14 lines · Rajendra Nayak
With
CONFIG_PMdisabled, turn the devices clocks on during driver binding to the device, and turn them off when the driver is unbound from the device.Signed-off-by Rajendra Nayak <[email protected]>--- drivers/clk/qcom/gdsc.c | 59 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+)drivers/clk/qcom/gdsc.c +0
-0
drivers/clk/qcom/gdsc.c line 19
Quoted 4 lines
drivers/clk/qcom/gdsc.c +1
-0@@ -16,6 +16,7 @@#include <linux/jiffies.h> #include <linux/pm_clock.h> #include <linux/slab.h> +#include <linux/platform_device.h>
#include <linux/clk.h>?
Quoted 20 lines
drivers/clk/qcom/gdsc.c +13
-0#include "gdsc.h" #define PWR_ON_MASK BIT(31)@@ -200,3 +201,61 @@ void gdsc_unregister(struct device *dev) {of_genpd_del_provider (dev->of_node); } + +#ifndef CONFIG_PM +static void enable_clock (struct device *dev,const char *con_id) +{ +struct clk *clk; + + clk =clk_get (dev, con_id); +if (!IS_ERR (clk)) { +clk_prepare_enable (clk); +clk_put (clk); + } +} +
drivers/clk/qcom/gdsc.c void gdsc_unregister(struct device *dev) · line 226
Quoted 10 lines
drivers/clk/qcom/gdsc.c +10
-0+static void disable_clock (struct device *dev,const char *con_id) +{ +struct clk *clk; + + clk =clk_get (dev, con_id); +if (!IS_ERR (clk)) { +clk_disable_unprepare (clk); +clk_put (clk); + } +}
Is there a reason why this whole patch isn't generic code? I recall some discussion but I forgot now and there isn't any mention of why this isn't generic code in the commit text.
drivers/clk/qcom/gdsc.c void gdsc_unregister(struct device *dev) · line 233
Quoted 7 lines
drivers/clk/qcom/gdsc.c +7
-0+ +static int clk_notify (struct notifier_block *nb,unsigned long action, +void *data) +{ +int sz; +struct device *dev = data; +char **con_id, *con_ids[] = {"core" ,"iface" ,NULL };
This again?
Quoted 8 lines
drivers/clk/qcom/gdsc.c +8
-0+ +if (!of_find_property (dev->of_node,"power-domains" , &sz)) +return 0 ; + +switch (action) { +case BUS_NOTIFY_BIND_DRIVER : +for (con_id = con_ids; *con_id; con_id++) +enable_clock (dev, *con_id);
drivers/clk/qcom/gdsc.c void gdsc_unregister(struct device *dev) · line 251
Quoted 10 lines
drivers/clk/qcom/gdsc.c +10
-0+break ; +case BUS_NOTIFY_UNBOUND_DRIVER : +for (con_id = con_ids; *con_id; con_id++) +disable_clock (dev, *con_id); +break ; + } +return 0 ; +} + +struct notifier_block nb = {
static?
drivers/clk/qcom/gdsc.c void gdsc_unregister(struct device *dev) · line 255
Quoted 4 lines
drivers/clk/qcom/gdsc.c +4
-0+ .notifier_call = clk_notify, +}; + +int qcom_pm_runtime_init (void )
static? __init?
drivers/clk/qcom/gdsc.c void gdsc_unregister(struct device *dev) · line 258
Quoted 3 lines
drivers/clk/qcom/gdsc.c +3
-0+{ +bus_register_notifier (&platform_bus_type, &nb); +return 0 ;
return bus_register_notifier()?
Quoted 3 lines
drivers/clk/qcom/gdsc.c +3
-0+} +core_initcall (qcom_pm_runtime_init); +#endif
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PATCH v6 4/13 clk: qcom: gdsc: Manage clocks with !CONFIG_PM
[]..
Quoted 19 lines
Quoted 19 lines
drivers/clk/qcom/gdsc.c +19
-0+ +#ifndef CONFIG_PM +static void enable_clock (struct device *dev,const char *con_id) +{ +struct clk *clk; + + clk =clk_get (dev, con_id); +if (!IS_ERR (clk)) { +clk_prepare_enable (clk); +clk_put (clk); + } +} + +static void disable_clock (struct device *dev,const char *con_id) +{ +struct clk *clk; + + clk =clk_get (dev, con_id); +if (!IS_ERR (clk)) {
Quoted 8 lines
drivers/clk/qcom/gdsc.c void gdsc_unregister(struct device *dev) · line 226
Quoted 4 lines
drivers/clk/qcom/gdsc.c +4
-0+clk_disable_unprepare (clk); +clk_put (clk); + } +}Is there a reason why this whole patch isn't generic code? I recall some discussion but I forgot now and there isn't any mention of why this isn't generic code in the commit text.
If by generic code, you mean using PM clocks, then this thread should give some context..
http://www.spinics.net/lists/arm-kernel/msg414072.html
PATCH v6 4/13 clk: qcom: gdsc: Manage clocks with !CONFIG_PM
Quoted 30 lines · Rajendra Nayak
[]..
Quoted 19 lines
Quoted 19 lines
drivers/clk/qcom/gdsc.c +19
-0+ +#ifndef CONFIG_PM +static void enable_clock (struct device *dev,const char *con_id) +{ +struct clk *clk; + + clk =clk_get (dev, con_id); +if (!IS_ERR (clk)) { +clk_prepare_enable (clk); +clk_put (clk); + } +} + +static void disable_clock (struct device *dev,const char *con_id) +{ +struct clk *clk; + + clk =clk_get (dev, con_id); +if (!IS_ERR (clk)) {Quoted 8 lines
drivers/clk/qcom/gdsc.c void gdsc_unregister(struct device *dev) · line 226
Quoted 4 lines
drivers/clk/qcom/gdsc.c +4
-0+clk_disable_unprepare (clk); +clk_put (clk); + } +}Is there a reason why this whole patch isn't generic code? I recall some discussion but I forgot now and there isn't any mention of why this isn't generic code in the commit text.
Quoted 3 lines
If by generic code, you mean using PM clocks, then this thread should give some context..
http://www.spinics.net/lists/arm-kernel/msg414072.html
Sorry, I read the thread and I tried to understand what was going on but I'm still lost. Can you clarify further in the commit text somehow?
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PATCH v6 4/13 clk: qcom: gdsc: Manage clocks with !CONFIG_PM
Quoted 31 lines · Stephen Boyd
Quoted 30 lines · Rajendra Nayak
[]..
Quoted 27 lines
Quoted 13 lines
drivers/clk/qcom/gdsc.c +13
-0+ +#ifndef CONFIG_PM +static void enable_clock (struct device *dev,const char *con_id) +{ +struct clk *clk; + + clk =clk_get (dev, con_id); +if (!IS_ERR (clk)) { +clk_prepare_enable (clk); +clk_put (clk); + } +} +drivers/clk/qcom/gdsc.c void gdsc_unregister(struct device *dev) · line 226
Quoted 10 lines
drivers/clk/qcom/gdsc.c +10
-0+static void disable_clock (struct device *dev,const char *con_id) +{ +struct clk *clk; + + clk =clk_get (dev, con_id); +if (!IS_ERR (clk)) { +clk_disable_unprepare (clk); +clk_put (clk); + } +}Is there a reason why this whole patch isn't generic code? I recall some discussion but I forgot now and there isn't any mention of why this isn't generic code in the commit text.
Quoted 6 lines
Quoted 3 lines
If by generic code, you mean using PM clocks, then this thread should give some context..
http://www.spinics.net/lists/arm-kernel/msg414072.htmlSorry, I read the thread and I tried to understand what was going on but I'm still lost. Can you clarify further in the commit text somehow?
So I can add this in the commit text, if it seems fine
"The use of pm_clk_add_notifier() isn't appropriate here since we need to only manage clocks with valid power domain associations done via DT, instead of what pm_clk_add_notifier() does, which is manage clocks for all on SoC/off SoC devices associating all of them to a dummy power domain instead"
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PATCH v6 4/13 clk: qcom: gdsc: Manage clocks with !CONFIG_PM
Quoted 6 lines · Rajendra Nayak
Quoted 3 lines · Stephen Boyd
Sorry, I read the thread and I tried to understand what was going on but I'm still lost. Can you clarify further in the commit text somehow?
Quoted 8 lines
So I can add this in the commit text, if it seems fine
"The use of
pm_clk_add_notifier()isn't appropriate here since we need to only manage clocks with valid power domain associations done via DT, instead of whatpm_clk_add_notifier()does, which is manage clocks for all on SoC/off SoC devices associating all of them to a dummy power domain instead"
Yes that's good, thanks. But I still wonder why the code isn't generic so that we don't have lots of drivers duplicating the same logic. I guess we can consolidate another day.
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PATCH v6 4/13 clk: qcom: gdsc: Manage clocks with !CONFIG_PM
Quoted 18 lines · Rajendra Nayak
Quoted 7 lines · Stephen Boyd
Quoted 2 lines
Sorry, I read the thread and I tried to understand what was going on
but
Quoted 1 line
I'm still lost. Can you clarify further in the commit text somehow?
Quoted 8 lines
So I can add this in the commit text, if it seems fine
"The use of
pm_clk_add_notifier()isn't appropriate here since we need to only manage clocks with valid power domain associations done via DT, instead of whatpm_clk_add_notifier()does, which is manage clocks for all on SoC/off SoC devices associating all of them to a dummy power domain instead"
Quoted 3 lines
Yes that's good, thanks. But I still wonder why the code isn't generic so that we don't have lots of drivers duplicating the same logic. I guess we can consolidate another day.
Yes, the code is quite generic and probably needs to be some place so it can be resued across drivers. For now I don;t see anyone else needing it, maybe sh mobile might plan to use something like it at a later time which is when we should probably consolidate.
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PATCH v6 5/13 clk: qcom: gdsc: Enable an RCG before turing on the gdsc
In reply to Rajendra NayakSome gdsc instances require a certain root clock (RCG) to be turned on *before* the power domain itself can be turned on. Handle this as part of the gdsc enable/disable callbacks.
--- drivers/clk/qcom/gdsc.c | 20 +++++++++++++++++++- drivers/clk/qcom/gdsc.h | 5 +++++ 2 files changed, 24 insertions(+), 1 deletion(-)
drivers/clk/qcom/gdsc.c +19 -1
@@ -84,6 +84,9 @@ static int gdsc_enable(struct generic_pm_domain *domain)struct gdsc *sc =domain_to_gdsc (domain);int ret; +if (sc->root_clk) +clk_prepare_enable (sc->root_clk); + ret =gdsc_toggle_logic (sc, true);if (ret)return ret;
@@ -101,9 +104,15 @@ static int gdsc_enable(struct generic_pm_domain *domain)static int gdsc_disable (struct generic_pm_domain *domain) { +int ret;struct gdsc *sc =domain_to_gdsc (domain); -return gdsc_toggle_logic (sc, false); + ret =gdsc_toggle_logic (sc, false); + +if (sc->root_clk) +clk_disable_unprepare (sc->root_clk); + +return ret; }static int gdsc_attach (struct generic_pm_domain *domain,struct device *dev)
@@ -125,6 +134,15 @@ static int gdsc_attach(struct generic_pm_domain *domain, struct device *dev) goto fail; } } + +if (sc->root_con_id) { + sc->root_clk =clk_get (dev, sc->root_con_id); +if (IS_ERR (sc->root_clk)) { +dev_err (dev,"failed to get root clock\n" ); +return PTR_ERR (sc->root_clk); + } + } +return 0 ; fail:pm_clk_destroy (dev);
drivers/clk/qcom/gdsc.h +5 -0
@@ -14,6 +14,7 @@#ifndef __QCOM_GDSC_H__#define __QCOM_GDSC_H__ +#include <linux/clk.h> #include <linux/pm_domain.h> #include <linux/regmap.h>
@@ -22,11 +23,15 @@* @pd: generic power domain * @regmap: regmap for MMIO accesses * @gdscr: gsdc control register +* @root_con_id: root clock to be enabled +* @root_clk: clk handle for the root clk */ struct gdsc {struct generic_pm_domain pd;struct regmap *regmap;unsigned int gdscr; +char *root_con_id; +struct clk *root_clk; };#ifdef CONFIG_QCOM_GDSC
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PATCH v6 6/13 clk: qcom: gdsc: Add support for Memory RET/OFF
In reply to Rajendra NayakAlong with the GDSC power switch, there is additional control to either retain all memory (core and peripheral) within a given powerdomain or to turn them off while the GDSC is powered down. Add support for these by modelling a RET state where all
memory is retained and an OFF state where all memory gets turned off.
The controls provided are granular enough to be able to support various differnt levels of RET states, like a 'shallow RET' with all memory retained and a 'deep RET' with some memory retained while some others are lost. The current patch does not support this and considers just one RET state where all memory is retained. Futher work, if needed can support multiple different levels of RET state.
--- drivers/clk/qcom/gdsc.c | 33 +++++++++++++++++++++++++++++++++ drivers/clk/qcom/gdsc.h | 13 +++++++++++++ 2 files changed, 46 insertions(+)
drivers/clk/qcom/gdsc.c +33 -0
@@ -32,6 +32,9 @@#define EN_FEW_WAIT_VAL (0x8 << 16)#define CLK_DIS_WAIT_VAL (0x2 << 12) +#define RETAIN_MEM BIT(14) +#define RETAIN_PERIPH BIT(13) +#define TIMEOUT_US 100#define domain_to_gdsc (domain) container_of(domain, struct gdsc, pd)
@@ -79,6 +82,24 @@ static int gdsc_toggle_logic(struct gdsc *sc, bool en)return -ETIMEDOUT ; } +static inline void gdsc_force_mem_on (struct gdsc *sc) +{ +int i; +u32 mask =RETAIN_MEM |RETAIN_PERIPH ; + +for (i =0 ; i < sc->cxc_count; i++) +regmap_update_bits (sc->regmap, sc->cxcs[i], mask, mask); +} + +static inline void gdsc_clear_mem_on (struct gdsc *sc) +{ +int i; +u32 mask =RETAIN_MEM |RETAIN_PERIPH ; + +for (i =0 ; i < sc->cxc_count; i++) +regmap_update_bits (sc->regmap, sc->cxcs[i], mask,0 ); +} +static int gdsc_enable (struct generic_pm_domain *domain) {struct gdsc *sc =domain_to_gdsc (domain);
@@ -90,6 +111,10 @@ static int gdsc_enable(struct generic_pm_domain *domain) ret =gdsc_toggle_logic (sc, true);if (ret)return ret; + +if (sc->pwrsts &PWRSTS_OFF ) +gdsc_force_mem_on (sc); +/* * If clocks to this power domain were already on, they will take an * additional 4 clock cycles to re-enable after the power domain is
@@ -109,6 +134,9 @@ static int gdsc_disable(struct generic_pm_domain *domain) ret =gdsc_toggle_logic (sc, false); +if (sc->pwrsts &PWRSTS_OFF ) +gdsc_clear_mem_on (sc); +if (sc->root_clk)clk_disable_unprepare (sc->root_clk);
@@ -176,6 +204,11 @@ static int gdsc_init(struct gdsc *sc)if (on <0 )return on; +if (on || (sc->pwrsts &PWRSTS_RET )) +gdsc_force_mem_on (sc); +else +gdsc_clear_mem_on (sc); + sc->pd.power_off = gdsc_disable; sc->pd.power_on = gdsc_enable; sc->pd.attach_dev = gdsc_attach;
drivers/clk/qcom/gdsc.h +13 -0
@@ -18,6 +18,13 @@#include <linux/pm_domain.h> #include <linux/regmap.h> +/* Powerdomain allowable state bitfields */ +#define PWRSTS_OFF BIT(0) +#define PWRSTS_RET BIT(1) +#define PWRSTS_ON BIT(2) +#define PWRSTS_OFF_ON (PWRSTS_OFF | PWRSTS_ON) +#define PWRSTS_RET_ON (PWRSTS_RET | PWRSTS_ON) +/** * struct gdsc - Globally Distributed Switch Controller * @pd: generic power domain
@@ -25,6 +32,9 @@* @gdscr: gsdc control register * @root_con_id: root clock to be enabled * @root_clk: clk handle for the root clk +* @cxcs: offsets of branch registers to toggle mem/periph bits in +* @cxc_count: number of @cxcs +* @pwrsts: Possible powerdomain power states */ struct gdsc {struct generic_pm_domain pd;
@@ -32,6 +42,9 @@ struct gdsc {unsigned int gdscr;char *root_con_id;struct clk *root_clk; +unsigned int *cxcs; +unsigned int cxc_count; +const u8 pwrsts; };#ifdef CONFIG_QCOM_GDSC
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PATCH v6 7/13 clk: qcom: gdsc: Add support for ON only state
In reply to Rajendra NayakCertain devices can have GDSCs' which support ON as the only state. They can't be power collapsed to either hit RET or OFF. The clients drivers for these GDSCs' however would expect the state of the core to be reset following a GDSC disable and re-enable. To do this assert/deassert reset lines every time the client driver would request the GDSC to be powered on/off instead.
--- drivers/clk/qcom/common.c | 3 ++- drivers/clk/qcom/gdsc.c | 33 ++++++++++++++++++++++++++++++++- drivers/clk/qcom/gdsc.h | 11 ++++++++++- 3 files changed, 44 insertions(+), 3 deletions(-)
drivers/clk/qcom/common.c +2 -1
@@ -124,7 +124,8 @@ int qcom_cc_really_probe(struct platform_device *pdev, goto err_reset;if (desc->gdscs && desc->num_gdscs) { - ret =gdsc_register (dev, desc->gdscs, desc->num_gdscs, regmap); + ret =gdsc_register (dev, desc->gdscs, desc->num_gdscs, + &reset->rcdev, regmap);if (ret) goto err_pd; }
drivers/clk/qcom/gdsc.c +32 -1
@@ -82,6 +82,24 @@ static int gdsc_toggle_logic(struct gdsc *sc, bool en)return -ETIMEDOUT ; } +static inline int gdsc_deassert_reset (struct gdsc *sc) +{ +int i; + +for (i =0 ; i < sc->reset_count; i++) + sc->rcdev->ops->deassert (sc->rcdev, sc->resets[i]); +return 0 ; +} + +static inline int gdsc_assert_reset (struct gdsc *sc) +{ +int i; + +for (i =0 ; i < sc->reset_count; i++) + sc->rcdev->ops->assert (sc->rcdev, sc->resets[i]); +return 0 ; +} +static inline void gdsc_force_mem_on (struct gdsc *sc) {int i;
@@ -105,6 +123,9 @@ static int gdsc_enable(struct generic_pm_domain *domain)struct gdsc *sc =domain_to_gdsc (domain);int ret; +if (sc->pwrsts ==PWRSTS_ON ) +return gdsc_deassert_reset (sc); +if (sc->root_clk)clk_prepare_enable (sc->root_clk);
@@ -132,6 +153,9 @@ static int gdsc_disable(struct generic_pm_domain *domain)int ret;struct gdsc *sc =domain_to_gdsc (domain); +if (sc->pwrsts ==PWRSTS_ON ) +return gdsc_assert_reset (sc); + ret =gdsc_toggle_logic (sc, false);if (sc->pwrsts &PWRSTS_OFF )
@@ -200,6 +224,12 @@ static int gdsc_init(struct gdsc *sc)if (ret)return ret; +/* Force gdsc ON if only ON state is supported */ +if (sc->pwrsts ==PWRSTS_ON ) + ret =gdsc_toggle_logic (sc, true); +if (ret) +return ret; + on =gdsc_is_enabled (sc);if (on <0 )return on;
@@ -220,7 +250,7 @@ static int gdsc_init(struct gdsc *sc) }int gdsc_register (struct device *dev,struct gdsc **scs,size_t num, -struct regmap *regmap) +struct reset_controller_dev *rcdev,struct regmap *regmap) {int i, ret;struct genpd_onecell_data *data;
@@ -239,6 +269,7 @@ int gdsc_register(struct device *dev, struct gdsc **scs, size_t num,if (!scs[i])continue ; scs[i]->regmap = regmap; + scs[i]->rcdev = rcdev; ret =gdsc_init (scs[i]);if (ret)return ret;
drivers/clk/qcom/gdsc.h +10 -1
@@ -17,6 +17,7 @@#include <linux/clk.h> #include <linux/pm_domain.h> #include <linux/regmap.h> +#include <linux/reset-controller.h> /* Powerdomain allowable state bitfields */ #define PWRSTS_OFF BIT(0)
@@ -34,6 +35,9 @@* @root_clk: clk handle for the root clk * @cxcs: offsets of branch registers to toggle mem/periph bits in * @cxc_count: number of @cxcs +* @resets: ids of resets associated with this gdsc +* @reset_count: number of @resets +* @rcdev: reset controller * @pwrsts: Possible powerdomain power states */ struct gdsc {
@@ -44,14 +48,19 @@ struct gdsc {struct clk *root_clk;unsigned int *cxcs;unsigned int cxc_count; +struct reset_controller_dev *rcdev; +unsigned int *resets; +unsigned int reset_count;const u8 pwrsts; };#ifdef CONFIG_QCOM_GDSC -int gdsc_register (struct device *,struct gdsc **,size_t n,struct regmap *); +int gdsc_register (struct device *,struct gdsc **,size_t n, +struct reset_controller_dev *,struct regmap *);void gdsc_unregister (struct device *);#else static inline int gdsc_register (struct device *d,struct gdsc **g,size_t n, +struct reset_controller_dev *rcdev,struct regmap *r) {return -ENOSYS ;
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PATCH v6 7/13 clk: qcom: gdsc: Add support for ON only state
drivers/clk/qcom/gdsc.c static int gdsc_init(struct gdsc *sc) · line 231
Quoted 9 lines · Rajendra Nayak
drivers/clk/qcom/gdsc.c +5
-0@@ -200,6 +224,12 @@ static int gdsc_init(struct gdsc *sc)if (ret)return ret; +/* Force gdsc ON if only ON state is supported */ +if (sc->pwrsts ==PWRSTS_ON ) + ret =gdsc_toggle_logic (sc, true); +if (ret) +return ret;
This is missing braces. Please test :)
Quoted 10 lines
drivers/clk/qcom/gdsc.c +1
-0+ on =gdsc_is_enabled (sc);if (on <0 )return on;drivers/clk/qcom/gdsc.h +0
-0
drivers/clk/qcom/gdsc.h line 20
Quoted 4 lines
drivers/clk/qcom/gdsc.h +1
-0@@ -17,6 +17,7 @@#include <linux/clk.h> #include <linux/pm_domain.h> #include <linux/regmap.h> +#include <linux/reset-controller.h>
Do we need this include either? Just forward declare stuff. Same comment goes for the clk include.
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PATCH v6 8/13 clk: qcom: gdsc: Add GDSCs in msm8916 GCC
In reply to Rajendra NayakAdd all data for the GDSCs which are part of msm8916 GCC block.
--- drivers/clk/qcom/Kconfig | 1 + drivers/clk/qcom/gcc-msm8916.c | 52 ++++++++++++++++++++++++++++ include/dt-bindings/clock/qcom,gcc-msm8916.h | 8 +++++ 3 files changed, 61 insertions(+)
drivers/clk/qcom/Kconfig +1 -0
@@ -54,6 +54,7 @@ config MSM_GCC_8660 config MSM_GCC_8916 tristate "MSM8916 Global Clock Controller" + select QCOM_GDSC depends on COMMON_CLK_QCOM help Support for the global clock controller on msm8916 devices.
drivers/clk/qcom/gcc-msm8916.c +52 -0
76 lines not on this page · raw message
include/dt-bindings/clock/qcom,gcc-msm8916.h +8 -0
@@ -153,4 +153,12 @@#define GCC_VENUS0_AXI_CLK 136#define GCC_VENUS0_VCODEC0_CLK 137 +/* Indexes for GDSCs */ +#define BIMC_GDSC 0 +#define VENUS_GDSC 1 +#define MDSS_GDSC 2 +#define JPEG_GDSC 3 +#define VFE_GDSC 4 +#define OXILI_GDSC 5 +#endif
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QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
PATCH v6 8/13 clk: qcom: gdsc: Add GDSCs in msm8916 GCC
Quoted 24 lines · Rajendra Nayak
drivers/clk/qcom/gcc-msm8916.c +20
-0@@ -2562,6 +2563,47 @@ static struct clk_branch gcc_venus0_vcodec0_clk = { }, }; +static struct gdsc venus_gdsc = { + .gdscr =0x4c018 , + .pd = { + .name ="venus" , + }, + .pwrsts =PWRDM_OFF_ON , +}; + +static struct gdsc mdss_gdsc = { + .gdscr =0x4d078 , + .pd = { + .name ="mdss" , + }, + .pwrsts =PWRDM_OFF_ON , +}; + +static struct gdsc jpeg_gdsc = { + .gdscr =0x5701c , + .pd = { + .name ="jpeg" ,
drivers/clk/qcom/gcc-msm8916.c static struct clk_branch gcc_venus0_vcodec0_clk = { · line 2595
Quoted 10 lines
drivers/clk/qcom/gcc-msm8916.c +10
-0+ }, + .pwrsts = PWRDM_OFF_ON, +}; + +static struct gdsc vfe_gdsc = { + .gdscr =0x58034 , + .pd = { + .name ="vfe" , + }, + .pwrsts =PWRDM_OFF_ON ,
Is this supposed to tbe PWRSTS_OFF_ON?
Quoted 11 lines
drivers/clk/qcom/gcc-msm8916.c +11
-0+}; + +static struct gdsc oxili_gdsc = { + .gdscr =0x5901c , + .pd = { + .name ="oxili" , + }, + .root_con_id ="gfx3d_clk_src" , + .pwrsts =PWRDM_OFF_ON , +}; +
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PATCH v6 8/13 clk: qcom: gdsc: Add GDSCs in msm8916 GCC
Quoted 29 lines · Stephen Boyd
Quoted 28 lines · Rajendra Nayak
drivers/clk/qcom/gcc-msm8916.c +24
-0@@ -2562,6 +2563,47 @@ static struct clk_branch gcc_venus0_vcodec0_clk = { }, }; +static struct gdsc venus_gdsc = { + .gdscr =0x4c018 , + .pd = { + .name ="venus" , + }, + .pwrsts =PWRDM_OFF_ON , +}; + +static struct gdsc mdss_gdsc = { + .gdscr =0x4d078 , + .pd = { + .name ="mdss" , + }, + .pwrsts =PWRDM_OFF_ON , +}; + +static struct gdsc jpeg_gdsc = { + .gdscr =0x5701c , + .pd = { + .name ="jpeg" , + }, + .pwrsts =PWRDM_OFF_ON , +}; +
Quoted 8 lines
drivers/clk/qcom/gcc-msm8916.c static struct clk_branch gcc_venus0_vcodec0_clk = { · line 2595
Quoted 6 lines
drivers/clk/qcom/gcc-msm8916.c +6
-0+static struct gdsc vfe_gdsc = { + .gdscr =0x58034 , + .pd = { + .name ="vfe" , + }, + .pwrsts =PWRDM_OFF_ON ,Is this supposed to tbe
PWRSTS_OFF_ON?
indeed, will fix.
PATCH v6 9/13 clk: qcom: gdsc: Add GDSCs in msm8974 GCC
In reply to Rajendra NayakFrom: Stephen Boyd <[email protected]>
Theres just one GDSC as part of the msm8974 GCC block.
--- drivers/clk/qcom/Kconfig | 1 + drivers/clk/qcom/gcc-msm8974.c | 15 +++++++++++++++ include/dt-bindings/clock/qcom,gcc-msm8974.h | 3 +++ 3 files changed, 19 insertions(+)
drivers/clk/qcom/Kconfig +1 -0
@@ -89,6 +89,7 @@ config MSM_MMCC_8960 config MSM_GCC_8974 tristate "MSM8974 Global Clock Controller" + select QCOM_GDSC depends on COMMON_CLK_QCOM help Support for the global clock controller on msm8974 devices.
drivers/clk/qcom/gcc-msm8974.c +15 -0
@@ -31,6 +31,7 @@#include "clk-rcg.h" #include "clk-branch.h" #include "reset.h" +#include "gdsc.h" enum {P_XO ,
@@ -2431,6 +2432,14 @@ static struct clk_branch gcc_usb_hsic_system_clk = { }, }; +static struct gdsc usb_hs_hsic_gdsc = { + .gdscr =0x404 , + .pd = { + .name ="usb_hs_hsic" , + }, + .pwrsts =PWRSTS_OFF_ON , +}; +static struct clk_regmap *gcc_msm8974_clocks[] = { [GPLL0 ] = &gpll0.clkr, [GPLL0_VOTE ] = &gpll0_vote,
@@ -2660,6 +2669,10 @@ static const struct qcom_reset_map gcc_msm8974_resets[] = { [GCC_VENUS_RESTART] = { 0x1740 }, }; +static struct gdsc *gcc_msm8974_gdscs[] = { + [USB_HS_HSIC_GDSC ] = &usb_hs_hsic_gdsc, +}; +static const struct regmap_config gcc_msm8974_regmap_config = { .reg_bits =32 , .reg_stride =4 ,
@@ -2674,6 +2687,8 @@ static const struct qcom_cc_desc gcc_msm8974_desc = { .num_clks = ARRAY_SIZE(gcc_msm8974_clocks), .resets = gcc_msm8974_resets, .num_resets = ARRAY_SIZE(gcc_msm8974_resets), + .gdscs = gcc_msm8974_gdscs, + .num_gdscs = ARRAY_SIZE(gcc_msm8974_gdscs), };static const struct of_device_id gcc_msm8974_match_table[] = {
include/dt-bindings/clock/qcom,gcc-msm8974.h +3 -0
@@ -321,4 +321,7 @@#define GCC_SDCC1_CDCCAL_SLEEP_CLK 304#define GCC_SDCC1_CDCCAL_FF_CLK 305 +/* gdscs */ +#define USB_HS_HSIC_GDSC 0 +#endif
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
PATCH v6 9/13 clk: qcom: gdsc: Add GDSCs in msm8974 GCC
Quoted 3 lines · Rajendra Nayak
From: Stephen Boyd <[email protected]>
Theres just one GDSC as part of the msm8974 GCC block.
s/Theres/There's/
Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH v6 10/13 clk: qcom: gdsc: Add GDSCs in msm8974 MMCC
In reply to Rajendra NayakFrom: Stephen Boyd <[email protected]>
Add the GDSC instances that exist as part of msm8974 MMCC block
--- drivers/clk/qcom/Kconfig | 1 + drivers/clk/qcom/mmcc-msm8974.c | 72 +++++++++++++++++++++++++++ include/dt-bindings/clock/qcom,mmcc-msm8974.h | 8 +++ 3 files changed, 81 insertions(+)
drivers/clk/qcom/Kconfig +1 -0
@@ -99,6 +99,7 @@ config MSM_GCC_8974 config MSM_MMCC_8974 tristate "MSM8974 Multimedia Clock Controller" select MSM_GCC_8974 + select QCOM_GDSC depends on COMMON_CLK_QCOM help Support for the multimedia clock controller on msm8974 devices.
drivers/clk/qcom/mmcc-msm8974.c +72 -0
96 lines not on this page · raw message
include/dt-bindings/clock/qcom,mmcc-msm8974.h +8 -0
@@ -158,4 +158,12 @@#define SPDM_RM_AXI 141#define SPDM_RM_OCMEMNOC 142 +/* gdscs */ +#define VENUS0_GDSC 0 +#define MDSS_GDSC 1 +#define CAMSS_JPEG_GDSC 2 +#define CAMSS_VFE_GDSC 3 +#define OXILI_GDSC 4 +#define OXILICX_GDSC 5 +#endif
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
PATCH v6 10/13 clk: qcom: gdsc: Add GDSCs in msm8974 MMCC
Quoted 7 lines · Rajendra Nayak
From: Stephen Boyd <[email protected]>
Add the GDSC instances that exist as part of msm8974 MMCC block
Signed-off-by Stephen Boyd <[email protected]>Signed-off-by Rajendra Nayak <[email protected]>
From here on it looks fine, just routine data additions.
Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH v6 11/13 clk: qcom: gdsc: Add GDSCs in apq8084 GCC
In reply to Rajendra NayakAdd the GDSC instances that exist as part of apq8084 GCC block
--- drivers/clk/qcom/Kconfig | 1 + drivers/clk/qcom/gcc-apq8084.c | 42 ++++++++++++++++++++++++++++ include/dt-bindings/clock/qcom,gcc-apq8084.h | 6 ++++ 3 files changed, 49 insertions(+)
drivers/clk/qcom/Kconfig +1 -0
@@ -7,6 +7,7 @@ config COMMON_CLK_QCOM config APQ_GCC_8084 tristate "APQ8084 Global Clock Controller" + select QCOM_GDSC depends on COMMON_CLK_QCOM help Support for the global clock controller on apq8084 devices.
drivers/clk/qcom/gcc-apq8084.c +42 -0
66 lines not on this page · raw message
include/dt-bindings/clock/qcom,gcc-apq8084.h +6 -0
@@ -348,4 +348,10 @@#define GCC_PCIE_1_PIPE_CLK 331#define GCC_PCIE_1_SLV_AXI_CLK 332 +/* gdscs */ +#define USB_HS_HSIC_GDSC 0 +#define PCIE0_GDSC 1 +#define PCIE1_GDSC 2 +#define USB30_GDSC 3 +#endif
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
PATCH v6 12/13 clk: qcom: gdsc: Add GDSCs in apq8084 MMCC
In reply to Rajendra NayakFrom: Stephane Viau <[email protected]>
Add the GDSC instances that exist as part of apq8084 MMCC block.
--- drivers/clk/qcom/Kconfig | 1 + drivers/clk/qcom/mmcc-apq8084.c | 68 ++++++++++++++++++++++++++- include/dt-bindings/clock/qcom,mmcc-apq8084.h | 8 ++++ 3 files changed, 76 insertions(+), 1 deletion(-)
drivers/clk/qcom/Kconfig +1 -0
@@ -17,6 +17,7 @@ config APQ_GCC_8084 config APQ_MMCC_8084 tristate "APQ8084 Multimedia Clock Controller" select APQ_GCC_8084 + select QCOM_GDSC depends on COMMON_CLK_QCOM help Support for the multimedia clock controller on apq8084 devices.
drivers/clk/qcom/mmcc-apq8084.c +67 -1
96 lines not on this page · raw message
include/dt-bindings/clock/qcom,mmcc-apq8084.h +8 -0
@@ -180,4 +180,12 @@#define VPU_SLEEP_CLK 163#define VPU_VDP_CLK 164 +/* GDSCs */ +#define VENUS0_GDSC 0 +#define MDSS_GDSC 1 +#define CAMSS_JPEG_GDSC 2 +#define CAMSS_VFE_GDSC 3 +#define OXILI_GDSC 4 +#define OXILICX_GDSC 5 +#endif
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
PATCH v6 13/13 arm: dts: qcom: Add #power-domain-cells property
In reply to Rajendra Nayakmsm8974 has gcc and mmcc nodes, and apq8084 has a gcc node which implement gdsc powerdomains. Add the #power-domain-cells property to them.
--- arch/arm/boot/dts/qcom-apq8084.dtsi | 1 + arch/arm/boot/dts/qcom-msm8974.dtsi | 2 ++ arch/arm64/boot/dts/qcom/msm8916.dtsi | 1 + 3 files changed, 4 insertions(+)
arch/arm/boot/dts/qcom-apq8084.dtsi +1 -0
@@ -221,6 +221,7 @@ compatible = "qcom,gcc-apq8084"; #clock-cells = <1>; #reset-cells = <1>; + #power-domain-cells = <1>; reg = <0xfc400000 0x4000>; };
arch/arm/boot/dts/qcom-msm8974.dtsi +2 -0
@@ -217,6 +217,7 @@ compatible = "qcom,gcc-msm8974"; #clock-cells = <1>; #reset-cells = <1>; + #power-domain-cells = <1>; reg = <0xfc400000 0x4000>; };
@@ -224,6 +225,7 @@ compatible = "qcom,mmcc-msm8974"; #clock-cells = <1>; #reset-cells = <1>; + #power-domain-cells = <1>; reg = <0xfd8c0000 0x6000>; };
arch/arm64/boot/dts/qcom/msm8916.dtsi +1 -0
@@ -120,6 +120,7 @@ compatible = "qcom,gcc-msm8916"; #clock-cells = <1>; #reset-cells = <1>; + #power-domain-cells = <1>; reg = <0x1800000 0x80000>; };
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