media: platform: add NVIDIA Tegra VI driver

index f6bed19..553867f 100644
@@ -119,6 +119,7 @@ source "drivers/media/platform/exynos4-is/Kconfig"
 source "drivers/media/platform/s5p-tv/Kconfig"
 source "drivers/media/platform/am437x/Kconfig"
 source "drivers/media/platform/xilinx/Kconfig"
+source "drivers/media/platform/tegra/Kconfig"
 
 endif # V4L_PLATFORM_DRIVERS
 

index 114f9ab..426e0e4 100644
@@ -52,4 +52,6 @@ obj-$(CONFIG_VIDEO_AM437X_VPFE)		+= am437x/
 
 obj-$(CONFIG_VIDEO_XILINX)		+= xilinx/
 
+obj-$(CONFIG_VIDEO_TEGRA)		+= tegra/
+
 ccflags-y += -I$(srctree)/drivers/media/i2c

new file mode 100644
index 0000000..54c0e7a
@@ -0,0 +1,10 @@
+config VIDEO_TEGRA
+	tristate "NVIDIA Tegra Video Input Driver"
+	depends on VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API && OF
+	depends on TEGRA_HOST1X
+	select VIDEOBUF2_DMA_CONTIG
+	---help---
+	  Driver for Video Input (VI) controller found on NVIDIA Tegra SoC.
+
+	  To compile this driver as a module, choose M here: the module will be
+	  called tegra-video.

new file mode 100644
index 0000000..18a1c16
@@ -0,0 +1,3 @@
+tegra-video-objs += tegra-core.o tegra-csi.o tegra-vi.o tegra-channel.o
+
+obj-$(CONFIG_VIDEO_TEGRA) += tegra-video.o

index d4ee460..534ada52 100644
@@ -7,6 +7,14 @@
 	model = "NVIDIA Tegra210 P2571 reference board (E.1)";
 	compatible = "nvidia,p2571-e01", "nvidia,tegra210";
 
+	host1x@0,50000000 {
+		vi@0,54080000 {
+			status = "okay";
+
+			avdd-dsi-csi-supply = <&vdd_dsi_csi>;
+		};
+	};
+
 	pinmux: pinmux@0,700008d4 {
 		pinctrl-names = "boot";
 		pinctrl-0 = <&state_boot>;

182 lines not on this page · raw message

index 46d6ead..433cb52 100644
@@ -40,10 +40,39 @@ of the following host1x client modules:
   - interrupts: The interrupt outputs from the controller.
   - clocks: Must contain one entry, for the module clock.
     See ../clocks/clock-bindings.txt for details.
+  - clock-names: Must include the following entries:
+    - vi
+      This MUST be the first entry.
+    - csi
+    - parent
   - resets: Must contain an entry for each entry in reset-names.
     See ../reset/reset.txt for details.
   - reset-names: Must include the following entries:
     - vi
+  - power-domains: The power domains settings.
+    See ../power/power_domain.txt
+  - iommus: The IOMMU settings.
+    See ../iommu/iommu.txt
+  - ports: several VI input ports which connecting CSI ports. Ports contain
+    several port and each port has one endpoint.
+    See ../graph.txt and ../media/video-interfaces.txt
+  - avdd-dsi-csi-supply: a regulator required by VI.
+
+- csi: camera serial interface
+
+  Required properties:
+  - compatible: "nvidia,tegra<chip>-csi"
+  - reg: Physical base address and length of the controller's registers.
+  - interrupts: The interrupt outputs from the controller.
+  - clocks: Must contain one entry, for the module clock.
+    See ../clocks/clock-bindings.txt for details.
+  - clock-names: Must include the following entries:
+    - cil
+      This MUST be the first entry.
+  - ports: 2 ports presenting 2 channels of CSI. Each port has 2 endpoints:
+    one connects to sensor device tree node as input and the other one connects
+    to VI endpoint.
+    See ../graph.txt and ../media/video-interfaces.txt
 
 - epp: encoder pre-processor
 

@@ -274,13 +303,183 @@ Example:
 			reset-names = "mpe";
 		};
 
-		vi {
-			compatible = "nvidia,tegra20-vi";
-			reg = <0x54080000 0x00040000>;
-			interrupts = <0 69 0x04>;
-			clocks = <&tegra_car TEGRA20_CLK_VI>;
-			resets = <&tegra_car 100>;
+		vi@0,54080000 {
+			compatible = "nvidia,tegra210-vi";
+			reg = <0x0 0x54080000 0x0 0x800>;
+			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+			clocks = <&tegra_car TEGRA210_CLK_VI>,
+				 <&tegra_car TEGRA210_CLK_CSI>,
+				 <&tegra_car TEGRA210_CLK_PLL_C>;
+			clock-names = "vi", "csi", "parent";
+			resets = <&tegra_car 20>;
 			reset-names = "vi";
+
+			power-domains = <&pmc TEGRA_POWERGATE_VENC>;
+
+			iommus = <&mc TEGRA_SWGROUP_VI>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					vi_in0: endpoint {
+						remote-endpoint = <&csi_out0>;
+					};
+				};
+				port@1 {
+					reg = <1>;
+
+					vi_in1: endpoint {
+						remote-endpoint = <&csi_out1>;
+					};
+				};
+				port@2 {
+					reg = <2>;
+
+					vi_in2: endpoint {
+						remote-endpoint = <&csi_out2>;
+					};
+				};
+				port@3 {
+					reg = <3>;
+
+					vi_in3: endpoint {
+						remote-endpoint = <&csi_out3>;
+					};
+				};
+				port@4 {
+					reg = <4>;
+
+					vi_in4: endpoint {
+						remote-endpoint = <&csi_out4>;
+					};
+				};
+				port@5 {
+					reg = <5>;
+
+					vi_in5: endpoint {
+						remote-endpoint = <&csi_out5>;
+					};
+				};
+
+			};
+		};
+
+		csi@0,54080838 {
+			compatible = "nvidia,tegra210-csi";
+			reg = <0x0 0x54080838 0x0 0x700>;
+			clocks = <&tegra_car TEGRA210_CLK_CILAB>;
+			clock-names = "cil";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+					csi_in0: endpoint@0 {
+						reg = <0x0>;
+					};
+					csi_out0: endpoint@1 {
+						reg = <0x1>;
+						remote-endpoint = <&vi_in0>;
+					};
+				};
+				port@1 {
+					reg = <1>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+					csi_in1: endpoint@0 {
+						reg = <0>;
+					};
+					csi_out1: endpoint@1 {
+						reg = <1>;
+						remote-endpoint = <&vi_in1>;
+					};
+				};
+			};
+		};
+
+		csi@1,54081038 {
+			compatible = "nvidia,tegra210-csi";
+			reg = <0x0 0x54081038 0x0 0x700>;
+			clocks = <&tegra_car TEGRA210_CLK_CILCD>;
+			clock-names = "cil";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@2 {
+					reg = <2>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+					csi_in2: endpoint@0 {
+						reg = <0>;
+					};
+
+					csi_out2: endpoint@1 {
+						reg = <1>;
+						remote-endpoint = <&vi_in2>;
+					};
+				};
+				port@3 {
+					reg = <3>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+					csi_in3: endpoint@0 {
+						reg = <0>;
+					};
+
+					csi_out3: endpoint@1 {
+						reg = <1>;
+						remote-endpoint = <&vi_in3>;
+					};
+				};
+			};
+		};
+
+		csi@2,54081838 {
+			compatible = "nvidia,tegra210-csi";
+			reg = <0x0 0x54081838 0x0 0x700>;
+			clocks = <&tegra_car TEGRA210_CLK_CILE>;
+			clock-names = "cil";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@4 {
+					reg = <4>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+					csi_in4: endpoint@0 {
+						reg = <0>;
+					};
+					csi_out4: endpoint@1 {
+						reg = <1>;
+						remote-endpoint = <&vi_in4>;
+					};
+				};
+				port@5 {
+					reg = <5>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+					csi_in5: endpoint@0 {
+						reg = <0>;
+					};
+					csi_out5: endpoint@1 {
+						reg = <1>;
+						remote-endpoint = <&vi_in5>;
+					};
+				};
+			};
 		};
 
 		epp {