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PCI: spear: Fix definition of LTSSM_STATE_MASK

RFC Superseded Fabio Estevam 1 participant 2 messages Oct 5, 2015 – Oct 9, 2015 PCI

v1 of 2 Superseded Latest is v2 →

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RFC 1/1 PCI: spear: Fix definition of LTSSM_STATE_MASK

From: Fabio Estevam <[email protected]>

Designware PCI block uses 0x3f for the LTSSM_STATE_MASK.

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Murali,

I am doing some consolidation on the PCI DW drivers and I noticed that keystone uses a different LTSSM_STATE_MASK definition.

Could you please double check it?

 drivers/pci/host/pci-keystone-dw.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/pci/host/pci-keystone-dw.c +1 -1
index 3cf55cd..78320e4 100644
@@ -25,7 +25,7 @@
 
 /* Application register defines */
 #define LTSSM_EN_VAL		        1
-#define LTSSM_STATE_MASK		0x1f
+#define LTSSM_STATE_MASK		0x3f
 #define LTSSM_STATE_L0			0x11
 #define DBI_CS2_EN_VAL			0x20
 #define OB_XLAT_EN_VAL		        2
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Quoted 4 lines · Fabio Estevam

From: Fabio Estevam <[email protected]>

Designware PCI block uses 0x3f for the LTSSM_STATE_MASK.

Quoted 8 lines

---
Murali,

I am doing some consolidation on the PCI DW drivers and I noticed that keystone uses a different LTSSM_STATE_MASK definition.

Could you please double check it?

Ok, checked in http://www.ti.com/lit/ug/sprugs6d/sprugs6d.pdf and LTSSM_STATE_MASK is only 5 bits, so the current code is correct.