PCI: hv: New paravirtual PCI front-end for Hyper-V VMs

From: Jake Oshins <[email protected]>

This patch adds an fwnode_handle to struct pci_sysdata, which is used by the next patch in the series when trying to locate an IRQ domain associated with a root PCI bus.

Signed-off-by Jake Oshins <[email protected]>

---
 arch/x86/include/asm/pci.h | 13 +++++++++++++
 include/asm-generic/pci.h  |  4 ++++
 2 files changed, 17 insertions(+)

arch/x86/include/asm/pci.h +13 -0

index 4625943..fb74453 100644
@@ -20,6 +20,9 @@ struct pci_sysdata {
 #ifdef CONFIG_X86_64
 	void		*iommu;		/* IOMMU private data */
 #endif
+#ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
+	void		*fwnode;	/* IRQ domain for MSI assignment */
+#endif
 };
 
 extern int pci_routeirq;

@@ -41,6 +44,16 @@ static inline int pci_proc_domain(struct pci_bus *bus)
 }
 #endif
 
+#ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
+static inline void *_pci_root_bus_fwnode(struct pci_bus *bus)
+{
+	struct pci_sysdata *sd = bus->sysdata;
+	return sd->fwnode;
+}
+
+#define pci_root_bus_fwnode	_pci_root_bus_fwnode
+#endif
+
 /* Can be used to override the logic in pci_scan_bus for skipping
    already-configured bus numbers - to be used for buggy BIOSes
    or architectures with incomplete PCI setup by the loader */

include/asm-generic/pci.h +0 -0

index f24bc51..3fde985 100644

include/asm-generic/pci.h +1 -0

+
 #endif /* _ASM_GENERIC_PCI_H */

-----Original Message-----
From: Jiang Liu [mailto:[email protected]]
Sent: Wednesday, December 2, 2015 10:53 PM
To: Jake Oshins <[email protected]>; [email protected]; KY Srinivasan <[email protected]>; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; Haiyang Zhang <[email protected]>; [email protected]; [email protected]; [email protected]
Subject: Re: [PATCH v6 4/7] PCI: Add fwnode_handle to pci_sysdata

include/asm-generic/pci.h static inline int pci_get_legacy_ide_irq(struct pci_dev

Quoted 21 lines · On 2015/11/3 5:33, [email protected] wrote:

From: Jake Oshins <[email protected]>

arch/x86/include/asm/pci.h +10 -0

+#ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
+static inline void *_pci_root_bus_fwnode(struct pci_bus *bus)
+{
+	struct pci_sysdata *sd = bus->sysdata;
+	return sd->fwnode;
+}
+
+#define pci_root_bus_fwnode	_pci_root_bus_fwnode
+#endif
+
 /* Can be used to override the logic in pci_scan_bus for skipping
    already-configured bus numbers - to be used for buggy BIOSes
    or architectures with incomplete PCI setup by the loader */

include/asm-generic/pci.h +0 -0

index f24bc51..3fde985 100644
@@ -21,4 +21,8 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev

*dev, int channel)

Quoted 3 lines

include/asm-generic/pci.h +0 -0

 #define PCI_DMA_BUS_IS_PHYS	(1)
 #endif
 

include/asm-generic/pci.h static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) · line 26

Quoted 3 lines

include/asm-generic/pci.h +3 -0

+#ifndef pci_root_bus_fwnode
+#define pci_root_bus_fwnode(bus)	((void)(bus),NULL)
+#endif

Hi Jakeo,
For x86, all PCI devices share the same MSI controller. But I'm
not sure whether it may have per-bus/per-device MSI controllers on other archs. If there may be multiple MSI controllers serving PCI devices under the same PCI root, it would be better to use some thing like pci_get_msi_fwnode(bus) or similar.
Thanks,
Gerry

From: Jake Oshins <[email protected]>

This patch introduces a new driver which exposes a root PCI bus whenever a PCI Express device is passed through to a guest VM under Hyper-V. The device can be single- or multi-function. The interrupts for the devices are managed by an IRQ domain, implemented within the driver.

Signed-off-by Jake Oshins <[email protected]>

---
 MAINTAINERS                    |    1 +
 drivers/pci/Kconfig            |    7 +
 drivers/pci/host/Makefile      |    1 +
 drivers/pci/host/hv_pcifront.c | 2267 ++++++++++++++++++++++++++++++++++++++++
 4 files changed, 2276 insertions(+)
 create mode 100644 drivers/pci/host/hv_pcifront.c

MAINTAINERS +0 -0

index a2d50fe..a1205b4 100644

MAINTAINERS +22 -0

+/* Interrupt management hooks */
+
+/**
+ * hv_msi_free() - Free the MSI.
+ * @domain:	The interrupt domain pointer
+ * @info:	Extra MSI-related context
+ * @irq:	Identifies the IRQ.
+ *
+ * The Hyper-V parent partition and hypervisor are tracking the
+ * messages that are in use, keeping the interrupt redirection
+ * table up to date.  This callback sends a message that frees
+ * the the IRT entry and related tracking nonsense.
+ */
+static void hv_msi_free(struct irq_domain *domain, struct msi_domain_info *info,
+			unsigned int irq)
+{
+	struct pci_delete_interrupt *int_pkt;
+	struct {
+		struct pci_packet pkt;
+		u8 buffer[sizeof(struct pci_delete_interrupt) -
+			  sizeof(struct pci_message)];
+	} ctxt;

MAINTAINERS +66 -0

+	hbus = info->data;
+	hpdev = lookup_hv_dev(hbus, devfn_to_wslot(pdev->devfn));
+	if (!hpdev)
+		return;
+
+	int_desc = irq_get_chip_data(irq);
+	if (int_desc) {
+		memset(&ctxt, 0, sizeof(ctxt));
+		int_pkt = (struct pci_delete_interrupt *)&ctxt.pkt.message;
+		int_pkt->message_type.message_type =
+			PCI_DELETE_INTERRUPT_MESSAGE;
+		int_pkt->wslot.slot = hpdev->desc.win_slot.slot;
+		int_pkt->int_desc = *int_desc;
+		vmbus_sendpacket(hbus->hdev->channel, int_pkt, sizeof(*int_pkt),
+				 (unsigned long)&ctxt.pkt, VM_PKT_DATA_INBAND,
+				 0);
+		desc->irq_data.chip_data = NULL;
+		kfree(int_desc);
+	}
+
+	hv_pcichild_dec(hpdev, hv_pcidev_ref_by_slot);
+}
+
+static int hv_set_affinity(struct irq_data *data, const struct cpumask *dest,
+			   bool force)
+{
+	struct irq_data *parent = data->parent_data;
+
+	return parent->chip->irq_set_affinity(parent, dest, force);
+}
+
+void hv_irq_mask(struct irq_data *data)
+{
+	pci_msi_mask_irq(data);
+}
+
+/**
+ * hv_irq_unmask() - "Unmask" the IRQ by setting its current
+ * affinity.
+ * @data:	Describes the IRQ
+ *
+ * Build new a destination for the MSI and make a hypercall to
+ * update the Interrupt Redirection Table. "Device Logical ID"
+ * is built out of this PCI bus's instance GUID and the function
+ * number of the device.
+ */
+void hv_irq_unmask(struct irq_data *data)
+{
+	struct msi_desc *msi_desc = irq_data_get_msi_desc(data);
+	struct irq_cfg *cfg = irqd_cfg(data);
+	struct retarget_msi_interrupt params;
+	struct hv_pcibus_device *hbus;
+	struct cpumask *dest;
+	struct pci_bus *pbus;
+	struct pci_dev *pdev;
+	int cpu;
+
+	dest = irq_data_get_affinity_mask(data);
+	pdev = msi_desc_to_pci_dev(msi_desc);
+	pbus = pdev->bus;
+	hbus = container_of(pbus->sysdata, struct hv_pcibus_device, sysdata);
+
+	memset(&params, 0, sizeof(params));
+	params.partition_id = HV_PARTITION_ID_SELF;
+	params.source = 1; /* MSI(-X) */
+	params.address = msi_desc->msg.address_lo;

MAINTAINERS +99 -0

+
+	hv_do_hypercall(HVCALL_RETARGET_INTERRUPT, &params, NULL);
+
+	pci_msi_unmask_irq(data);
+}
+
+struct compose_comp_ctxt {
+	struct hv_pci_compl comp_pkt;
+	struct tran_int_desc int_desc;
+};
+
+static void hv_pci_compose_compl(void *context, struct pci_response *resp,
+				 int resp_packet_size)
+{
+	struct compose_comp_ctxt *comp_pkt = context;
+	struct pci_create_int_response *int_resp =
+		(struct pci_create_int_response *)resp;
+
+	comp_pkt->comp_pkt.completion_status = resp->status;
+	comp_pkt->int_desc = int_resp->int_desc;
+	complete(&comp_pkt->comp_pkt.host_event);
+}
+
+/**
+ * hv_compose_msi_msg() - Supplies a valid MSI address/data
+ * @data:	Everything about this MSI
+ * @msg:	Buffer that is filled in by this function
+ *
+ * This function unpacks the IRQ looking for target CPU set, IDT
+ * vector and mode and sends a message to the parent partition
+ * asking for a mapping for that tuple in this partition.  The
+ * response supplies a data value and address to which that data
+ * should be written to trigger that interrupt.
+ */
+static void hv_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
+{
+	struct irq_cfg *cfg = irqd_cfg(data);
+	struct hv_pcibus_device *hbus;
+	struct hv_pci_dev *hpdev;
+	struct pci_bus *pbus;
+	struct pci_dev *pdev;
+	struct pci_create_interrupt *int_pkt;
+	struct compose_comp_ctxt comp;
+	struct tran_int_desc *int_desc;
+	struct cpumask *affinity;
+	struct {
+		struct pci_packet pkt;
+		u8 buffer[sizeof(struct pci_create_interrupt) -
+			  sizeof(struct pci_message)];
+	} ctxt;
+	int cpu;
+	int ret;
+
+	pdev = msi_desc_to_pci_dev(irq_data_get_msi_desc(data));
+	pbus = pdev->bus;
+	hbus = container_of(pbus->sysdata, struct hv_pcibus_device, sysdata);
+	hpdev = lookup_hv_dev(hbus, devfn_to_wslot(pdev->devfn));
+
+	if (!hpdev)
+		goto return_null_message;
+
+	int_desc = kzalloc(sizeof(*int_desc), GFP_KERNEL);
+	if (!int_desc)
+		goto drop_reference;
+
+	memset(&ctxt, 0, sizeof(ctxt));
+	init_completion(&comp.comp_pkt.host_event);
+	ctxt.pkt.completion_func = hv_pci_compose_compl;
+	ctxt.pkt.compl_ctxt = ∁
+	int_pkt = (struct pci_create_interrupt *)&ctxt.pkt.message;
+	int_pkt->message_type.message_type = PCI_CREATE_INTERRUPT_MESSAGE;
+	int_pkt->wslot.slot = hpdev->desc.win_slot.slot;
+	int_pkt->int_desc.vector = cfg->vector;
+	int_pkt->int_desc.vector_count = 1;
+	int_pkt->int_desc.delivery_mode =
+		(apic->irq_delivery_mode == dest_LowestPrio) ? 1 : 0;
+
+	/*
+	 * This bit doesn't have to work on machines with more than 64
+	 * processors because Hyper-V only supports 64 in a guest.
+	 */
+	affinity = irq_data_get_affinity_mask(data);
+	for_each_cpu(cpu, affinity) {
+		if (cpu_is_offline(cpu))
+			continue;
+		int_pkt->int_desc.cpu_mask |=
+			(1 << vmbus_cpu_number_to_vp_number(cpu));
+	}
+
+	ret = vmbus_sendpacket(hpdev->hbus->hdev->channel, int_pkt,
+			       sizeof(*int_pkt), (unsigned long)&ctxt.pkt,
+			       VM_PKT_DATA_INBAND,
+			       VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED);
+	if (!ret)
+		wait_for_completion(&comp.comp_pkt.host_event);
+
+	if (comp.comp_pkt.completion_status < 0) {
+		pr_err("Request for interrupt failed: 0x%x",
+		       comp.comp_pkt.completion_status);

MAINTAINERS +37 -0

+
+	/* Pass up the result. */
+	msg->address_hi = comp.int_desc.address >> 32;
+	msg->address_lo = comp.int_desc.address & 0xffffffff;
+	msg->data = comp.int_desc.data;
+
+	hv_pcichild_dec(hpdev, hv_pcidev_ref_by_slot);
+	return;
+
+free_int_desc:
+	kfree(int_desc);
+drop_reference:
+	hv_pcichild_dec(hpdev, hv_pcidev_ref_by_slot);
+return_null_message:
+	msg->address_hi = 0;
+	msg->address_lo = 0;
+	msg->data = 0;
+}
+
+/* HW Interrupt Chip Descriptor */
+static struct irq_chip hv_msi_irq_chip = {
+	.name			= "Hyper-V PCIe MSI",
+	.irq_compose_msi_msg	= hv_compose_msi_msg,
+	.irq_set_affinity	= hv_set_affinity,
+	.irq_ack		= irq_chip_ack_parent,
+	.irq_mask		= hv_irq_mask,
+	.irq_unmask		= hv_irq_unmask,
+};
+
+static irq_hw_number_t hv_msi_domain_ops_get_hwirq(struct msi_domain_info *info,
+						   msi_alloc_info_t *arg)
+{
+	return arg->msi_hwirq;
+}
+
+/**
+ * hv_msi_set_desc() - Create a "hardware IRQ" for a message.

MAINTAINERS +18 -0

+static void hv_msi_set_desc(msi_alloc_info_t *arg, struct msi_desc *desc)
+{
+	arg->msi_hwirq = (irq_hw_number_t)desc->msi_attrib.entry_nr |
+		(arg->msi_dev->devfn << 11) |
+		(pci_domain_nr(arg->msi_dev->bus) & 0xFFFFFFFF) << 19;
+}
+
+static struct msi_domain_ops hv_msi_ops = {
+	.get_hwirq	= hv_msi_domain_ops_get_hwirq,
+	.msi_prepare	= pci_msi_prepare,
+	.set_desc	= hv_msi_set_desc,
+	.msi_free	= hv_msi_free,
+};
+
+/**
+ * hv_pcie_free_irq_domain - Free IRQ domain
+ * @hbus:	The root PCI bus
+ */

MAINTAINERS +38 -0

+
+	irq_domain_remove(hbus->irq_domain);
+}
+
+/**
+ * hv_pcie_init_irq_domain() - Initialize IRQ domain
+ * @hbus:	The root PCI bus
+ *
+ * This function creates an IRQ domain which will be used for
+ * interrupts from devices that have been passed through.  These
+ * devices only support MSI and MSI-X, not line-based interrupts
+ * or simulations of line-based interrupts through PCIe's
+ * fabric-layer messages.  Because interrupts are remapped, we
+ * can support multi-message MSI here.
+ *
+ * Return: '0' on success and error value on failure
+ */
+static int hv_pcie_init_irq_domain(struct hv_pcibus_device *hbus)
+{
+	hbus->msi_info.chip = &hv_msi_irq_chip;
+	hbus->msi_info.chip_data = hbus;
+	hbus->msi_info.ops = &hv_msi_ops;
+	hbus->msi_info.flags = (MSI_FLAG_USE_DEF_DOM_OPS |
+		MSI_FLAG_USE_DEF_CHIP_OPS | MSI_FLAG_MULTI_PCI_MSI |
+		MSI_FLAG_PCI_MSIX);
+	hbus->msi_info.handler = handle_edge_irq;
+	hbus->msi_info.handler_name = "edge";
+	hbus->msi_info.data = hbus;
+	hbus->irq_domain = pci_msi_create_irq_domain(hbus->sysdata.fwnode,
+						     &hbus->msi_info,
+						     x86_vector_domain);
+	if (!hbus->irq_domain) {
+		pr_err("Failed to build an MSI IRQ domain\n");
+		return -ENODEV;
+	}
+
+	return 0;
+}

-----Original Message-----
From: Jiang Liu [mailto:[email protected]]
Sent: Wednesday, December 2, 2015 7:12 PM
To: Jake Oshins <[email protected]>; [email protected]; KY Srinivasan <[email protected]>; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; Haiyang Zhang <[email protected]>; [email protected]; [email protected]; [email protected]
Subject: Re: [PATCH v6 7/7] PCI: hv: New paravirtual PCI front-end for Hyper- V VMs

Quoted 2 lines · On 2015/11/3 5:33, [email protected] wrote:

From: Jake Oshins <[email protected]>

Quoted 16 lines

drivers/pci/host/hv_pcifront.c new file +16 -0

+
+/**
+ * hv_irq_unmask() - "Unmask" the IRQ by setting its current
+ * affinity.
+ * @data:	Describes the IRQ
+ *
+ * Build new a destination for the MSI and make a hypercall to
+ * update the Interrupt Redirection Table. "Device Logical ID"
+ * is built out of this PCI bus's instance GUID and the function
+ * number of the device.
+ */
+void hv_irq_unmask(struct irq_data *data)
+{
+	struct msi_desc *msi_desc = irq_data_get_msi_desc(data);
+	struct irq_cfg *cfg = irqd_cfg(data);
+	struct retarget_msi_interrupt params;

drivers/pci/host/hv_pcifront.c

Quoted 10 lines

drivers/pci/host/hv_pcifront.c new file +10 -0

+	struct hv_pcibus_device *hbus;
+	struct cpumask *dest;
+	struct pci_bus *pbus;
+	struct pci_dev *pdev;
+	int cpu;
+
+	dest = irq_data_get_affinity_mask(data);
+	pdev = msi_desc_to_pci_dev(msi_desc);
+	pbus = pdev->bus;
+	hbus = container_of(pbus->sysdata, struct hv_pcibus_device,

sysdata);

Quoted 11 lines

drivers/pci/host/hv_pcifront.c new file +11 -0

+
+	memset(&params, 0, sizeof(params));
+	params.partition_id = HV_PARTITION_ID_SELF;
+	params.source = 1; /* MSI(-X) */
+	params.address = msi_desc->msg.address_lo;
+	params.data = msi_desc->msg.data;
+	params.device_id = (hbus->hdev->dev_instance.b[5] << 24) |
+			   (hbus->hdev->dev_instance.b[4] << 16) |
+			   (hbus->hdev->dev_instance.b[7] << 8) |
+			   (hbus->hdev->dev_instance.b[6] & 0xf8) |
+			   PCI_FUNC(pdev->devfn);

drivers/pci/host/hv_pcifront.c

Quoted 4 lines

drivers/pci/host/hv_pcifront.c new file +4 -0

+	params.vector = cfg->vector;
+
+	for_each_cpu_and(cpu, dest, cpu_online_mask)
+		params.vp_mask |= (1 <<

vmbus_cpu_number_to_vp_number(cpu));
No knowledge about the HV implementation details, but feel some chances of race here between hv_irq_unmask(), hv_set_affinity() and cpu_up()/cpu_down() when accessing 'dest' and cpu_online_mask.

-----Original Message-----
From: [email protected] [mailto:[email protected]]
Sent: Monday, November 2, 2015 1:33 PM
To: [email protected]; KY Srinivasan <[email protected]>; linux- [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; Haiyang Zhang <[email protected]>; [email protected]; [email protected]; [email protected]
Cc: Jake Oshins <[email protected]>
Subject: [PATCH v6 0/7] PCI: hv: New paravirtual PCI front-end for Hyper-V VMs

From: Jake Oshins <[email protected]>

This version of this patch series incorporates feedback from Andy Shevchenko.

First, export functions that allow correlating Hyper-V virtual processors and Linux cpus, along with the means for invoking a hypercall that targets interrupts at chosen vectors on specfic cpus.

Second, mark various parts of IRQ domain related code as exported, so that this PCI front-end can implement an IRQ domain as part of a module. (The alternative would be to pull all this into the kernel, which would pull in a lot of other Hyper-V related code, as this IRQ domain depends on hv_vmbus.ko.)

Third, modify PCI so that new root PCI buses can be marked with an associated
fwnode_handle, and so that root PCI buses can look up their associated IRQ domain by that handle.

Fourth, introduce a new driver, hv_pcifront, which eposes root PCI buses in a Hyper-V VM. These root PCI buses expose real PCIe devices, or PCI Virtual Functions.

Jake Oshins (7):
drivers:hv: Export a function that maps Linux CPU num onto Hyper-V
proc num
drivers:hv: Export hv_do_hypercall()
PCI: Make it possible to implement a PCI MSI IRQ Domain in a module.
PCI: Add fwnode_handle to pci_sysdata
PCI: irqdomain: Look up IRQ domain by fwnode_handle drivers:hv: Define the channel type of Hyper-V PCI Express
pass-through
PCI: hv: New paravirtual PCI front-end for Hyper-V VMs

 MAINTAINERS                    |    1 +
 arch/x86/include/asm/msi.h     |    4 +
 arch/x86/include/asm/pci.h     |   13 +
 arch/x86/kernel/apic/msi.c     |    5 +-
 arch/x86/kernel/apic/vector.c  |    2 +
 drivers/hv/hv.c                |   20 +-
 drivers/hv/hyperv_vmbus.h      |    2 +-
 drivers/hv/vmbus_drv.c         |   17 +
 drivers/pci/Kconfig            |    7 +
 drivers/pci/host/Makefile      |    1 +
 drivers/pci/host/hv_pcifront.c | 2267
++++++++++++++++++++++++++++++++++++++++
 drivers/pci/msi.c              |    4 +
 drivers/pci/probe.c            |   14 +
 include/asm-generic/pci.h      |    4 +
 include/linux/hyperv.h         |   14 +
 kernel/irq/chip.c              |    1 +
 kernel/irq/irqdomain.c         |    2 +
 17 files changed, 2365 insertions(+), 13 deletions(-)
 create mode 100644 drivers/pci/host/hv_pcifront.c

--
1.9.1