ppc: Add "native" POWER8 platform

Instead of an array of fixed sized blocks, use a list, as we will need to have sources with variable number of interrupts. SPAPR only uses a single entry. Native will create more. If performance becomes an issue we can add some hashed lookup but for now this will do fine.

Signed-off-by Benjamin Herrenschmidt <[email protected]>

---
 hw/intc/xics.c        | 86 +++++++++++++++++++++++++++++++--------------------
 hw/intc/xics_kvm.c    | 28 +++++++++--------
 hw/intc/xics_spapr.c  | 75 ++++++++++++++++++++++++--------------------
 hw/ppc/spapr_events.c |  2 +-
 hw/ppc/spapr_pci.c    |  4 +--
 hw/ppc/spapr_vio.c    |  2 +-
 include/hw/ppc/xics.h | 10 +++---
 7 files changed, 118 insertions(+), 89 deletions(-)

hw/intc/xics.c +13 -9

index d21471f..c4ac057 100644
@@ -79,13 +79,16 @@ void xics_cpu_setup(XICSState *xics, PowerPCCPU *cpu)
 static void xics_common_reset(DeviceState *d)
 {
     XICSState *xics = XICS_COMMON(d);
+    ICSState *ics;
     int i;
 
     for (i = 0; i < xics->nr_servers; i++) {
         device_reset(DEVICE(&xics->ss[i]));
     }
 
-    device_reset(DEVICE(xics->ics));
+    QLIST_FOREACH(ics, &xics->ics, list) {
+        device_reset(DEVICE(ics));
+    }
 }
 
 static void xics_prop_get_nr_irqs(Object *obj, Visitor *v,

@@ -117,7 +120,6 @@ static void xics_prop_set_nr_irqs(Object *obj, Visitor *v,
     }
 
     assert(info->set_nr_irqs);
-    assert(xics->ics);
     info->set_nr_irqs(xics, value, errp);
 }
 

@@ -195,33 +197,35 @@ static void ics_reject(ICSState *ics, int nr);
 static void ics_resend(ICSState *ics);
 static void ics_eoi(ICSState *ics, int nr);
 
-static void icp_check_ipi(XICSState *xics, int server)
+static void icp_check_ipi(ICPState *ss, int server)
 {
-    ICPState *ss = xics->ss + server;
-
     if (XISR(ss) && (ss->pending_priority <= ss->mfrr)) {
         return;
     }
 
     trace_xics_icp_check_ipi(server, ss->mfrr);
 
-    if (XISR(ss)) {
-        ics_reject(xics->ics, XISR(ss));
+    if (XISR(ss) && ss->xirr_owner) {
+        ics_reject(ss->xirr_owner, XISR(ss));
     }
 
     ss->xirr = (ss->xirr & ~XISR_MASK) | XICS_IPI;
     ss->pending_priority = ss->mfrr;
+    ss->xirr_owner = NULL;
     qemu_irq_raise(ss->output);
 }
 
 static void icp_resend(XICSState *xics, int server)
 {
     ICPState *ss = xics->ss + server;
+    ICSState *ics;
 
     if (ss->mfrr < CPPR(ss)) {
-        icp_check_ipi(xics, server);
+        icp_check_ipi(ss, server);
+    }
+    QLIST_FOREACH(ics, &xics->ics, list) {
+        ics_resend(ics);
     }
-    ics_resend(xics->ics);
 }
 
 void icp_set_cppr(XICSState *xics, int server, uint8_t cppr)

hw/intc/xics.c +12 -3

         }
     } else {
         if (!XISR(ss)) {

@@ -254,7 +261,7 @@ void icp_set_mfrr(XICSState *xics, int server, uint8_t mfrr)
 
     ss->mfrr = mfrr;
     if (mfrr < CPPR(ss)) {
-        icp_check_ipi(xics, server);
+        icp_check_ipi(ss, server);
     }
 }
 

@@ -265,6 +272,7 @@ uint32_t icp_accept(ICPState *ss)
     qemu_irq_lower(ss->output);
     ss->xirr = ss->pending_priority << 24;
     ss->pending_priority = 0xff;
+    ss->xirr_owner = NULL;
 
     trace_xics_icp_accept(xirr, ss->xirr);
 

@@ -282,30 +290,40 @@ uint32_t icp_ipoll(ICPState *ss, uint32_t *mfrr)
 void icp_eoi(XICSState *xics, int server, uint32_t xirr)
 {
     ICPState *ss = xics->ss + server;
+    ICSState *ics;
+    uint32_t irq;
 
     /* Send EOI -> ICS */
     ss->xirr = (ss->xirr & ~CPPR_MASK) | (xirr & CPPR_MASK);
     trace_xics_icp_eoi(server, xirr, ss->xirr);
-    ics_eoi(xics->ics, xirr & XISR_MASK);
+    irq = xirr & XISR_MASK;
+    QLIST_FOREACH(ics, &xics->ics, list) {
+        if (ics_valid_irq(ics, irq)) {
+            ics_eoi(ics, irq);
+        }
+    }
     if (!XISR(ss)) {
         icp_resend(xics, server);
     }
 }
 
-static void icp_irq(XICSState *xics, int server, int nr, uint8_t priority)
+static void icp_irq(ICSState *ics, int server, int nr, uint8_t priority)
 {
+    XICSState *xics = ics->xics;
     ICPState *ss = xics->ss + server;
 

hw/intc/xics.c +14 -17

+            ics_reject(ss->xirr_owner, XISR(ss));
+            ss->xirr_owner = NULL;
         }
         ss->xirr = (ss->xirr & ~XISR_MASK) | (nr & XISR_MASK);
+        ss->xirr_owner = ics;
         ss->pending_priority = priority;
         trace_xics_icp_raise(ss->xirr, ss->pending_priority);
         qemu_irq_raise(ss->output);

@@ -388,8 +406,7 @@ static void resend_msi(ICSState *ics, int srcno)
     if (irq->status & XICS_STATUS_REJECTED) {
         irq->status &= ~XICS_STATUS_REJECTED;
         if (irq->priority != 0xff) {
-            icp_irq(ics->xics, irq->server, srcno + ics->offset,
-                    irq->priority);
+            icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
         }
     }
 }

@@ -402,7 +419,7 @@ static void resend_lsi(ICSState *ics, int srcno)
         && (irq->status & XICS_STATUS_ASSERTED)
         && !(irq->status & XICS_STATUS_SENT)) {
         irq->status |= XICS_STATUS_SENT;
-        icp_irq(ics->xics, irq->server, srcno + ics->offset, irq->priority);
+        icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
     }
 }
 

@@ -417,7 +434,7 @@ static void set_irq_msi(ICSState *ics, int srcno, int val)
             irq->status |= XICS_STATUS_MASKED_PENDING;
             trace_xics_masked_pending();
         } else  {
-            icp_irq(ics->xics, irq->server, srcno + ics->offset, irq->priority);
+            icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
         }
     }
 }

@@ -456,7 +473,7 @@ static void write_xive_msi(ICSState *ics, int srcno)
     }
 
     irq->status &= ~XICS_STATUS_MASKED_PENDING;
-    icp_irq(ics->xics, irq->server, srcno + ics->offset, irq->priority);
+    icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
 }
 
 static void write_xive_lsi(ICSState *ics, int srcno)

@@ -642,28 +659,23 @@ static const TypeInfo ics_info = {
 /*
  * Exported functions
  */
-int xics_find_source(XICSState *xics, int irq)
+ICSState *xics_find_source(XICSState *xics, int irq)
 {
-    int sources = 1;
-    int src;
+    ICSState *ics;
 
-    /* FIXME: implement multiple sources */
-    for (src = 0; src < sources; ++src) {
-        ICSState *ics = &xics->ics[src];
+    QLIST_FOREACH(ics, &xics->ics, list) {
         if (ics_valid_irq(ics, irq)) {
-            return src;
+            return ics;
         }
     }
-
-    return -1;
+    return NULL;
 }
 
 qemu_irq xics_get_qirq(XICSState *xics, int irq)
 {
-    int src = xics_find_source(xics, irq);
+    ICSState *ics = xics_find_source(xics, irq);
 
-    if (src >= 0) {
-        ICSState *ics = &xics->ics[src];
+    if (ics) {
         return ics->qirqs[irq - ics->offset];
     }
 

hw/intc/xics.c +4 -0

+    xics->nr_irqs = nr_irqs;
+    if (ics) {
+        ics->nr_irqs = nr_irqs;
+    }
 }
 
 void xics_set_nr_servers(XICSState *xics, uint32_t nr_servers, Error **errp)

hw/intc/xics_kvm.c +14 -12

index 7d86157..a478d25 100644
@@ -356,11 +356,6 @@ static void xics_kvm_cpu_setup(XICSState *xics, PowerPCCPU *cpu)
     }
 }
 
-static void xics_kvm_set_nr_irqs(XICSState *xics, uint32_t nr_irqs, Error **errp)
-{
-    xics->nr_irqs = xics->ics->nr_irqs = nr_irqs;
-}
-
 static void xics_kvm_set_nr_servers(XICSState *xics, uint32_t nr_servers,
                                     Error **errp)
 {

@@ -391,6 +386,7 @@ static void xics_kvm_realize(DeviceState *dev, Error **errp)
 {
     KVMXICSState *xicskvm = KVM_XICS(dev);
     XICSState *xics = XICS_COMMON(dev);
+    ICSState *ics;
     int i, rc;
     Error *error = NULL;
     struct kvm_create_device xics_create_device = {

@@ -442,10 +438,12 @@ static void xics_kvm_realize(DeviceState *dev, Error **errp)
 
     xicskvm->kernel_xics_fd = xics_create_device.fd;
 
-    object_property_set_bool(OBJECT(xics->ics), true, "realized", &error);
-    if (error) {
-        error_propagate(errp, error);
-        goto fail;
+    QLIST_FOREACH(ics, &xics->ics, list) {
+        object_property_set_bool(OBJECT(ics), true, "realized", &error);
+        if (error) {
+            error_propagate(errp, error);
+            goto fail;
+        }
     }
 
     assert(xics->nr_servers);

@@ -473,10 +471,14 @@ fail:
 static void xics_kvm_initfn(Object *obj)
 {
     XICSState *xics = XICS_COMMON(obj);
+    ICSState *ics;
+
+    QLIST_INIT(&xics->ics);
 
-    xics->ics = ICS(object_new(TYPE_KVM_ICS));
-    object_property_add_child(obj, "ics", OBJECT(xics->ics), NULL);
-    xics->ics->xics = xics;
+    ics = ICS(object_new(TYPE_KVM_ICS));
+    object_property_add_child(obj, "ics", OBJECT(ics), NULL);
+    ics->xics = xics;
+    QLIST_INSERT_HEAD(&xics->ics, ics, list);
 }
 
 static void xics_kvm_class_init(ObjectClass *oc, void *data)

hw/intc/xics_kvm.c +0 -0

     xsc->set_nr_servers = xics_kvm_set_nr_servers;
 }
 

hw/intc/xics_spapr.c +0 -0

index fb508cd..d75fcf0 100644
@@ -111,10 +111,10 @@ static void rtas_set_xive(PowerPCCPU *cpu, sPAPRMachineState *spapr,
                           uint32_t nargs, target_ulong args,
                           uint32_t nret, target_ulong rets)

hw/intc/xics_spapr.c +26 -17

@@ -139,10 +139,10 @@ static void rtas_get_xive(PowerPCCPU *cpu, sPAPRMachineState *spapr,
                           uint32_t nargs, target_ulong args,
                           uint32_t nret, target_ulong rets)
 {
-    ICSState *ics = spapr->xics->ics;
+    ICSState *ics = QLIST_FIRST(&spapr->xics->ics);
     uint32_t nr;
 
-    if ((nargs != 1) || (nret != 3)) {
+    if ((nargs != 1) || (nret != 3) || !ics) {
         rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
         return;
     }

@@ -164,10 +164,10 @@ static void rtas_int_off(PowerPCCPU *cpu, sPAPRMachineState *spapr,
                          uint32_t nargs, target_ulong args,
                          uint32_t nret, target_ulong rets)
 {
-    ICSState *ics = spapr->xics->ics;
+    ICSState *ics = QLIST_FIRST(&spapr->xics->ics);
     uint32_t nr;
 
-    if ((nargs != 1) || (nret != 1)) {
+    if ((nargs != 1) || (nret != 1) || !ics) {
         rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
         return;
     }

@@ -190,10 +190,10 @@ static void rtas_int_on(PowerPCCPU *cpu, sPAPRMachineState *spapr,
                         uint32_t nargs, target_ulong args,
                         uint32_t nret, target_ulong rets)
 {
-    ICSState *ics = spapr->xics->ics;
+    ICSState *ics = QLIST_FIRST(&spapr->xics->ics);
     uint32_t nr;
 
-    if ((nargs != 1) || (nret != 1)) {
+    if ((nargs != 1) || (nret != 1) || !ics) {
         rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
         return;
     }

@@ -215,6 +215,7 @@ static void rtas_int_on(PowerPCCPU *cpu, sPAPRMachineState *spapr,
 static void xics_spapr_realize(DeviceState *dev, Error **errp)
 {
     XICSState *xics = XICS(dev);
+    ICSState *ics;
     Error *error = NULL;
     int i;
 

@@ -236,10 +237,12 @@ static void xics_spapr_realize(DeviceState *dev, Error **errp)
     spapr_register_hypercall(H_EOI, h_eoi);
     spapr_register_hypercall(H_IPOLL, h_ipoll);
 
-    object_property_set_bool(OBJECT(xics->ics), true, "realized", &error);
-    if (error) {
-        error_propagate(errp, error);
-        return;
+    QLIST_FOREACH(ics, &xics->ics, list) {
+        object_property_set_bool(OBJECT(ics), true, "realized", &error);
+        if (error) {
+            error_propagate(errp, error);
+            return;
+        }
     }
 
     for (i = 0; i < xics->nr_servers; i++) {

@@ -254,10 +257,14 @@ static void xics_spapr_realize(DeviceState *dev, Error **errp)
 static void xics_spapr_initfn(Object *obj)
 {
     XICSState *xics = XICS(obj);
+    ICSState *ics;
+
+    QLIST_INIT(&xics->ics);
 
-    xics->ics = ICS(object_new(TYPE_ICS));
-    object_property_add_child(obj, "ics", OBJECT(xics->ics), NULL);
-    xics->ics->xics = xics;
+    ics = ICS(object_new(TYPE_ICS));    
+    object_property_add_child(obj, "ics", OBJECT(ics), NULL);
+    ics->xics = xics;
+    QLIST_INSERT_HEAD(&xics->ics, ics, list);
 }
 
 static void xics_spapr_class_init(ObjectClass *oc, void *data)

@@ -303,29 +310,31 @@ static int ics_find_free_block(ICSState *ics, int num, int alignnum)
     return -1;
 }
 
-int xics_spapr_alloc(XICSState *xics, int src, int irq_hint, bool lsi)
+int xics_spapr_alloc(XICSState *xics, int irq_hint, bool lsi)
 {
-    ICSState *ics = &xics->ics[src];
+    ICSState *ics = QLIST_FIRST(&xics->ics);
     int irq;
 
+    if (!ics) {
+        return -1;
+    }
     if (irq_hint) {
-        assert(src == xics_find_source(xics, irq_hint));
         if (!ICS_IRQ_FREE(ics, irq_hint - ics->offset)) {
-            trace_xics_alloc_failed_hint(src, irq_hint);
+            trace_xics_alloc_failed_hint(0, irq_hint);
             return -1;
         }
         irq = irq_hint;
     } else {
         irq = ics_find_free_block(ics, 1, 1);
         if (irq < 0) {

hw/intc/xics_spapr.c +11 -13

     return irq;
 }

@@ -334,12 +343,15 @@ int xics_spapr_alloc(XICSState *xics, int src, int irq_hint, bool lsi)
  * Allocate block of consecutive IRQs, and return the number of the first IRQ in the block.
  * If align==true, aligns the first IRQ number to num.
  */
-int xics_spapr_alloc_block(XICSState *xics, int src, int num, bool lsi, bool align)
+int xics_spapr_alloc_block(XICSState *xics, int num, bool lsi, bool align)
 {
+    ICSState *ics = QLIST_FIRST(&xics->ics);
     int i, first = -1;
-    ICSState *ics = &xics->ics[src];
 
-    assert(src == 0);
+    if (!ics) {
+        return -1;
+    }
+
     /*
      * MSIMesage::data is used for storing VIRQ so
      * it has to be aligned to num to support multiple

@@ -362,7 +374,7 @@ int xics_spapr_alloc_block(XICSState *xics, int src, int num, bool lsi, bool ali
     }
     first += ics->offset;
 
-    trace_xics_alloc_block(src, first, num, lsi, align);
+    trace_xics_alloc_block(0, first, num, lsi, align);
 
     return first;
 }

@@ -373,7 +385,7 @@ static void ics_free(ICSState *ics, int srcno, int num)
 
     for (i = srcno; i < srcno + num; ++i) {
         if (ICS_IRQ_FREE(ics, i)) {
-            trace_xics_ics_free_warn(ics - ics->xics->ics, i + ics->offset);
+            trace_xics_ics_free_warn(0, i + ics->offset);
         }
         memset(&ics->irqs[i], 0, sizeof(ICSIRQState));
     }

@@ -381,15 +393,10 @@ static void ics_free(ICSState *ics, int srcno, int num)
 
 void xics_spapr_free(XICSState *xics, int irq, int num)
 {
-    int src = xics_find_source(xics, irq);
-
-    if (src >= 0) {
-        ICSState *ics = &xics->ics[src];
-
-        /* FIXME: implement multiple sources */
-        assert(src == 0);
+    ICSState *ics = xics_find_source(xics, irq);
 
-        trace_xics_ics_free(ics - xics->ics, irq, num);
+    if (ics) {
+        trace_xics_ics_free(0, irq, num);
         ics_free(ics, irq - ics->offset, num);
     }
 }

hw/ppc/spapr_events.c +1 -1

index c06deea..6335ead 100644
@@ -587,7 +587,7 @@ out_no_events:
 void spapr_events_init(sPAPRMachineState *spapr)
 {
     QTAILQ_INIT(&spapr->pending_events);
-    spapr->check_exception_irq = xics_spapr_alloc(spapr->xics, 0, 0, false);
+    spapr->check_exception_irq = xics_spapr_alloc(spapr->xics, 0, false);
     spapr->epow_notifier.notify = spapr_powerdown_req;
     qemu_register_powerdown_notifier(&spapr->epow_notifier);
     spapr_rtas_register(RTAS_CHECK_EXCEPTION, "check-exception",

hw/ppc/spapr_pci.c +2 -2

index cf3192e..9b13f85 100644
@@ -351,7 +351,7 @@ static void rtas_ibm_change_msi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
     }
 
     /* Allocate MSIs */
-    irq = xics_spapr_alloc_block(spapr->xics, 0, req_num, false,
+    irq = xics_spapr_alloc_block(spapr->xics, req_num, false,
                            ret_intr_type == RTAS_TYPE_MSI);
     if (!irq) {
         error_report("Cannot allocate MSIs for device %x", config_addr);

@@ -1360,7 +1360,7 @@ static void spapr_phb_realize(DeviceState *dev, Error **errp)
     for (i = 0; i < PCI_NUM_PINS; i++) {
         uint32_t irq;
 
-        irq = xics_spapr_alloc_block(spapr->xics, 0, 1, true, false);
+        irq = xics_spapr_alloc_block(spapr->xics, 1, true, false);
         if (!irq) {
             error_setg(errp, "spapr_allocate_lsi failed");
             return;

hw/ppc/spapr_vio.c +1 -1

index fc731eb..1a84815 100644
@@ -462,7 +462,7 @@ static void spapr_vio_busdev_realize(DeviceState *qdev, Error **errp)
         dev->qdev.id = id;
     }
 
-    dev->irq = xics_spapr_alloc(spapr->xics, 0, dev->irq, false);
+    dev->irq = xics_spapr_alloc(spapr->xics, dev->irq, false);
     if (!dev->irq) {
         error_setg(errp, "can't allocate IRQ");
         return;

include/hw/ppc/xics.h +1 -1

index e670e89..12fc584 100644
@@ -79,7 +79,7 @@ struct XICSState {
     uint32_t nr_servers;
     uint32_t nr_irqs;
     ICPState *ss;
-    ICSState *ics;
+    QLIST_HEAD(, ICSState) ics;
 };
 
 #define TYPE_ICP "icp"

include/hw/ppc/xics.h +4 -3

     uint32_t xirr;
     uint8_t pending_priority;
     uint8_t mfrr;

@@ -139,6 +140,7 @@ struct ICSState {
     qemu_irq *qirqs;
     ICSIRQState *irqs;
     XICSState *xics;
+    QLIST_ENTRY(ICSState) list;
 };
 
 static inline bool ics_valid_irq(ICSState *ics, uint32_t nr)

@@ -167,8 +169,8 @@ struct ICSIRQState {
 
 qemu_irq xics_get_qirq(XICSState *icp, int irq);
 
-int xics_spapr_alloc(XICSState *icp, int src, int irq_hint, bool lsi);
-int xics_spapr_alloc_block(XICSState *icp, int src, int num, bool lsi, bool align);
+int xics_spapr_alloc(XICSState *icp, int irq_hint, bool lsi);
+int xics_spapr_alloc_block(XICSState *icp, int num, bool lsi, bool align);
 void xics_spapr_free(XICSState *icp, int irq, int num);
 
 void xics_cpu_setup(XICSState *icp, PowerPCCPU *cpu);

@@ -189,6 +191,6 @@ void ics_set_irq_type(ICSState *ics, int srcno, bool lsi);
 
 void xics_set_nr_irqs(XICSState *icp, uint32_t nr_irqs, Error **errp);
 void xics_set_nr_servers(XICSState *icp, uint32_t nr_servers, Error **errp);
-int xics_find_source(XICSState *icp, int irq);
+ICSState *xics_find_source(XICSState *icp, int irq);
 
 #endif /* __XICS_H__ */

This will make life easier for dealing with dynamically configured ICSes such as PHB3

Signed-off-by Benjamin Herrenschmidt <[email protected]>

---
 include/hw/ppc/xics.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

include/hw/ppc/xics.h +1 -1

index 12fc584..51a63cb 100644
@@ -145,7 +145,7 @@ struct ICSState {
 
 static inline bool ics_valid_irq(ICSState *ics, uint32_t nr)
 {
-    return (nr >= ics->offset)
+    return (ics->offset != 0) && (nr >= ics->offset)
         && (nr < (ics->offset + ics->nr_irqs));
 }
 

It will not be used by the native implementation. This allows us to also remove the include of spapr.h from the common code

Signed-off-by Benjamin Herrenschmidt <[email protected]>

---
 hw/intc/xics.c        | 12 ------------
 hw/intc/xics_kvm.c    | 13 ++++++++++++-
 hw/intc/xics_spapr.c  | 13 ++++++++++++-
 include/hw/ppc/xics.h |  1 -
 4 files changed, 24 insertions(+), 15 deletions(-)

hw/intc/xics.c +0 -12

index c4ac057..0c355f4 100644
@@ -28,7 +28,6 @@
 #include "hw/hw.h"
 #include "trace.h"
 #include "qemu/timer.h"
-#include "hw/ppc/spapr.h"
 #include "hw/ppc/xics.h"
 #include "qemu/error-report.h"
 #include "qapi/visitor.h"

@@ -694,17 +693,6 @@ void ics_set_irq_type(ICSState *ics, int srcno, bool lsi)
  * XICS
  */
 
-void xics_set_nr_irqs(XICSState *xics, uint32_t nr_irqs, Error **errp)
-{
-    ICSState *ics = QLIST_FIRST(&xics->ics);
-
-    /* This needs to be deprecated ... */
-    xics->nr_irqs = nr_irqs;
-    if (ics) {
-        ics->nr_irqs = nr_irqs;
-    }
-}
-
 void xics_set_nr_servers(XICSState *xics, uint32_t nr_servers, Error **errp)
 {
     int i;

hw/intc/xics_kvm.c +1 -0

index a478d25..6fbc715 100644
@@ -468,6 +468,17 @@ fail:
     kvmppc_define_rtas_kernel_token(0, "ibm,int-off");
 }
 
+static void xics_kvm_set_nr_irqs(XICSState *xics, uint32_t nr_irqs, Error **errp)

hw/intc/xics_kvm.c +1 -1

 static void xics_kvm_initfn(Object *obj)
 {
     XICSState *xics = XICS_COMMON(obj);

@@ -488,7 +499,7 @@ static void xics_kvm_class_init(ObjectClass *oc, void *data)
 
     dc->realize = xics_kvm_realize;
     xsc->cpu_setup = xics_kvm_cpu_setup;
-    xsc->set_nr_irqs = xics_set_nr_irqs;
+    xsc->set_nr_irqs = xics_kvm_set_nr_irqs;
     xsc->set_nr_servers = xics_kvm_set_nr_servers;
 }
 

hw/intc/xics_spapr.c +12 -1

index d75fcf0..3092f8d 100644
@@ -267,13 +267,24 @@ static void xics_spapr_initfn(Object *obj)
     QLIST_INSERT_HEAD(&xics->ics, ics, list);
 }
 
+static void xics_spapr_set_nr_irqs(XICSState *xics, uint32_t nr_irqs, Error **errp)
+{
+    ICSState *ics = QLIST_FIRST(&xics->ics);
+
+    /* This needs to be deprecated ... */
+    xics->nr_irqs = nr_irqs;
+    if (ics) {
+        ics->nr_irqs = nr_irqs;
+    }
+}
+
 static void xics_spapr_class_init(ObjectClass *oc, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(oc);
     XICSStateClass *xsc = XICS_SPAPR_CLASS(oc);
 
     dc->realize = xics_spapr_realize;
-    xsc->set_nr_irqs = xics_set_nr_irqs;
+    xsc->set_nr_irqs = xics_spapr_set_nr_irqs;
     xsc->set_nr_servers = xics_set_nr_servers;
 }
 

include/hw/ppc/xics.h +0 -1

index 51a63cb..9e5b751 100644
@@ -189,7 +189,6 @@ void ics_write_xive(ICSState *ics, int nr, int server,
 
 void ics_set_irq_type(ICSState *ics, int srcno, bool lsi);
 
-void xics_set_nr_irqs(XICSState *icp, uint32_t nr_irqs, Error **errp);
 void xics_set_nr_servers(XICSState *icp, uint32_t nr_servers, Error **errp);
 ICSState *xics_find_source(XICSState *icp, int irq);
 

Signed-off-by Benjamin Herrenschmidt <[email protected]>

---
 hw/intc/xics.c        | 6 ++++++
 hw/intc/xics_spapr.c  | 3 +--
 include/hw/ppc/xics.h | 1 +
 3 files changed, 8 insertions(+), 2 deletions(-)

hw/intc/xics.c +6 -0

index 0c355f4..3cd696f 100644
@@ -90,6 +90,12 @@ static void xics_common_reset(DeviceState *d)
     }
 }
 
+void xics_add_ics(XICSState *xics, ICSState *ics)
+{
+    ics->xics = xics;
+    QLIST_INSERT_HEAD(&xics->ics, ics, list);
+}
+
 static void xics_prop_get_nr_irqs(Object *obj, Visitor *v,
                                   void *opaque, const char *name, Error **errp)
 {

hw/intc/xics_spapr.c +1 -2

index 3092f8d..fc331d8 100644
@@ -263,8 +263,7 @@ static void xics_spapr_initfn(Object *obj)
 
     ics = ICS(object_new(TYPE_ICS));    
     object_property_add_child(obj, "ics", OBJECT(ics), NULL);
-    ics->xics = xics;
-    QLIST_INSERT_HEAD(&xics->ics, ics, list);
+    xics_add_ics(xics, ics);
 }
 
 static void xics_spapr_set_nr_irqs(XICSState *xics, uint32_t nr_irqs, Error **errp)

include/hw/ppc/xics.h +1 -0

index 9e5b751..5acb329 100644
@@ -191,5 +191,6 @@ void ics_set_irq_type(ICSState *ics, int srcno, bool lsi);
 
 void xics_set_nr_servers(XICSState *icp, uint32_t nr_servers, Error **errp);
 ICSState *xics_find_source(XICSState *icp, int irq);
+void xics_add_ics(XICSState *xics, ICSState *ics);
 
 #endif /* __XICS_H__ */

The existing implementation becomes the "ics-simple" subclass of ICS, so there should be no change in behaviour for SPAPR.

This will allow different implementations for the source controllers such as the MSI support of PHB3 on Power8 which uses in-memory state tables for example.

Signed-off-by Benjamin Herrenschmidt <[email protected]>

include/hw/ppc/xics.h +7 -3

+
 #define TYPE_KVM_ICS "icskvm"
 #define KVM_ICS(obj) OBJECT_CHECK(ICSState, (obj), TYPE_KVM_ICS)
 

@@ -129,6 +132,9 @@ struct ICSStateClass {
 
     void (*pre_save)(ICSState *s);
     int (*post_load)(ICSState *s, int version_id);
+    void (*reject)(ICSState *s, uint32_t irq);
+    void (*resend)(ICSState *s);
+    void (*eoi)(ICSState *s, uint32_t irq);
 };
 
 struct ICSState {

@@ -184,10 +190,10 @@ uint32_t icp_accept(ICPState *ss);
 uint32_t icp_ipoll(ICPState *ss, uint32_t *mfrr);
 void icp_eoi(XICSState *icp, int server, uint32_t xirr);
 
-void ics_write_xive(ICSState *ics, int nr, int server,
-                    uint8_t priority, uint8_t saved_priority);
+void ics_simple_write_xive(ICSState *ics, int nr, int server,
+                           uint8_t priority, uint8_t saved_priority);
 
-void ics_set_irq_type(ICSState *ics, int srcno, bool lsi);
+void ics_simple_set_irq_type(ICSState *ics, int srcno, bool lsi);
 
 void xics_set_nr_servers(XICSState *icp, uint32_t nr_servers, Error **errp);
 ICSState *xics_find_source(XICSState *icp, int irq);

This provides MMIO based ICP access as found on POWER8

Signed-off-by Benjamin Herrenschmidt <[email protected]>

---
 default-configs/ppc64-softmmu.mak |   3 +-
 hw/intc/Makefile.objs             |   1 +
 hw/intc/xics_native.c             | 294 ++++++++++++++++++++++++++++++++++++++
 include/hw/ppc/xics.h             |  14 ++
 4 files changed, 311 insertions(+), 1 deletion(-)
 create mode 100644 hw/intc/xics_native.c

default-configs/ppc64-softmmu.mak +2 -1

index 516a6e2..d30176e 100644
@@ -49,8 +49,9 @@ CONFIG_PLATFORM_BUS=y
 CONFIG_ETSEC=y
 CONFIG_LIBDECNUMBER=y
 # For pSeries
-CONFIG_XICS=$(CONFIG_PSERIES)
+CONFIG_XICS=$(or $(CONFIG_PSERIES),$(CONFIG_POWERNV))
 CONFIG_XICS_SPAPR=$(CONFIG_PSERIES)
+CONFIG_XICS_NATIVE=$(CONFIG_POWERNV)
 CONFIG_XICS_KVM=$(and $(CONFIG_PSERIES),$(CONFIG_KVM))
 # For PReP
 CONFIG_MC146818RTC=y

hw/intc/Makefile.objs +1 -0

index e24cb03..104a169 100644
@@ -27,6 +27,7 @@ obj-$(CONFIG_OPENPIC_KVM) += openpic_kvm.o
 obj-$(CONFIG_SH4) += sh_intc.o
 obj-$(CONFIG_XICS) += xics.o
 obj-$(CONFIG_XICS_SPAPR) += xics_spapr.o
+obj-$(CONFIG_XICS_NATIVE) += xics_native.o
 obj-$(CONFIG_XICS_KVM) += xics_kvm.o
 obj-$(CONFIG_ALLWINNER_A10_PIC) += allwinner-a10-pic.o
 obj-$(CONFIG_S390_FLIC) += s390_flic.o

hw/intc/xics_native.c new file +0 -0

new file mode 100644
index 0000000..3f488f3

hw/intc/xics_native.c new file +244 -0

+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include "hw/hw.h"
+#include "trace.h"
+#include "qemu/timer.h"
+#include "hw/ppc/xics.h"
+#include "qemu/error-report.h"
+#include "qapi/visitor.h"
+
+#include <libfdt.h>
+
+//#define DEBUG_MM(fmt...)      printf(fmt)
+#define DEBUG_MM(fmt...)        do { } while(0)
+
+static void xics_native_initfn(Object *obj)
+{
+    XICSState *xics = XICS_NATIVE(obj);
+
+    QLIST_INIT(&xics->ics);
+}
+
+static uint64_t icp_mm_read(void *opaque, hwaddr addr, unsigned width)
+{
+    XICSState *s = opaque;
+    int32_t cpu_id, server;
+    uint32_t val;
+    ICPState *ss;
+    bool byte0 = (width == 1 && (addr & 0x3) == 0);
+
+    cpu_id = (addr & (ICP_MM_SIZE - 1)) >> 12;
+    server = get_cpu_index_by_dt_id(cpu_id);
+    if (server < 0) {
+        fprintf(stderr, "XICS: Bad ICP server %d\n", server);
+        goto bad_access;
+    }
+    ss = &s->ss[server];
+
+    switch(addr & 0xffc) {
+    case 0: /* poll */
+        val = icp_ipoll(ss, NULL);
+        if (byte0) {
+            val >>= 24;
+        } else if (width != 4) {
+            goto bad_access;
+        }
+        break;
+    case 4: /* xirr */
+        if (byte0) {
+            val = icp_ipoll(ss, NULL) >> 24;
+        } else if (width == 4) {
+            val = icp_accept(ss);
+        } else {
+            goto bad_access;
+        }
+        break;
+    case 12:
+        if (byte0) {
+            val = ss->mfrr;
+        } else {
+            goto bad_access;
+        }
+        break;
+    case 16:
+        if (width == 4) {
+            val = ss->links[0];
+        } else {
+            goto bad_access;
+        }
+        break;
+    case 20:
+        if (width == 4) {
+            val = ss->links[1];
+        } else {
+            goto bad_access;
+        }
+        break;
+    case 24:
+        if (width == 4) {
+            val = ss->links[2];
+        } else {
+            goto bad_access;
+        }
+        break;
+    default:
+bad_access:
+        fprintf(stderr, "XICS: Bad ICP access %llx/%d\n",
+                (unsigned long long)addr, width);
+        val = 0xffffffff;
+    }
+    DEBUG_MM("icp_mm_read(addr=%016llx,serv=0x%x/%d,off=%d,w=%d,val=0x%08x)\n",
+             (unsigned long long)addr, cpu_id, server, (int)(addr & 0xffc),
+             width, val);
+
+    return val;
+}
+
+static void icp_mm_write(void *opaque, hwaddr addr, uint64_t val,
+                        unsigned width)
+{
+    XICSState *s = opaque;
+    int32_t cpu_id, server;
+    ICPState *ss;
+    bool byte0 = (width == 1 && (addr & 0x3) == 0);
+
+    cpu_id = (addr & (ICP_MM_SIZE - 1)) >> 12;
+    server = get_cpu_index_by_dt_id(cpu_id);
+    if (server < 0) {
+        fprintf(stderr, "XICS: Bad ICP server %d\n", server);
+        goto bad_access;
+    }
+    ss = &s->ss[server];
+
+    DEBUG_MM("icp_mm_write(addr=%016llx,serv=0x%x/%d,off=%d,w=%d,val=0x%08x)\n",
+             (unsigned long long)addr, cpu_id, server,
+             (int)(addr & 0xffc), width, (uint32_t)val);
+
+    switch(addr & 0xffc) {
+    case 4: /* xirr */
+        if (byte0) {
+            icp_set_cppr(s, server, val);
+        } else if (width == 4) {
+            icp_eoi(s, server, val);
+        } else {
+            goto bad_access;
+        }
+        break;
+    case 12:
+        if (byte0) {
+            icp_set_mfrr(s, server, val);
+        } else {
+            goto bad_access;
+        }
+        break;
+    case 16:
+        if (width == 4) {
+            ss->links[0] = val;
+        } else {
+            goto bad_access;
+        }
+        break;
+    case 20:
+        if (width == 4) {
+            ss->links[1] = val;
+        } else {
+            goto bad_access;
+        }
+        break;
+    case 24:
+        if (width == 4) {
+            ss->links[2] = val;
+        } else {
+            goto bad_access;
+        }
+        break;
+    default:
+ bad_access:
+        val = 0xffffffff;
+    }
+}
+
+static const MemoryRegionOps icp_mm_ops = {
+    .read = icp_mm_read,
+    .write = icp_mm_write,
+    .valid.min_access_size = 1,
+    .valid.max_access_size = 4,
+    .impl.min_access_size = 1,
+    .impl.max_access_size = 4,
+    .endianness = DEVICE_BIG_ENDIAN,
+};
+
+#define _FDT(exp) \
+    do { \
+        int ret = (exp);                                           \
+        if (ret < 0) {                                             \
+            fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \
+                    #exp, fdt_strerror(ret));                      \
+            exit(1);                                               \
+        }                                                          \
+    } while (0)
+
+void xics_create_native_icp_node(XICSState *s, void *fdt,
+                                 uint32_t base, uint32_t count)
+{
+    uint64_t addr;
+    char *name;
+    const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp";
+    uint32_t irange[2], i, rsize;
+    uint64_t *reg;
+
+    addr = ICP_MM_BASE | (base << 12);
+
+    irange[0] = cpu_to_be32(base);
+    irange[1] = cpu_to_be32(count);
+
+    rsize = sizeof(uint64_t) * 2 * count;
+    reg = g_malloc(rsize);
+    for (i = 0; i < count; i++) {
+        reg[i * 2] = cpu_to_be64(addr | ((base + i) * 0x1000));
+        reg[i * 2 + 1] = cpu_to_be64(0x1000);
+    }
+
+    name = g_strdup_printf("interrupt-controller@%"PRIX64, addr);
+
+    /* interrupt controller */
+    _FDT((fdt_begin_node(fdt, name)));
+    g_free(name);
+
+    _FDT((fdt_property(fdt, "compatible", compat, sizeof(compat))));
+    _FDT((fdt_property(fdt, "reg", reg, rsize)));
+    _FDT((fdt_property_string(fdt, "device_type",
+                              "PowerPC-External-Interrupt-Presentation")));
+    _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
+    _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges",
+                       irange, sizeof(irange))));
+    _FDT((fdt_property_cell(fdt, "#interrupt-cells", 1)));
+    _FDT((fdt_property_cell(fdt, "#address-cells", 0)));
+    _FDT((fdt_end_node(fdt)));
+}
+
+static void xics_native_realize(DeviceState *dev, Error **errp)
+{
+    XICSState *s = XICS_NATIVE(dev);
+    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+    Error *error = NULL;
+    int i;
+

hw/intc/xics_native.c new file +7 -0

+
+    for (i = 0; i < s->nr_servers; i++) {
+        object_property_set_bool(OBJECT(&s->ss[i]), true, "realized", &error);
+        if (error) {
+            error_propagate(errp, error);
+            return;
+        }

hw/intc/xics_native.c new file +16 -0

+}
+
+static const TypeInfo xics_native_info = {
+    .name          = TYPE_XICS_NATIVE,
+    .parent        = TYPE_XICS_COMMON,
+    .instance_size = sizeof(XICSState),
+    .class_size = sizeof(XICSStateClass),
+    .class_init    = xics_native_class_init,
+    .instance_init = xics_native_initfn,
+};
+
+static void xics_native_register_types(void)
+{
+    type_register_static(&xics_native_info);
+}
+type_init(xics_native_register_types)

include/hw/ppc/xics.h +14 -0

index 93a627b..f32f409 100644
@@ -38,6 +38,9 @@
 #define TYPE_XICS_SPAPR_KVM "xics-spapr-kvm"
 #define KVM_XICS(obj) OBJECT_CHECK(KVMXICSState, (obj), TYPE_XICS_SPAPR_KVM)
 
+#define TYPE_XICS_NATIVE "xics-native"
+#define XICS_NATIVE(obj) OBJECT_CHECK(XICSState, (obj), TYPE_XICS_NATIVE)
+
 #define XICS_COMMON_CLASS(klass) \
      OBJECT_CLASS_CHECK(XICSStateClass, (klass), TYPE_XICS_COMMON)
 #define XICS_SPAPR_CLASS(klass) \

@@ -46,6 +49,8 @@
      OBJECT_GET_CLASS(XICSStateClass, (obj), TYPE_XICS_COMMON)
 #define XICS_SPAPR_GET_CLASS(obj) \
      OBJECT_GET_CLASS(XICSStateClass, (obj), TYPE_XICS_SPAPR)
+#define XICS_NATIVE_CLASS(klass) \
+     OBJECT_CLASS_CHECK(XICSStateClass, (klass), TYPE_XICS_NATIVE)
 
 #define XICS_IPI        0x2
 #define XICS_BUID       0x1

@@ -80,6 +85,7 @@ struct XICSState {
     uint32_t nr_irqs;
     ICPState *ss;
     QLIST_HEAD(, ICSState) ics;
+    MemoryRegion icp_mmio;
 };
 
 #define TYPE_ICP "icp"

@@ -111,8 +117,13 @@ struct ICPState {
     uint8_t mfrr;
     qemu_irq output;
     bool cap_irq_xics_enabled;
+    uint32_t links[3];
 };
 
+/* This should be an XSCOM BAR ... the size is arbitrary as well */
+#define ICP_MM_BASE     0x0003FFFF80000000
+#define ICP_MM_SIZE     0x0000000010000000
+
 #define TYPE_ICS "ics"
 #define ICS(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS)
 

@@ -181,6 +192,9 @@ void xics_spapr_free(XICSState *icp, int irq, int num);
 
 void xics_cpu_setup(XICSState *icp, PowerPCCPU *cpu);
 
+void xics_create_native_icp_node(XICSState *s, void *fdt,
+                                 uint32_t base, uint32_t count);
+
 /* Internal XICS interfaces */
 int get_cpu_index_by_dt_id(int cpu_dt_id);
 

This provides MMIO based ICP access as found on POWER8

Signed-off-by Benjamin Herrenschmidt <[email protected]>

Useful to debug interrupt problems.

Signed-off-by Benjamin Herrenschmidt <[email protected]>

---
 hmp-commands-info.hx  |  2 ++
 hw/intc/xics.c        | 38 ++++++++++++++++++++++++++++++++++++++
 hw/ppc/ppc.c          | 14 ++++++++++++++
 include/hw/ppc/ppc.h  |  2 ++
 include/hw/ppc/xics.h |  2 ++
 monitor.c             |  3 +++
 6 files changed, 61 insertions(+)

hmp-commands-info.hx +2 -0

index 9b71351..2f1dc86 100644
@@ -203,6 +203,8 @@ ETEXI
         .mhandler.cmd = sun4m_hmp_info_pic,
 #elif defined(TARGET_LM32)
         .mhandler.cmd = lm32_hmp_info_pic,
+#elif defined(TARGET_PPC)
+        .mhandler.cmd = ppc_hmp_info_pic,
 #else
         .mhandler.cmd = hmp_info_pic,
 #endif

hw/intc/xics.c +38 -0

index 4b33e6d..d027a24 100644
@@ -31,6 +31,9 @@
 #include "hw/ppc/xics.h"
 #include "qemu/error-report.h"
 #include "qapi/visitor.h"
+#include "monitor/monitor.h"
+
+static XICSState *g_xics;
 
 int get_cpu_index_by_dt_id(int cpu_dt_id)
 {

@@ -170,6 +173,9 @@ static void xics_common_initfn(Object *obj)
     object_property_add(obj, "nr_servers", "int",
                         xics_prop_get_nr_servers, xics_prop_set_nr_servers,
                         NULL, NULL, NULL);
+
+    /* For exclusive use of monitor command */
+    g_xics = XICS_COMMON(obj);
 }
 
 static void xics_common_class_init(ObjectClass *oc, void *data)

@@ -614,6 +620,38 @@ static int ics_dispatch_post_load(void *opaque, int version_id)
     return 0;
 }
 
+void xics_hmp_info_pic(Monitor *mon, const QDict *qdict)
+{
+    ICSState *ics;
+    uint32_t i;
+
+    for (i = 0; i < g_xics->nr_servers; i++) {
+        ICPState *icp = &g_xics->ss[i];
+
+        if (!icp->output) {
+            continue;
+        }
+        monitor_printf(mon, "CPU %d XIRR=%08x (%p) PP=%02x MFRR=%02x\n",
+                       i, icp->xirr, icp->xirr_owner,
+                       icp->pending_priority, icp->mfrr);
+    }
+    QLIST_FOREACH(ics, &g_xics->ics, list) {
+        monitor_printf(mon, "ICS %4x..%4x %p\n",
+                       ics->offset, ics->offset + ics->nr_irqs - 1, ics);
+        for (i = 0; i < ics->nr_irqs; i++) {
+            ICSIRQState *irq = ics->irqs + i;
+
+            if (!(irq->flags & XICS_FLAGS_IRQ_MASK)) {
+                continue;
+            }
+            monitor_printf(mon, "  %4x %s %02x %02x\n",
+                           ics->offset + i,
+                           (irq->flags & XICS_FLAGS_IRQ_LSI) ? "LSI" : "MSI",
+                           irq->priority, irq->status);
+        }
+    }
+}
+
 static const VMStateDescription vmstate_ics_simple_irq = {
     .name = "ics/irq",
     .version_id = 2,

hw/ppc/ppc.c +14 -0

index 2c604ef..3b14f09 100644
@@ -24,6 +24,7 @@
 #include "hw/hw.h"
 #include "hw/ppc/ppc.h"
 #include "hw/ppc/ppc_e500.h"
+#include "hw/i386/pc.h"
 #include "qemu/timer.h"
 #include "sysemu/sysemu.h"
 #include "sysemu/cpus.h"

@@ -35,6 +36,10 @@
 #include "kvm_ppc.h"
 #include "trace.h"
 
+#if defined(TARGET_PPC64)
+#include "hw/ppc/xics.h"
+#endif
+
 //#define PPC_DEBUG_IRQ
 //#define PPC_DEBUG_TB
 

@@ -1337,3 +1342,12 @@ PowerPCCPU *ppc_get_vcpu_by_dt_id(int cpu_dt_id)
 
     return NULL;
 }
+
+void ppc_hmp_info_pic(Monitor *mon, const QDict *qdict)
+{
+    /* Call in turn every PIC around. OpenPIC doesn't have one yet */
+#ifdef TARGET_PPC64
+    xics_hmp_info_pic(mon, qdict);
+#endif
+    hmp_info_pic(mon, qdict);
+}

include/hw/ppc/ppc.h +2 -0

index 14efd0c..d5c648d 100644
@@ -1,6 +1,8 @@
 #ifndef HW_PPC_H
 #define HW_PPC_H 1
 
+void ppc_hmp_info_pic(Monitor *mon, const QDict *qdict);
+
 void ppc_set_irq(PowerPCCPU *cpu, int n_IRQ, int level);
 
 /* PowerPC hardware exceptions management helpers */

include/hw/ppc/xics.h +2 -0

index f32f409..1cf7037 100644
@@ -213,4 +213,6 @@ void xics_set_nr_servers(XICSState *icp, uint32_t nr_servers, Error **errp);
 ICSState *xics_find_source(XICSState *icp, int irq);
 void xics_add_ics(XICSState *xics, ICSState *ics);
 
+void xics_hmp_info_pic(Monitor *mon, const QDict *qdict);
+
 #endif /* __XICS_H__ */

monitor.c +3 -0

index 3295840..988477e 100644
@@ -76,6 +76,9 @@
 #include "qapi-event.h"
 #include "qmp-introspect.h"
 #include "sysemu/block-backend.h"
+#if defined(TARGET_PPC)
+#include "hw/ppc/ppc.h"
+#endif
 
 /* for hmp_info_irq/pic */
 #if defined(TARGET_SPARC)

Signed-off-by Benjamin Herrenschmidt <[email protected]>

---
 hw/ppc/pnv.c          | 69 +++++++++++++++++++++++++++++++++++++++++++++++++++
 include/hw/ppc/pnv.h  |  2 ++
 include/hw/ppc/xics.h |  2 ++
 3 files changed, 73 insertions(+)

hw/ppc/pnv.c +69 -0

index 2eac877..a7a9b0f 100644
@@ -41,6 +41,7 @@
 #include "hw/ppc/ppc.h"
 #include "hw/ppc/pnv.h"
 #include "hw/loader.h"
+#include "hw/ppc/xics.h"
 #include "hw/ppc/pnv_xscom.h"
 
 #include "exec/address-spaces.h"

@@ -81,6 +82,59 @@ struct sPowerNVMachineState {
     PnvSystem sys;
 };
 
+static XICSState *try_create_xics(const char *type, int nr_servers,
+                                  int nr_irqs, Error **errp)
+{
+    Error *err = NULL;
+    DeviceState *dev;
+
+    dev = qdev_create(NULL, type);
+    qdev_prop_set_uint32(dev, "nr_servers", nr_servers);
+    object_property_set_bool(OBJECT(dev), true, "realized", &err);
+    if (err) {
+        error_propagate(errp, err);
+        object_unparent(OBJECT(dev));
+        return NULL;
+    }
+
+    return XICS_COMMON(dev);
+}
+
+static XICSState *xics_system_init(int nr_servers, int nr_irqs)
+{
+    XICSState *xics = NULL;
+
+#if 0 /* Some fixing needed to handle native ICS in KVM mode */
+    if (kvm_enabled()) {
+        QemuOpts *machine_opts = qemu_get_machine_opts();
+        bool irqchip_allowed = qemu_opt_get_bool(machine_opts,
+                                                "kernel_irqchip", true);
+        bool irqchip_required = qemu_opt_get_bool(machine_opts,
+                                                  "kernel_irqchip", false);
+        if (irqchip_allowed) {
+                icp = try_create_xics(TYPE_KVM_XICS, nr_servers, nr_irqs,
+                                      &error_abort);
+        }
+
+        if (irqchip_required && !icp) {
+            perror("Failed to create in-kernel XICS\n");
+            abort();
+        }
+    }
+#endif
+
+    if (!xics) {
+        xics = try_create_xics(TYPE_XICS_NATIVE, nr_servers, nr_irqs,
+                               &error_abort);
+    }
+
+    if (!xics) {
+        perror("Failed to create XICS\n");
+        abort();
+    }
+    return xics;
+}
+
 static size_t create_page_sizes_prop(CPUPPCState *env, uint32_t *prop,
                                      size_t maxsize)
 {

@@ -366,6 +420,13 @@ static void *powernv_create_fdt(PnvSystem *sys, uint32_t initrd_base, uint32_t i
 
     _FDT((fdt_end_node(fdt)));
 
+    /* ICPs */
+    CPU_FOREACH(cs) {
+        PowerPCCPU *cpu = POWERPC_CPU(cs);
+        uint32_t base_server = ppc_get_vcpu_dt_id(cpu);
+        xics_create_native_icp_node(sys->xics, fdt, base_server, smt);
+    }
+
     /* Memory */
     _FDT((powernv_populate_memory(fdt)));
 

@@ -451,11 +512,17 @@ static void ppc_powernv_init(MachineState *machine)
     MemoryRegion *ram = g_new(MemoryRegion, 1);
     sPowerNVMachineState *pnv_machine = POWERNV_MACHINE(machine);
     PnvSystem *sys = &pnv_machine->sys;
+    XICSState *xics;
     long fw_size;
     char *filename;
     void *fdt;
     int i;
 
+    /* Set up Interrupt Controller before we create the VCPUs */
+    xics = xics_system_init(smp_cpus * kvmppc_smt_threads() / smp_threads,
+                            XICS_IRQS_POWERNV);
+    sys->xics = xics;
+
     /* init CPUs */
     if (cpu_model == NULL) {
         cpu_model = kvm_enabled() ? "host" : "POWER8";

@@ -475,6 +542,8 @@ static void ppc_powernv_init(MachineState *machine)
         /* MSR[IP] doesn't exist nowadays */
         env->msr_mask &= ~(1 << 6);
 
+        xics_cpu_setup(xics, cpu);
+
         qemu_register_reset(powernv_cpu_reset, cpu);
     }
 

include/hw/ppc/pnv.h +2 -0

index cb157eb..80617b4 100644
@@ -21,6 +21,7 @@
 
 #include "hw/hw.h"
 typedef struct XScomBus XScomBus;
+typedef struct XICSState XICSState;
 
 /* Should we turn that into a QOjb of some sort ? */
 typedef struct PnvChip {

@@ -29,6 +30,7 @@ typedef struct PnvChip {
 } PnvChip;
 
 typedef struct PnvSystem {
+    XICSState *xics;
     uint32_t  num_chips;
 #define PNV_MAX_CHIPS		1
     PnvChip   chips[PNV_MAX_CHIPS];

include/hw/ppc/xics.h +2 -0

index 1cf7037..85d2fb9 100644
@@ -183,6 +183,8 @@ struct ICSIRQState {
 };
 
 #define XICS_IRQS_SPAPR               1024
+#define XICS_IRQS_POWERNV             (1 << 19)
+
 
 qemu_irq xics_get_qirq(XICSState *icp, int irq);
 

This adds a model of the POWER8 LPC controller. It is then used by the PowerNV code to attach a UART and RTC, which, with the right version of OPAL firmware, will provide a working console.

This version of the LPC controller model doesn't yet implement support for the SerIRQ deserializer present in the Naples version of the chip though some preliminary work is there.

Quoted 8 lines · Benjamin Herrenschmidt

This adds a model of the POWER8 LPC controller. It is then used by the PowerNV code to attach a UART and RTC, which, with the right version of OPAL firmware, will provide a working console.

This version of the LPC controller model doesn't yet implement support for the SerIRQ deserializer present in the Naples version of the chip though some preliminary work is there.

Is this LPC controller one per a chip or per a machine?

In general it is quite nice when "-nodefaults" does not create neither PHB nor LPC so the user can add them manually with parameters different than defaults.

Quoted 11 lines · Alexey Kardashevskiy

Quoted 8 lines · Benjamin Herrenschmidt

This adds a model of the POWER8 LPC controller. It is then used by the PowerNV code to attach a UART and RTC, which, with the right version of OPAL firmware, will provide a working console.

This version of the LPC controller model doesn't yet implement support for the SerIRQ deserializer present in the Naples version of the chip though some preliminary work is there.

Is this LPC controller one per a chip or per a machine?

Per chip but we usually only wire one up per machine.

Quoted 3 lines

In general it is quite nice when "-nodefaults" does not create neither PHB nor LPC so the user can add them manually with parameters different than defaults.

In this case though, PHB and LPC bridges are all part of the P8 chip, and I'm trying to represent that topology as best as possible.

I think "-nodefaults" for Pnv should only be about the devices we attach to the LPC/PHB not the busses themselves.

Quoted 22 lines · Benjamin Herrenschmidt

Quoted 11 lines · Alexey Kardashevskiy

Quoted 8 lines · Benjamin Herrenschmidt

This adds a model of the POWER8 LPC controller. It is then used by the PowerNV code to attach a UART and RTC, which, with the right version of OPAL firmware, will provide a working console.

This version of the LPC controller model doesn't yet implement support for the SerIRQ deserializer present in the Naples version of the chip though some preliminary work is there.

Is this LPC controller one per a chip or per a machine?

Per chip but we usually only wire one up per machine.

Quoted 3 lines

In general it is quite nice when "-nodefaults" does not create neither PHB nor LPC so the user can add them manually with parameters different than defaults.

In this case though, PHB and LPC bridges are all part of the P8 chip, and I'm trying to represent that topology as best as possible.

Quoted 2 lines

I think "-nodefaults" for Pnv should only be about the devices we attach to the LPC/PHB not the busses themselves.

Exactly what is and isn't covered by -nodefaults is a bit of a mess - part of the topic of my talk at KVM Forum.

But on the whole I agree with you, since the LPC is part of the P8 chip, I think it makes sense to include it even with -nodefaults.

Quoted 2 lines

But on the whole I agree with you, since the LPC is part of the P8 chip, I think it makes sense to include it even with -nodefaults.

POWER8 chips all have 8 threads per core but we do not always assume -smt ...,threads=8, how are LPC or PHB different?

PHB is more interesting - how is the user supposed to add more?

And there always will be the default one
which properties are set in a separate way (via -global, not -device). I found it sometime really annoying to debug the existing pseries which always adds a default PHB (I know, this was to make libvirt happy but this is not the case here).

Out of curiosity - if we have 2 chips, will the system work if the second chip does not get any LPC or PHB attached?

Quoted 5 lines · Alexey Kardashevskiy

Quoted 2 lines

But on the whole I agree with you, since the LPC is part of the P8 chip, I think it makes sense to include it even with -nodefaults.

POWER8 chips all have 8 threads per core but we do not always assume -smt ...,threads=8, how are LPC or PHB different?

First, for pseries which is paravirtualized it's a different can of worms completely. For powernv, we *should* represent all 8 threads, we just can't yet due to TCG limitations.

Quoted 1 line

PHB is more interesting - how is the user supposed to add more?

That's an open question. Since we model a real P8 chip we can only model the PHBs as they exist on it, which is up to 3 per chip at very specific XSCOM addresses. We could try to model some non-existing P8 chip with more but bad things will happen when the FW try to assign interrupt numbers for example.

We simulate a machine that has been primed by HostBoot before OPAL starts. So we rely on what the device-tree tells us of what PHB were enabled but appart from that, we have to stick to the limitations.

Quoted 6 lines

And there always will be the default one
which properties are set in a separate way (via -global, not -device). I found it sometime really annoying to debug the existing pseries which always adds a default PHB (I know, this was to make libvirt happy but this is not the case here).

Quoted 2 lines

Out of curiosity - if we have 2 chips, will the system work if the second chip does not get any LPC or PHB attached?

This is something I need to look into, there's a lot of work needed to properly model "chips" that I haven't done yet, but what is there is sufficient for a lot of usages already.

Quoted 7 lines · Benjamin Herrenschmidt

Quoted 5 lines · Alexey Kardashevskiy

Quoted 2 lines

But on the whole I agree with you, since the LPC is part of the P8 chip, I think it makes sense to include it even with -nodefaults.

POWER8 chips all have 8 threads per core but we do not always assume -smt ...,threads=8, how are LPC or PHB different?

Quoted 3 lines

First, for pseries which is paravirtualized it's a different can of worms completely. For powernv, we *should* represent all 8 threads, we just can't yet due to TCG limitations.

Out of curiosity - for pseries we should not? I know it works with various numbers of threads but is not that because we also control guest linux kernel and, for example, the Other OS (AIX) might be upset on non-multiply-of-2 number of threads?

Quoted 18 lines

Quoted 1 line

PHB is more interesting - how is the user supposed to add more?

That's an open question. Since we model a real P8 chip we can only model the PHBs as they exist on it, which is up to 3 per chip at very specific XSCOM addresses. We could try to model some non-existing P8 chip with more but bad things will happen when the FW try to assign interrupt numbers for example.

We simulate a machine that has been primed by HostBoot before OPAL starts. So we rely on what the device-tree tells us of what PHB were enabled but appart from that, we have to stick to the limitations.

Quoted 6 lines

And there always will be the default one
which properties are set in a separate way (via -global, not -device). I found it sometime really annoying to debug the existing pseries which always adds a default PHB (I know, this was to make libvirt happy but this is not the case here).

Quoted 6 lines

Quoted 2 lines

Out of curiosity - if we have 2 chips, will the system work if the second chip does not get any LPC or PHB attached?

This is something I need to look into, there's a lot of work needed to properly model "chips" that I haven't done yet, but what is there is sufficient for a lot of usages already.

For now, if possible, I'd suggest implementing -nodefaults with no defaults whatsoever and create a config somewhere in the qemu tree to pass it via -readconfig to get reasonably configured machine so people will know what is expected to work but there will still be possibility for experiments (do not we secretly hope that other vendors will start designing/manufacturing their ppc64 chips?). It could be a config file per an actual POWER8 chip (we have two already).

There are several different cases here and I'm not sure which you're thinking about.

1) Guest has different number of threads-per-core than the host

This one is just fine - PAPR defines how the guest should get the number of threads from the device tree, and qemu sets that correctly.

2) Guest threads-per-core not a power of two

The PAPR thread mechanism allows this to be communicated to the guest, and I don't know if PAPR explicitly permits or prohibitis this situation.  Guests could get confused by it, although that's arguably a guest bug.

Quoted 7 lines

For now, if possible, I'd suggest implementing -nodefaults with no defaults whatsoever and create a config somewhere in the qemu tree to pass it via -readconfig to get reasonably configured machine so people will know what is expected to work but there will still be possibility for experiments (do not we secretly hope that other vendors will start designing/manufacturing their ppc64 chips?). It could be a config file per an actual POWER8 chip (we have two already).

I can see some benefit to that approach, but it does stray away from current qemu practice (in general, not just compared to spapr). Hmm.. not sure.

What I do think would be a good idea is to represent a POWER8 "chip" as a instantiable qdev device, which will create the scoms and PHBs under itself as per the hardware.  We can add device properties as needed to make that construction more flexible.

We probably don't want to link the number of CPUs to the chip qdevs, partly because that doesn't really fit the qemu model, but also because we'll probably want some extra flexibility.  e.g. making a UP system for experimentation, even though a single chip would have multiple cores (IIUC) - SMP TCG is super slow, so we probably want that.

Quoted 4 lines · Benjamin Herrenschmidt

Quoted 3 lines · Alexey Kardashevskiy

Quoted 2 lines

But on the whole I agree with you, since the LPC is part of the P8 chip, I think it makes sense to include it even with -nodefaults.

Quoted 6 lines

Quoted 2 lines

POWER8 chips all have 8 threads per core but we do not always assume -smt ...,threads=8, how are LPC or PHB different?

First, for pseries which is paravirtualized it's a different can of worms completely. For powernv, we *should* represent all 8 threads, we just can't yet due to TCG limitations.

Out of curiosity - for pseries we should not?

I know it works with various
numbers of threads but is not that because we also control guest linux kernel and, for example, the Other OS (AIX) might be upset on non-multiply-of-2 number of threads?

Quoted 8 lines

Quoted 2 lines

PHB is more interesting - how is the user supposed to add more?

That's an open question. Since we model a real P8 chip we can only model the PHBs as they exist on it, which is up to 3 per chip at very specific XSCOM addresses. We could try to model some non-existing P8 chip with more but bad things will happen when the FW try to assign interrupt numbers for example.

 >

Quoted 3 lines

We simulate a machine that has been primed by HostBoot before OPAL starts. So we rely on what the device-tree tells us of what PHB were enabled but appart from that, we have to stick to the limitations.

 >

Quoted 6 lines

Quoted 6 lines

And there always will be the default one
which properties are set in a separate way (via -global, not -device). I found it sometime really annoying to debug the existing pseries which always adds a default PHB (I know, this was to make libvirt happy but this is not the case here).

Quoted 6 lines

Quoted 2 lines

Out of curiosity - if we have 2 chips, will the system work if the second chip does not get any LPC or PHB attached?

This is something I need to look into, there's a lot of work needed to properly model "chips" that I haven't done yet, but what is there is sufficient for a lot of usages already.

For now, if possible, I'd suggest implementing -nodefaults with no defaults whatsoever and create a config somewhere in the qemu tree to pass it via -readconfig to get reasonably configured machine so people will know what is expected to work but there will still be possibility for experiments (do not we secretly hope that other vendors will start designing/manufacturing their ppc64 chips?). It could be a config file per an actual POWER8 chip (we have two already).

hw/pci-bridge/pci_bridge_dev.c static int pci_bridge_dev_initfn(PCIDevice *dev) · line 65

Quoted 6 lines · Benjamin Herrenschmidt

     if (bridge_dev->flags & (1 << PCI_BRIDGE_DEV_F_SHPC_REQ)) {

hw/pci-bridge/pci_bridge_dev.c +2 -0

+        /* SHCP gets upset if we try to use slot 0 */
+        br->sec_bus.devfn_min = PCI_FUNC_MAX;
         dev->config[PCI_INTERRUPT_PIN] = 0x1;
         memory_region_init(&bridge_dev->bar, OBJECT(dev), "shpc-bar",
                            shpc_bar_size(dev));

This needs backwards compatibility gunk unfortunately. However we should fix it in 2.5 because it's a bug. I'll send a patch.

Quoted 10 lines · Paolo Bonzini

hw/pci-bridge/pci_bridge_dev.c static int pci_bridge_dev_initfn(PCIDevice *dev) · line 65

Quoted 6 lines · Benjamin Herrenschmidt

     if (bridge_dev->flags & (1 << PCI_BRIDGE_DEV_F_SHPC_REQ)) {

hw/pci-bridge/pci_bridge_dev.c +2 -0

+        /* SHCP gets upset if we try to use slot 0 */
+        br->sec_bus.devfn_min = PCI_FUNC_MAX;
         dev->config[PCI_INTERRUPT_PIN] = 0x1;
         memory_region_init(&bridge_dev->bar, OBJECT(dev), "shpc-bar",
                            shpc_bar_size(dev));

Quoted 2 lines

This needs backwards compatibility gunk unfortunately. However we should fix it in 2.5 because it's a bug. I'll send a patch.

Actually it turns out that the forbidden configuration is blocked elsewhere:

$ x86_64-softmmu/qemu-system-x86_64 \
	-device pci-bridge,id=foo,chassis_nr=1 \
	-device virtio-scsi-pci,bus=foo
qemu-system-x86_64: -device virtio-scsi-pci,bus=foo: Unsupported PCI
slot 0 for standard hotplug controller. Valid slots are between 1 and 31.

so this patch is just allowing the above command line to work. There's no effect with or without the patch if addr=0, so the patch is good for 2.5 IMO.

Michael, can you queue it?

Paolo

This depends on the devfn_min thing, right? I'm yet to review it, generally I'd prefer to avoid changing device allocation rules since that makes it so easy to break compatibility.

Assuming addresses are all explicitly stated, is there even a problem?

Quoted 5 lines · Michael S. Tsirkin

This depends on the devfn_min thing, right? I'm yet to review it, generally I'd prefer to avoid changing device allocation rules since that makes it so easy to break compatibility.

Quoted 2 lines

Assuming addresses are all explicitly stated, is there even a problem?

It makes it a bit easier to use pci-bridge; it is a bug, albeit one that only affects direct usage through the command line of PCI bridges.

Paolo

This allows a bus class to tell whether a given bus has room for any new device. max_dev isn't sufficient as the rules can depend on some arguments or can differ between instances of a bus. This will be used by PCI in subsequent patches

Signed-off-by Benjamin Herrenschmidt <[email protected]>

---
 include/hw/qdev-core.h |  1 +
 qdev-monitor.c         | 13 ++++++++-----
 2 files changed, 9 insertions(+), 5 deletions(-)

include/hw/qdev-core.h +1 -0

index 8057aed..6f3dd8d 100644
@@ -202,6 +202,7 @@ struct BusClass {
      */
     char *(*get_fw_dev_path)(DeviceState *dev);
     void (*reset)(BusState *bus);
+    bool (*can_add_device)(BusState *bus, QemuOpts *opts);
     BusRealize realize;
     BusUnrealize unrealize;
 

qdev-monitor.c +5 -2

index a35098f..4023357 100644
@@ -384,7 +384,7 @@ static inline bool qbus_is_full(BusState *bus)
  * Return the bus if found, else %NULL.
  */
 static BusState *qbus_find_recursive(BusState *bus, const char *name,
-                                     const char *bus_typename)
+                                     const char *bus_typename, QemuOpts *opts)
 {
     BusChild *kid;
     BusState *pick, *child, *ret;

@@ -398,7 +398,10 @@ static BusState *qbus_find_recursive(BusState *bus, const char *name,
     }
 
     if (match && !qbus_is_full(bus)) {
-        return bus;             /* root matches and isn't full */
+        BusClass *bc = BUS_GET_CLASS(bus);
+        if (!bc->can_add_device || bc->can_add_device(bus, opts)) {
+            return bus;             /* root matches and isn't full */
+	}
     }
 
     pick = match ? bus : NULL;

qdev-monitor.c +2 -2

             if (ret && !qbus_is_full(ret)) {
                 return ret;     /* a descendant matches and isn't full */
             }

@@ -436,7 +439,7 @@ static BusState *qbus_find(const char *path, Error **errp)
             assert(!path[0]);
             elem[0] = len = 0;
         }
-        bus = qbus_find_recursive(sysbus_get_default(), elem, NULL);
+        bus = qbus_find_recursive(sysbus_get_default(), elem, NULL, NULL);
         if (!bus) {
             error_setg(errp, "Bus '%s' not found", elem);
             return NULL;

@@ -542,7 +545,7 @@ DeviceState *qdev_device_add(QemuOpts *opts, Error **errp)
             return NULL;
         }
     } else if (dc->bus_type != NULL) {
-        bus = qbus_find_recursive(sysbus_get_default(), NULL, dc->bus_type);
+	    bus = qbus_find_recursive(sysbus_get_default(), NULL, dc->bus_type, opts);
         if (!bus || qbus_is_full(bus)) {
             error_setg(errp, "No '%s' bus found for device '%s'",
                        dc->bus_type, driver);

Tabs for indentation.  There are other occurrences in the patch.

Apart from this,

Reviewed-by Paolo Bonzini <[email protected]>

Acked-by Paolo Bonzini <[email protected]>

Quoted 29 lines

             if (ret && !qbus_is_full(ret)) {
                 return ret;     /* a descendant matches and isn't full */
             }

(quoted diff) +1 -1

@@ -436,7 +439,7 @@ static BusState *qbus_find(const char *path,
 Error **errp)
              assert(!path[0]);
              elem[0] = len = 0;
          }
-        bus = qbus_find_recursive(sysbus_get_default(), elem,
 NULL);
+        bus = qbus_find_recursive(sysbus_get_default(), elem,
 NULL, NULL);

         if (!bus) {
             error_setg(errp, "Bus '%s' not found", elem); return NULL;

(quoted diff) +1 -1

@@ -542,7 +545,7 @@ DeviceState *qdev_device_add(QemuOpts *opts,
 Error **errp)
              return NULL;
          }
      } else if (dc->bus_type != NULL) {
-        bus = qbus_find_recursive(sysbus_get_default(), NULL, dc-
 >bus_type);
+	    bus = qbus_find_recursive(sysbus_get_default(), NULL,
 dc->bus_type, opts);

         if (!bus || qbus_is_full(bus)) { error_setg(errp, "No '%s' bus found for device '%s'", dc->bus_type, driver);