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ppc: Add "native" POWER8 platform

Benjamin Herrenschmidt qemu-devel 1 version In review

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b4 am [email protected]

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  1. v1 Latest77 patches 120 repliesIn review

Patches in v1 No applies recorded yet

#Subject and filesSizeRepliesApplied
1/77ppc: Remove MMU_MODEn_SUFFIX definitionstarget-ppc/cpu.h+0 -30 replies
2/77ppc: Use split I/D mmu modes to avoid flushes on interruptstarget-ppc/cpu.h target-ppc/excp_helper.c target-ppc/helper_regs.h +2 more+62 -255 replies
3/77ppc: Do some batching of TCG tlb flusheshw/ppc/spapr_hcall.c target-ppc/cpu.h target-ppc/excp_helper.c +5 more+81 -163 replies
4/77target-ppc: Use sensible POWER8/POWER8E versionstarget-ppc/cpu-models.c target-ppc/cpu-models.h+8 -85 replies
5/77ppc: Update SPR definitionstarget-ppc/cpu.h+47 -71 reply
6/77ppc: Add macros to register hypervisor mode SPRstarget-ppc/translate.c target-ppc/translate_init.c+47 -141 reply
7/77ppc: Add a bunch of hypervisor SPRs to Book3starget-ppc/translate_init.c+137 -32 replies
8/77ppc: Add number of threads per core to the processor definitiontarget-ppc/cpu-qom.h target-ppc/translate_init.c+8 -12 replies
9/77ppc: Fix do_rfi() for rfi emulationtarget-ppc/excp_helper.c+2 -23 replies
10/77ppc: Fix hreg_store_msr() so that non-HV mode cannot alter MSR:HVtarget-ppc/excp_helper.c target-ppc/helper_regs.h+8 -41 reply
11/77ppc: Create cpu_ppc_set_papr() helperhw/ppc/spapr.c target-ppc/cpu.h target-ppc/translate_init.c+40 -101 reply
12/77ppc: Better figure out if processor has HV modetarget-ppc/cpu.h target-ppc/translate.c target-ppc/translate_init.c+23 -61 reply
13/77ppc: tlbie, tlbia and tlbisync are HV onlytarget-ppc/translate.c+3 -33 replies
14/77ppc: Change 'invalid' bit mask of tlbiel and tlbietarget-ppc/translate.c+4 -21 reply
15/77ppc: Fix sign extension issue in mtmsr(d) emulationtarget-ppc/translate.c+2 -22 replies
16/77ppc: Get out of emulation on SMT "OR" opstarget-ppc/translate.c+17 -21 reply
17/77ppc: Add PPC_64H instruction flag to POWER7 and POWER8target-ppc/translate_init.c+2 -21 reply
18/77ppc: Rework POWER7 & POWER8 exception modeltarget-ppc/cpu.h target-ppc/excp_helper.c target-ppc/translate_init.c+92 -872 replies
19/77ppc: Fix POWER7 and POWER8 exception definitionstarget-ppc/cpu.h target-ppc/translate_init.c+31 -71 reply
20/77ppc: Fix generation if ISI/DSI vs. HV modetarget-ppc/mmu-hash64.c+47 -191 reply
21/77ppc: Rework generation of priv and inval interruptslinux-user/main.c target-ppc/excp_helper.c target-ppc/translate.c+302 -3965 replies
22/77ppc: Add real mode CI load/store instructions for P7 and P8target-ppc/cpu.h target-ppc/translate.c target-ppc/translate_init.c+51 -152 replies
23/77ppc: Turn a bunch of booleans from int to booltarget-ppc/translate.c+19 -201 reply
24/77ppc: Move exception generation code out of linetarget-ppc/translate.c+6 -32 replies
25/77ppc: Add P7/P8 Power Management instructionstarget-ppc/cpu.h target-ppc/excp_helper.c target-ppc/helper.h +2 more+241 -31 reply
26/77ppc/pnv: Add skeletton PowerNV platformdefault-configs/ppc64-softmmu.mak hw/ppc/Makefile.objs hw/ppc/pnv.c +1 more+639 -04 replies
27/77ppc/pnv: Add XSCOM infrastructurehw/ppc/Makefile.objs hw/ppc/pnv.c hw/ppc/pnv_xscom.c +2 more+502 -13 replies
28/77ppc/xics: Rename existing XICS classe to XICS_SPAPRhw/intc/xics.c hw/intc/xics_kvm.c hw/ppc/spapr.c +4 more+38 -371 reply
29/77ppc/xics: Move SPAPR specific code to a separate filedefault-configs/ppc64-softmmu.mak hw/intc/Makefile.objs hw/intc/xics.c +2 more+437 -3791 reply
30/77ppc/xics: Implement H_IPOLL using an accessorhw/intc/xics.c hw/intc/xics_spapr.c include/hw/ppc/xics.h+13 -30 replies
31/77ppc/xics: Remove unused xics_set_irq_type()hw/intc/xics.c include/hw/ppc/xics.h+0 -121 reply
32/77ppc/xics: Replace "icp" with "xics" in most placeshw/intc/xics.c hw/intc/xics_kvm.c hw/intc/xics_spapr.c +8 more+145 -1451 reply
33/77ppc/xics: Make the ICSState a listhw/intc/xics.c hw/intc/xics_kvm.c hw/intc/xics_spapr.c +4 more+118 -891 reply
34/77ppc/xics: An ICS with offset 0 is assumed to be uninitializedinclude/hw/ppc/xics.h+1 -11 reply
35/77ppc/xics: Move xics_set_nr_irqs() to xics_spapr.c and xics_kvm.chw/intc/xics.c hw/intc/xics_kvm.c hw/intc/xics_spapr.c +1 more+24 -151 reply
36/77ppc/xics: Use a helper to add a new ICShw/intc/xics.c hw/intc/xics_spapr.c include/hw/ppc/xics.h+8 -21 reply
37/77ppc/xics: Split ICS into base class and "simple" implementationhw/intc/xics.c hw/intc/xics_kvm.c hw/intc/xics_spapr.c +1 more+108 -631 reply
38/77ppc/xics: Add "native" XICS subclassdefault-configs/ppc64-softmmu.mak hw/intc/Makefile.objs hw/intc/xics_native.c +1 more+311 -12 replies
39/77ppc/xics: Add xics to the monitor "info pic" commandhmp-commands-info.hx hw/intc/xics.c hw/ppc/ppc.c +3 more+61 -01 reply
40/77ppc/pnv: Wire up XICS native with PowerNV platformhw/ppc/pnv.c include/hw/ppc/pnv.h include/hw/ppc/xics.h+73 -01 reply
41/77ppc/pnv: Add LPC controller and hook it up with a UART and RTChw/ppc/Makefile.objs hw/ppc/pnv.c hw/ppc/pnv_lpc.c +1 more+578 -59 replies
42/77ppc/pnv: Add cut down PSI bridge model and hookup external interrupthw/ppc/Makefile.objs hw/ppc/pnv.c hw/ppc/pnv_psi.c +1 more+632 -80 replies
43/77ppc/pnv: Add OCC model stub with interrupt supporthw/ppc/Makefile.objs hw/ppc/pnv.c hw/ppc/pnv_occ.c +1 more+132 -10 replies
44/77pci-bridge: Set a supported devfn_min for bridgehw/pci-bridge/pci_bridge_dev.c+3 -05 replies
45/77qdev: Add a hook for a bus to device if it can add devicesinclude/hw/qdev-core.h qdev-monitor.c+9 -52 replies
46/77pci: Use the new pci_can_add_device() to enforce devfn_min/maxhw/pci/pci.c include/hw/pci/pci_bus.h+23 -01 reply
47/77pci: Don't call pci_irq_handler() for a negative intxhw/pci/pci.c+3 -10 replies
48/77ppc/pnv: Add model for Power8 PHB3 PCIe Host bridgehw/intc/xics.c hw/pci-host/Makefile.objs hw/pci-host/pnv_phb3.c +8 more+2543 -42 replies
49/77ppc/pnv: Create a default PCI layouthw/ppc/pnv.c+98 -10 replies
50/77ppc: Update LPCR definitionstarget-ppc/cpu.h+13 -30 replies
51/77ppc: Use a helper to filter writes to LPCRtarget-ppc/helper.h target-ppc/mmu-hash64.c target-ppc/translate_init.c+96 -190 replies
52/77ppc: Cosmetic, align some commentstarget-ppc/mmu-hash32.c target-ppc/mmu_helper.c+6 -60 replies
53/77ppc: Add proper real mode translation supporthw/ppc/spapr.c target-ppc/mmu-hash64.c target-ppc/mmu-hash64.h +1 more+144 -200 replies
54/77ppc: Fix 64K pages support in full emulationhw/ppc/spapr_hcall.c target-ppc/cpu.h target-ppc/mmu-hash64.c +1 more+69 -240 replies
55/77ppc/pnv+spapr: Add "ibm, pa-features" property to the device-treehw/ppc/pnv.c target-ppc/translate_init.c+9 -00 replies
56/77ppc: Fix conditions for delivering external interrupts to a guesttarget-ppc/excp_helper.c+8 -110 replies
57/77ppc: Enforce setting MSR:EE, IR and DR when MSR:PR is settarget-ppc/helper_regs.h+4 -00 replies
58/77ppc: Initial HDEC supporthw/ppc/ppc.c target-ppc/excp_helper.c target-ppc/helper.h +2 more+66 -150 replies
59/77ppc: Add placeholder SPRs for DPDES and DHDES on P8target-ppc/cpu.h target-ppc/translate_init.c+19 -00 replies
60/77ppc: LPCR is a HV resourcetarget-ppc/translate_init.c+5 -40 replies
61/77ppc: SPURR & PURR are HV writeable and privilegedtarget-ppc/translate_init.c+16 -80 replies
62/77ppc: Add dummy SPR_IC for POWER8target-ppc/cpu.h target-ppc/translate_init.c+13 -00 replies
63/77ppc: Initialize AMOR in PAPR modetarget-ppc/translate_init.c+4 -00 replies
64/77ppc: Fix writing to AMR/UAMORtarget-ppc/translate_init.c+60 -160 replies
65/77ppc: Add POWER8 IAMR registertarget-ppc/cpu.h target-ppc/translate_init.c+40 -10 replies
66/77ppc: Add a few more P8 PMU SPRstarget-ppc/cpu.h target-ppc/translate_init.c+35 -00 replies
67/77ppc: Add dummy write to VTBtarget-ppc/translate_init.c+11 -40 replies
68/77ppc: Add dummy POWER8 MPPR registertarget-ppc/cpu.h target-ppc/translate_init.c+14 -00 replies
69/77ppc: Add dummy POWER8 PSPB SPRtarget-ppc/cpu.h target-ppc/translate_init.c+12 -00 replies
70/77ppc: Add dummy CIABR SPRtarget-ppc/cpu.h target-ppc/translate_init.c+6 -00 replies
71/77ppc: Add dummy ACOP SPRtarget-ppc/cpu.h target-ppc/translate_init.c+5 -01 reply
72/77ppc: A couple more dummy POWER8 Book4 regstarget-ppc/cpu.h target-ppc/translate_init.c+14 -412 replies
73/77ppc: Add KVM numbers to some P8 SPRstarget-ppc/translate_init.c+11 -110 replies
74/77ppc: Print HSRR0/HSRR1 in "info registers"target-ppc/translate.c+7 -00 replies
75/77ppc: Add dummy logmpp instructiontarget-ppc/translate.c+18 -00 replies
76/77ppc: Add slbfee. instructiontarget-ppc/helper.h target-ppc/mmu-hash64.c target-ppc/translate.c+50 -00 replies
77/77ppc: Fix CFAR updatestarget-ppc/translate.c+4 -40 replies

Reviews trailers per patch

16 of 77 patches have a Reviewed-by or Acked-by.

PatchStewart SmithDavid GibsonPaolo Bonzini
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Trailers given in replies are filled; those carried in the patches from earlier versions are outlined with dashes. Scroll the table sideways for all 3 reviewers.

Read the v1 thread

Cover letter [Qemu-devel] [PATCH 00/77] ppc: Add "native" POWER8 platform

This requires an OPAL firmware file which isn't included yet, will emulate enough to boot existing distros and run KVM inside TCG

Read the cover letter in its thread