clk: tegra30: init PLL_C to sane rate
Subsystems (3)
PATCH 1/2 clk: tegra30: init PLL_C to sane rate
If the bootloader does not touch PLL_C it will stay in its reset state, failing to lock when enabled. This leads to consumers of this clock to fail probing. Fix this by always programming the PLL with a sane rate, which allows it to lock, at startup.
--- drivers/clk/tegra/clk-tegra30.c | 1 + 1 file changed, 1 insertion(+)
drivers/clk/tegra/clk-tegra30.c +1 -0
@@ -1372,6 +1372,7 @@ static struct tegra_clk_init_table init_table[] __initdata = { { TEGRA30_CLK_SBC4, TEGRA30_CLK_PLL_P, 100000000, 0 }, { TEGRA30_CLK_SBC5, TEGRA30_CLK_PLL_P, 100000000, 0 }, { TEGRA30_CLK_SBC6, TEGRA30_CLK_PLL_P, 100000000, 0 }, + { TEGRA30_CLK_PLL_C, TEGRA30_CLK_CLK_MAX, 600000000, 0 }, { TEGRA30_CLK_HOST1X, TEGRA30_CLK_PLL_C, 150000000, 0 }, { TEGRA30_CLK_DISP1, TEGRA30_CLK_PLL_P, 600000000, 0 }, { TEGRA30_CLK_DISP2, TEGRA30_CLK_PLL_P, 600000000, 0 },
Signature · 1 line
2.5.0
PATCH 2/2 clk: tegra30: fix PLL_U post divider and init rate
The post divider value in the frequency table is wrong as it would lead to the PLL producing a output rate of 960MHz instead of the desired 480MHz. This wasn't a problem as nothing used the table to actually init the PLL rate, but the bootloader configuration was used unaltered.
If the bootloader does not set up the PLL it will fail to come when used under Linux. To fix this don't rely on the bootloader, but set the correct rate in the clock driver.
--- drivers/clk/tegra/clk-tegra30.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-)
drivers/clk/tegra/clk-tegra30.c +6 -5
@@ -339,11 +339,11 @@ static const struct pdiv_map pllu_p[] = { };static struct tegra_clk_pll_freq_table pll_u_freq_table[] = { - {12000000 ,480000000 ,960 ,12 ,1 ,12 }, - {13000000 ,480000000 ,960 ,13 ,1 ,12 }, - {16800000 ,480000000 ,400 ,7 ,1 ,5 }, - {19200000 ,480000000 ,200 ,4 ,1 ,3 }, - {26000000 ,480000000 ,960 ,26 ,1 ,12 }, + {12000000 ,480000000 ,960 ,12 ,2 ,12 }, + {13000000 ,480000000 ,960 ,13 ,2 ,12 }, + {16800000 ,480000000 ,400 ,7 ,2 ,5 }, + {19200000 ,480000000 ,200 ,4 ,2 ,3 }, + {26000000 ,480000000 ,960 ,26 ,2 ,12 }, {0 ,0 ,0 ,0 ,0 ,0 }, };
@@ -1380,6 +1380,7 @@ static struct tegra_clk_init_table init_table[] __initdata = { { TEGRA30_CLK_GR2D, TEGRA30_CLK_PLL_C, 300000000, 0 }, { TEGRA30_CLK_GR3D, TEGRA30_CLK_PLL_C, 300000000, 0 }, { TEGRA30_CLK_GR3D2, TEGRA30_CLK_PLL_C, 300000000, 0 }, + { TEGRA30_CLK_PLL_U, TEGRA30_CLK_CLK_MAX, 480000000, 0 },/* must be the last entry */ { TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0 }, };
Signature · 1 line
2.5.0
Thierry Reding
AppliedRe: [PATCH 2/2] clk: tegra30: fix PLL_U post divider and init rate
Quoted 6 lines · Lucas Stach
The post divider value in the frequency table is wrong as it would lead to the PLL producing a output rate of 960MHz instead of the desired 480MHz. This wasn't a problem as nothing used the table to actually init the PLL rate, but the bootloader configuration was used unaltered.
Quoted 8 lines
If the bootloader does not set up the PLL it will fail to come when used under Linux. To fix this don't rely on the bootloader, but set the correct rate in the clock driver.
Signed-off-by Lucas Stach <[email protected]>--- drivers/clk/tegra/clk-tegra30.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-)
Applied, thanks.
Thierry
Am Montag, den 29.02.2016, 21:46 +0100 schrieb Lucas Stach:
Quoted 5 lines
If the bootloader does not touch
PLL_Cit will stay in its reset state, failing to lock when enabled. This leads to consumers of this clock to fail probing. Fix this by always programming the PLL with a sane rate, which allows it to lock, at startup.
Those 2 patches haven't been applied, as far as I can see. Any comments on them?
Quoted 19 lines
Signed-off-by Lucas Stach <[email protected]>---
drivers/clk/tegra/clk-tegra30.c | 1 +1 file changed, 1 insertion(+)drivers/clk/tegra/clk- renamed from drivers/clk/tegra/clk-tegra30.c +0
-0
tegra30.c
index 0478565..236e2db 100644drivers/clk/tegra/clk-tegra30.c +1
-0@@ -1372,6 +1372,7 @@ static struct tegra_clk_init_table init_table[] __initdata = { { TEGRA30_CLK_SBC4, TEGRA30_CLK_PLL_P, 100000000, 0 }, { TEGRA30_CLK_SBC5, TEGRA30_CLK_PLL_P, 100000000, 0 }, { TEGRA30_CLK_SBC6, TEGRA30_CLK_PLL_P, 100000000, 0 }, + { TEGRA30_CLK_PLL_C, TEGRA30_CLK_CLK_MAX, 600000000, 0 }, { TEGRA30_CLK_HOST1X, TEGRA30_CLK_PLL_C, 150000000, 0 }, { TEGRA30_CLK_DISP1, TEGRA30_CLK_PLL_P, 600000000, 0 },{
TEGRA30_CLK_DISP2,TEGRA30_CLK_PLL_P, 600000000, 0 },
Thierry Reding
AppliedQuoted 9 lines · Lucas Stach
If the bootloader does not touch
PLL_Cit will stay in its reset state, failing to lock when enabled. This leads to consumers of this clock to fail probing. Fix this by always programming the PLL with a sane rate, which allows it to lock, at startup.Signed-off-by Lucas Stach <[email protected]>--- drivers/clk/tegra/clk-tegra30.c | 1 + 1 file changed, 1 insertion(+)
Applied, thanks.
Thierry