serial: 8250_fintek: Fix the IRQ mode and code refactoring
v2 cover serial: 8250_fintek: Fix the IRQ mode and code refactoring
The following patches will fix the Fintek LPC to UARTs IRQ mode mismatch issue and code refactoring.
Some BIOS only use _OSI("Linux") to distinguish between Linux & Windows. Apply Level/Low to UART trigger mode if Windows, Edge/High otherwise. But since 2.6.23 the mainline kernel no longer returns true for _OSI("Linux"). The BIOS ASL should avoid to use _OSI() to check system type and use ACPI MADT override IRQ mode instead.
We'll try to refactoring the source code more readable with SuperIO read/write register functions.
Changelog:
V2
1. Code refacting. Suggest by Ricardo Ribalda Delgado.
Ji-Ze Hong (Peter Hong) (6):
serial: 8250_fintek: Refactoring read/write method
serial: 8250_fintek: Set IRQ Mode when port probed
serial: 8250_fintek: Set maximum FIFO of F81216H
serial: 8250_fintek: Add F81216 Support
serial: 8250_fintek: Add F81866 Support
serial: 8250_fintek: Add F81865 Support
drivers/tty/serial/8250/8250_fintek.c | 231 +++++++++++++++++++++++++--------- 1 file changed, 173 insertions(+), 58 deletions(-)
Signature · 1 line
1.9.1
PATCH v2 1/6 serial: 8250_fintek: Refactoring read/write method
If we need to access SuperIO registers, It should write register offset to base_addr and read/write value to base_addr + 1 to perform read/write. We can make it more simply with write/read functions.
This patch add sio_read_reg()/sio_write_reg()/sio_write_mask_reg() to reduce SuperIO register operation with lot of outb()/inb().
Signed-off-by Ji-Ze Hong (Peter Hong) <[email protected]>
--- drivers/tty/serial/8250/8250_fintek.c | 73 ++++++++++++++++++----------------- 1 file changed, 38 insertions(+), 35 deletions(-)
drivers/tty/serial/8250/8250_fintek.c +38 -35
@@ -49,6 +49,27 @@ struct fintek_8250 {u8 key; }; +static u8 sio_read_reg (struct fintek_8250 *pdata,u8 reg) +{ +outb (reg, pdata->base_port +ADDR_PORT ); +return inb (pdata->base_port +DATA_PORT ); +} + +static void sio_write_reg (struct fintek_8250 *pdata,u8 reg,u8 data) +{ +outb (reg, pdata->base_port +ADDR_PORT ); +outb (data, pdata->base_port +DATA_PORT ); +} + +static void sio_write_mask_reg (struct fintek_8250 *pdata,u8 reg,u8 mask, +u8 data) +{ +u8 tmp; + + tmp = (sio_read_reg (pdata, reg) & ~mask) | (mask & data); +sio_write_reg (pdata, reg, tmp); +} +static int fintek_8250_enter_key (u16 base_port,u8 key) {if (!request_muxed_region (base_port,2 ,"8250_fintek" ))
@@ -66,22 +87,18 @@ static void fintek_8250_exit_key(u16 base_port)release_region (base_port +ADDR_PORT ,2 ); } -static int fintek_8250_check_id (u16 base_port) +static int fintek_8250_check_id (struct fintek_8250 *pdata) {u16 chip; -outb (VENDOR_ID1 , base_port +ADDR_PORT ); -if (inb (base_port +DATA_PORT ) !=VENDOR_ID1_VAL ) +if (sio_read_reg (pdata,VENDOR_ID1 ) !=VENDOR_ID1_VAL )return -ENODEV ; -outb (VENDOR_ID2 , base_port +ADDR_PORT ); -if (inb (base_port +DATA_PORT ) !=VENDOR_ID2_VAL ) +if (sio_read_reg (pdata,VENDOR_ID2 ) !=VENDOR_ID2_VAL )return -ENODEV ; -outb (CHIP_ID1 , base_port +ADDR_PORT ); - chip =inb (base_port +DATA_PORT ); -outb (CHIP_ID2 , base_port +ADDR_PORT ); - chip |=inb (base_port +DATA_PORT ) <<8 ; + chip =sio_read_reg (pdata,CHIP_ID1 ); + chip |=sio_read_reg (pdata,CHIP_ID2 ) <<8 ;if (chip !=CHIP_ID_0 && chip !=CHIP_ID_1 )return -ENODEV ;
@@ -128,10 +145,8 @@ static int fintek_8250_rs485_config(struct uart_port *port,if (fintek_8250_enter_key (pdata->base_port, pdata->key))return -EBUSY ; -outb (LDN , pdata->base_port +ADDR_PORT ); -outb (pdata->index, pdata->base_port +DATA_PORT ); -outb (RS485 , pdata->base_port +ADDR_PORT ); -outb (config, pdata->base_port +DATA_PORT ); +sio_write_reg (pdata,LDN , pdata->index); +sio_write_reg (pdata,RS485 , config);fintek_8250_exit_key (pdata->base_port); port->rs485 = *rs485;
@@ -147,10 +162,12 @@ static int find_base_port(struct fintek_8250 *pdata, u16 io_address)for (i =0 ; i <ARRAY_SIZE (addr); i++) {for (j =0 ; j <ARRAY_SIZE (keys); j++) { + pdata->base_port = addr[i]; + pdata->key = keys[j];if (fintek_8250_enter_key (addr[i], keys[j]))continue ; -if (fintek_8250_check_id (addr[i])) { +if (fintek_8250_check_id (pdata)) {fintek_8250_exit_key (addr[i]);continue ; }
@@ -158,19 +175,13 @@ static int find_base_port(struct fintek_8250 *pdata, u16 io_address)for (k =0 ; k <4 ; k++) {u16 aux; -outb (LDN , addr[i] +ADDR_PORT ); -outb (k, addr[i] +DATA_PORT ); - -outb (IO_ADDR1 , addr[i] +ADDR_PORT ); - aux =inb (addr[i] +DATA_PORT ); -outb (IO_ADDR2 , addr[i] +ADDR_PORT ); - aux |=inb (addr[i] +DATA_PORT ) <<8 ; +sio_write_reg (pdata,LDN , k); + aux =sio_read_reg (pdata,IO_ADDR1 ); + aux |=sio_read_reg (pdata,IO_ADDR2 ) <<8 ;if (aux != io_address)continue ;fintek_8250_exit_key (addr[i]); - pdata->key = keys[j]; - pdata->base_port = addr[i]; pdata->index = k;return 0 ;
@@ -186,24 +197,16 @@ static int find_base_port(struct fintek_8250 *pdata, u16 io_address)static int fintek_8250_set_irq_mode (struct fintek_8250 *pdata,bool level_mode) {int status; -u8 tmp; status =fintek_8250_enter_key (pdata->base_port, pdata->key);if (status)return status; -outb (LDN , pdata->base_port +ADDR_PORT ); -outb (pdata->index, pdata->base_port +DATA_PORT ); - -outb (FINTEK_IRQ_MODE , pdata->base_port +ADDR_PORT ); - tmp =inb (pdata->base_port +DATA_PORT ); - - tmp &= ~IRQ_MODE_MASK ; - tmp |=IRQ_SHARE ; -if (!level_mode) - tmp |=IRQ_EDGE_HIGH ; +sio_write_reg (pdata,LDN , pdata->index); +sio_write_mask_reg (pdata,FINTEK_IRQ_MODE ,IRQ_SHARE ,IRQ_SHARE ); +sio_write_mask_reg (pdata,FINTEK_IRQ_MODE ,IRQ_MODE_MASK , + level_mode ?IRQ_LEVEL_LOW :IRQ_EDGE_HIGH ); -outb (tmp, pdata->base_port +DATA_PORT );fintek_8250_exit_key (pdata->base_port);return 0 ; }
Signature · 1 line
1.9.1
PATCH v2 2/6 serial: 8250_fintek: Set IRQ Mode when port probed
In reply to Ji-Ze Hong (Peter Hong)Set IRQ Mode when port probed in probe_setup_port()
It should hold the IO port premission via fintek_8250_enter_key() and release via fintek_8250_exit_key() when we configure the SuperIO.
This patch will move all SuperIO configure operations to probe_setup_port() to reduce fintek_8250_enter_key() and fintek_8250_exit_key() usage.
Suggested-by Ricardo Ribalda Delgado <[email protected]>
Signed-off-by Ji-Ze Hong (Peter Hong) <[email protected]>
--- drivers/tty/serial/8250/8250_fintek.c | 45 +++++++++++++++++------------------ 1 file changed, 22 insertions(+), 23 deletions(-)
drivers/tty/serial/8250/8250_fintek.c +22 -23
@@ -154,10 +154,21 @@ static int fintek_8250_rs485_config(struct uart_port *port,return 0 ; } -static int find_base_port (struct fintek_8250 *pdata,u16 io_address) +static void fintek_8250_set_irq_mode (struct fintek_8250 *pdata,bool is_level) +{ +sio_write_reg (pdata,LDN , pdata->index); +sio_write_mask_reg (pdata,FINTEK_IRQ_MODE ,IRQ_SHARE ,IRQ_SHARE ); +sio_write_mask_reg (pdata,FINTEK_IRQ_MODE ,IRQ_MODE_MASK , + is_level ?IRQ_LEVEL_LOW :IRQ_EDGE_HIGH ); +} + +static int probe_setup_port (struct fintek_8250 *pdata,u16 io_address, +unsigned int irq) {static const u16 addr[] = {0x4e ,0x2e };static const u8 keys[] = {0x77 ,0xa0 ,0x87 ,0x67 }; +struct irq_data *irq_data; +bool level_mode = false;int i, j, k;for (i =0 ; i <ARRAY_SIZE (addr); i++) {
@@ -181,9 +192,16 @@ static int find_base_port(struct fintek_8250 *pdata, u16 io_address)if (aux != io_address)continue ; -fintek_8250_exit_key (addr[i]); pdata->index = k; + irq_data =irq_get_irq_data (irq); +if (irq_data) + level_mode = +irqd_is_level_type (irq_data); + +fintek_8250_set_irq_mode (pdata, level_mode); +fintek_8250_exit_key (addr[i]); +return 0 ; }
@@ -194,31 +212,12 @@ static int find_base_port(struct fintek_8250 *pdata, u16 io_address)return -ENODEV ; } -static int fintek_8250_set_irq_mode (struct fintek_8250 *pdata,bool level_mode) -{ -int status; - - status =fintek_8250_enter_key (pdata->base_port, pdata->key); -if (status) -return status; - -sio_write_reg (pdata,LDN , pdata->index); -sio_write_mask_reg (pdata,FINTEK_IRQ_MODE ,IRQ_SHARE ,IRQ_SHARE ); -sio_write_mask_reg (pdata,FINTEK_IRQ_MODE ,IRQ_MODE_MASK , - level_mode ?IRQ_LEVEL_LOW :IRQ_EDGE_HIGH ); - -fintek_8250_exit_key (pdata->base_port); -return 0 ; -} -int fintek_8250_probe (struct uart_8250_port *uart) {struct fintek_8250 *pdata;struct fintek_8250 probe_data; -struct irq_data *irq_data =irq_get_irq_data (uart->port.irq); -bool level_mode =irqd_is_level_type (irq_data); -if (find_base_port (&probe_data, uart->port.iobase)) +if (probe_setup_port (&probe_data, uart->port.iobase, uart->port.irq))return -ENODEV ; pdata =devm_kzalloc (uart->port.dev,sizeof (*pdata),GFP_KERNEL );
@@ -229,5 +228,5 @@ int fintek_8250_probe(struct uart_8250_port *uart) uart->port.rs485_config = fintek_8250_rs485_config; uart->port.private_data = pdata; -return fintek_8250_set_irq_mode (pdata, level_mode); +return 0 ; }
Signature · 1 line
1.9.1
PATCH v2 3/6 serial: 8250_fintek: Set maximum FIFO of F81216H
In reply to Ji-Ze Hong (Peter Hong)The Fintek F81216H had maximum 128Bytes FIFO, but some BIOS configurated as normal 16Bytes FIFO. This patch will set 128Bytes FIFO and trigger level multiplier as 4x when F81216H detected.
Default 16550A trigger level is 8Bytes. When this patch applied, the trigger level will change to 8Byte x 4 = 32Byte. It can be reduce the RX incoming interrupts.
Suggested-by Ricardo Ribalda Delgado <[email protected]>
Signed-off-by Ji-Ze Hong (Peter Hong) <[email protected]>
--- drivers/tty/serial/8250/8250_fintek.c | 29 ++++++++++++++++++++++++++--- 1 file changed, 26 insertions(+), 3 deletions(-)
drivers/tty/serial/8250/8250_fintek.c +26 -3
@@ -21,8 +21,8 @@#define EXIT_KEY 0xAA#define CHIP_ID1 0x20#define CHIP_ID2 0x21 -#define CHIP_ID_0 0x1602 -#define CHIP_ID_1 0x0501 +#define CHIP_ID_F81216AD 0x1602 +#define CHIP_ID_F81216H 0x0501#define VENDOR_ID1 0x23#define VENDOR_ID1_VAL 0x19#define VENDOR_ID2 0x24
@@ -43,7 +43,14 @@#define RXW4C_IRA BIT(3)#define TXW4C_IRA BIT(2) +#define FIFO_CTRL 0xF6 +#define FIFO_MODE_MASK (BIT(1) | BIT(0)) +#define FIFO_MODE_128 (BIT(1) | BIT(0)) +#define RXFTHR_MODE_MASK (BIT(5) | BIT(4)) +#define RXFTHR_MODE_4X BIT(5) +struct fintek_8250 { +u16 pid;u16 base_port;u8 index;u8 key;
@@ -100,9 +107,10 @@ static int fintek_8250_check_id(struct fintek_8250 *pdata) chip =sio_read_reg (pdata,CHIP_ID1 ); chip |=sio_read_reg (pdata,CHIP_ID2 ) <<8 ; -if (chip !=CHIP_ID_0 && chip !=CHIP_ID_1 ) +if (chip !=CHIP_ID_F81216AD && chip !=CHIP_ID_F81216H )return -ENODEV ; + pdata->pid = chip;return 0 ; }
@@ -162,6 +170,20 @@ static void fintek_8250_set_irq_mode(struct fintek_8250 *pdata, bool is_level) is_level ? IRQ_LEVEL_LOW : IRQ_EDGE_HIGH); } +static void fintek_8250_set_max_fifo (struct fintek_8250 *pdata) +{ +switch (pdata->pid) { +case CHIP_ID_F81216H :/* 128Bytes FIFO */ +sio_write_mask_reg (pdata,FIFO_CTRL , +FIFO_MODE_MASK |RXFTHR_MODE_MASK , +FIFO_MODE_128 |RXFTHR_MODE_4X ); +break ; + +default :/* Default 16Bytes FIFO */ +break ; + } +} +static int probe_setup_port (struct fintek_8250 *pdata,u16 io_address,unsigned int irq) {
@@ -200,6 +222,7 @@ static int probe_setup_port(struct fintek_8250 *pdata, u16 io_address,irqd_is_level_type (irq_data);fintek_8250_set_irq_mode (pdata, level_mode); +fintek_8250_set_max_fifo (pdata);fintek_8250_exit_key (addr[i]);return 0 ;
Signature · 1 line
1.9.1
PATCH v2 4/6 serial: 8250_fintek: Add F81216 Support
In reply to Ji-Ze Hong (Peter Hong)Fintek F81216 is a LPC to 4 UARTs device. It's the F81216 series but support less functional than F81216AD/F81216H
The following list is brief descriptions of F81216 series:
F81216H (0105)
9Bit/High baud rate(not implements with mainline) RS485, 128Bytes FIFO (implemented)
F81216AD (0216)
9Bit(not implements with mainline) RS485(implemented)
F81216 (0208)
basically 16550A
Suggested-by Ricardo Ribalda Delgado <[email protected]>
Signed-off-by Ji-Ze Hong (Peter Hong) <[email protected]>
--- drivers/tty/serial/8250/8250_fintek.c | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-)
drivers/tty/serial/8250/8250_fintek.c +24 -2
@@ -23,6 +23,7 @@#define CHIP_ID2 0x21#define CHIP_ID_F81216AD 0x1602#define CHIP_ID_F81216H 0x0501 +#define CHIP_ID_F81216 0x0802#define VENDOR_ID1 0x23#define VENDOR_ID1_VAL 0x19#define VENDOR_ID2 0x24
@@ -107,8 +108,14 @@ static int fintek_8250_check_id(struct fintek_8250 *pdata) chip =sio_read_reg (pdata,CHIP_ID1 ); chip |=sio_read_reg (pdata,CHIP_ID2 ) <<8 ; -if (chip !=CHIP_ID_F81216AD && chip !=CHIP_ID_F81216H ) +switch (chip) { +case CHIP_ID_F81216AD : +case CHIP_ID_F81216H : +case CHIP_ID_F81216 : +break ; +default :return -ENODEV ; + } pdata->pid = chip;return 0 ;
@@ -235,6 +242,21 @@ static int probe_setup_port(struct fintek_8250 *pdata, u16 io_address,return -ENODEV ; } +static void fintek_8250_set_rs485_handler (struct uart_8250_port *uart) +{ +struct fintek_8250 *pdata = uart->port.private_data; + +switch (pdata->pid) { +case CHIP_ID_F81216AD : +case CHIP_ID_F81216H : + uart->port.rs485_config = fintek_8250_rs485_config; +break ; + +default :/* No RS485 Auto direction functional */ +break ; + } +} +int fintek_8250_probe (struct uart_8250_port *uart) {struct fintek_8250 *pdata;
@@ -248,8 +270,8 @@ int fintek_8250_probe(struct uart_8250_port *uart)return -ENOMEM ;memcpy (pdata, &probe_data,sizeof (probe_data)); - uart->port.rs485_config = fintek_8250_rs485_config; uart->port.private_data = pdata; +fintek_8250_set_rs485_handler (uart);return 0 ; }
Signature · 1 line
1.9.1
PATCH v2 5/6 serial: 8250_fintek: Add F81866 Support
In reply to Ji-Ze Hong (Peter Hong)Fintek F81866 is a LPC to 6 UARTs SuperIO. It has fully functional UARTs likes F81216H. It's also need check the IRQ mode with system assigned, but the configuration is not the same with F81216 series.
F81866 IRQ Mode setting:
0xf0 Bit1: IRQ_MODE0 Bit0: Share mode (always on) 0xf6 Bit3: IRQ_MODE1 Level/Low: IRQ_MODE0:0, IRQ_MODE1:0 Edge/High: IRQ_MODE0:1, IRQ_MODE1:0
The following list is brief descriptions of F81866:
F81866 (1010)
9Bit/High baud rate(not implements with mainline) RS485, 128Bytes FIFO (implemented)
Signed-off-by Ji-Ze Hong (Peter Hong) <[email protected]>
--- drivers/tty/serial/8250/8250_fintek.c | 74 ++++++++++++++++++++++++++++++++--- 1 file changed, 68 insertions(+), 6 deletions(-)
drivers/tty/serial/8250/8250_fintek.c +68 -6
@@ -21,6 +21,7 @@#define EXIT_KEY 0xAA#define CHIP_ID1 0x20#define CHIP_ID2 0x21 +#define CHIP_ID_F81866 0x1010#define CHIP_ID_F81216AD 0x1602#define CHIP_ID_F81216H 0x0501#define CHIP_ID_F81216 0x0802
@@ -50,6 +51,26 @@#define RXFTHR_MODE_MASK (BIT(5) | BIT(4))#define RXFTHR_MODE_4X BIT(5) +#define F81216_LDN_LOW 0x0 +#define F81216_LDN_HIGH 0x4 + +/* +* F81866 registers +* +* The IRQ setting mode of F81866 is not the same with F81216 series. +* Level/Low: IRQ_MODE0:0, IRQ_MODE1:0 +* Edge/High: IRQ_MODE0:1, IRQ_MODE1:0 +*/ +#define F81866_IRQ_MODE 0xf0 +#define F81866_IRQ_SHARE BIT(0) +#define F81866_IRQ_MODE0 BIT(1) + +#define F81866_FIFO_CTRL FIFO_CTRL +#define F81866_IRQ_MODE1 BIT(3) + +#define F81866_LDN_LOW 0x10 +#define F81866_LDN_HIGH 0x16 +struct fintek_8250 {u16 pid;u16 base_port;
@@ -109,6 +130,7 @@ static int fintek_8250_check_id(struct fintek_8250 *pdata) chip |=sio_read_reg (pdata,CHIP_ID2 ) <<8 ;switch (chip) { +case CHIP_ID_F81866 :case CHIP_ID_F81216AD :case CHIP_ID_F81216H :case CHIP_ID_F81216 :
@@ -121,6 +143,26 @@ static int fintek_8250_check_id(struct fintek_8250 *pdata)return 0 ; } +static int fintek_8250_get_ldn_range (struct fintek_8250 *pdata,int *min, +int *max) +{ +switch (pdata->pid) { +case CHIP_ID_F81866 : + *min =F81866_LDN_LOW ; + *max =F81866_LDN_HIGH ; +return 0 ; + +case CHIP_ID_F81216AD : +case CHIP_ID_F81216H : +case CHIP_ID_F81216 : + *min =F81216_LDN_LOW ; + *max =F81216_LDN_HIGH ; +return 0 ; + } + +return -ENODEV ; +} +static int fintek_8250_rs485_config (struct uart_port *port,struct serial_rs485 *rs485) {
@@ -172,15 +214,33 @@ static int fintek_8250_rs485_config(struct uart_port *port,static void fintek_8250_set_irq_mode (struct fintek_8250 *pdata,bool is_level) {sio_write_reg (pdata,LDN , pdata->index); -sio_write_mask_reg (pdata,FINTEK_IRQ_MODE ,IRQ_SHARE ,IRQ_SHARE ); -sio_write_mask_reg (pdata,FINTEK_IRQ_MODE ,IRQ_MODE_MASK , - is_level ?IRQ_LEVEL_LOW :IRQ_EDGE_HIGH ); + +switch (pdata->pid) { +case CHIP_ID_F81866 : +sio_write_mask_reg (pdata,F81866_FIFO_CTRL ,F81866_IRQ_MODE1 , +0 ); +sio_write_mask_reg (pdata,F81866_IRQ_MODE ,F81866_IRQ_SHARE , +F81866_IRQ_SHARE ); +sio_write_mask_reg (pdata,F81866_IRQ_MODE ,F81866_IRQ_MODE0 , + is_level ?0 :F81866_IRQ_MODE0 ); +break ; + +case CHIP_ID_F81216AD : +case CHIP_ID_F81216H : +case CHIP_ID_F81216 : +sio_write_mask_reg (pdata,FINTEK_IRQ_MODE ,IRQ_SHARE , +IRQ_SHARE ); +sio_write_mask_reg (pdata,FINTEK_IRQ_MODE ,IRQ_MODE_MASK , + is_level ?IRQ_LEVEL_LOW :IRQ_EDGE_HIGH ); +break ; + } }static void fintek_8250_set_max_fifo (struct fintek_8250 *pdata) {switch (pdata->pid) {case CHIP_ID_F81216H :/* 128Bytes FIFO */ +case CHIP_ID_F81866 :sio_write_mask_reg (pdata,FIFO_CTRL ,FIFO_MODE_MASK |RXFTHR_MODE_MASK ,FIFO_MODE_128 |RXFTHR_MODE_4X );
@@ -198,7 +258,7 @@ static int probe_setup_port(struct fintek_8250 *pdata, u16 io_address,static const u8 keys[] = {0x77 ,0xa0 ,0x87 ,0x67 };struct irq_data *irq_data;bool level_mode = false; -int i, j, k; +int i, j, k, min, max;for (i =0 ; i <ARRAY_SIZE (addr); i++) {for (j =0 ; j <ARRAY_SIZE (keys); j++) {
@@ -207,12 +267,13 @@ static int probe_setup_port(struct fintek_8250 *pdata, u16 io_address,if (fintek_8250_enter_key (addr[i], keys[j]))continue ; -if (fintek_8250_check_id (pdata)) { +if (fintek_8250_check_id (pdata) || +fintek_8250_get_ldn_range (pdata, &min, &max)) {fintek_8250_exit_key (addr[i]);continue ; } -for (k =0 ; k <4 ; k++) { +for (k = min; k < max; k++) {u16 aux;sio_write_reg (pdata,LDN , k);
@@ -249,6 +310,7 @@ static void fintek_8250_set_rs485_handler(struct uart_8250_port *uart)switch (pdata->pid) {case CHIP_ID_F81216AD :case CHIP_ID_F81216H : +case CHIP_ID_F81866 : uart->port.rs485_config = fintek_8250_rs485_config;break ;
Signature · 1 line
1.9.1
PATCH v2 6/6 serial: 8250_fintek: Add F81865 Support
In reply to Ji-Ze Hong (Peter Hong)Fintek F81865 is a LPC to 6 UARTs SuperIO. It has less functional UARTs likes F81866. It's also need check the IRQ mode with system assigned, but the configuration is not the same with F81216 series.
F81865 IRQ Mode setting:
0xf0
Bit1: IRQ_MODE0
Bit0: Share mode (always on)
Level/Low: IRQ_MODE0:0
Edge/High: IRQ_MODE0:1The following list is brief descriptions of F81865:
F81865 (0704)
9Bit(not implements with mainline)
RS485(implemented)
Suggested-by Ricardo Ribalda Delgado <[email protected]>
Signed-off-by Ji-Ze Hong (Peter Hong) <[email protected]>
--- drivers/tty/serial/8250/8250_fintek.c | 6 ++++++ 1 file changed, 6 insertions(+)
drivers/tty/serial/8250/8250_fintek.c +6 -0
@@ -21,6 +21,7 @@#define EXIT_KEY 0xAA#define CHIP_ID1 0x20#define CHIP_ID2 0x21 +#define CHIP_ID_F81865 0x0407#define CHIP_ID_F81866 0x1010#define CHIP_ID_F81216AD 0x1602#define CHIP_ID_F81216H 0x0501
@@ -130,6 +131,7 @@ static int fintek_8250_check_id(struct fintek_8250 *pdata) chip |=sio_read_reg (pdata,CHIP_ID2 ) <<8 ;switch (chip) { +case CHIP_ID_F81865 :case CHIP_ID_F81866 :case CHIP_ID_F81216AD :case CHIP_ID_F81216H :
@@ -147,6 +149,7 @@ static int fintek_8250_get_ldn_range(struct fintek_8250 *pdata, int *min, int *max) {switch (pdata->pid) { +case CHIP_ID_F81865 :case CHIP_ID_F81866 : *min =F81866_LDN_LOW ; *max =F81866_LDN_HIGH ;
@@ -219,6 +222,8 @@ static void fintek_8250_set_irq_mode(struct fintek_8250 *pdata, bool is_level)case CHIP_ID_F81866 :sio_write_mask_reg (pdata,F81866_FIFO_CTRL ,F81866_IRQ_MODE1 ,0 ); +/* fall through */ +case CHIP_ID_F81865 :sio_write_mask_reg (pdata,F81866_IRQ_MODE ,F81866_IRQ_SHARE ,F81866_IRQ_SHARE ); sio_write_mask_reg(pdata, F81866_IRQ_MODE, F81866_IRQ_MODE0,
@@ -311,6 +316,7 @@ static void fintek_8250_set_rs485_handler(struct uart_8250_port *uart)case CHIP_ID_F81216AD :case CHIP_ID_F81216H :case CHIP_ID_F81866 : +case CHIP_ID_F81865 : uart->port.rs485_config = fintek_8250_rs485_config;break ;
Signature · 1 line
1.9.1