mmc: sdhci-msm: Add clk-rates, DDR, HS400 support

From: Venkat Gopalakrishnan <[email protected]>

The following msm platform specific changes are added to support HS400.
- Allow tuning for HS400 mode.
- Configure HS400 timing mode using the VENDOR_SPECIFIC_FUNC register.

Signed-off-by Venkat Gopalakrishnan <[email protected]>

Signed-off-by Ritesh Harjani <[email protected]>

---
 drivers/mmc/host/sdhci-msm.c | 124 +++++++++++++++++++++++++++++++++++++++----
 1 file changed, 113 insertions(+), 11 deletions(-)

drivers/mmc/host/sdhci-msm.c +12 -2

index eb1a9e3..612fa82 100644
@@ -31,6 +31,7 @@
 #define HC_MODE_EN		0x1
 #define CORE_POWER		0x0
 #define CORE_SW_RST		BIT(7)
+#define FF_CLK_SW_RST_DIS	BIT(13)
 
 #define CORE_PWRCTL_STATUS	0xdc
 #define CORE_PWRCTL_MASK	0xe0

@@ -64,11 +65,18 @@
 
 #define CORE_VENDOR_SPEC	0x10c
 #define CORE_CLK_PWRSAVE	BIT(1)
+#define CORE_HC_MCLK_SEL_DFLT	(2 << 8)
+#define CORE_HC_MCLK_SEL_HS400	(3 << 8)
+#define CORE_HC_MCLK_SEL_MASK	(3 << 8)
+#define CORE_HC_SELECT_IN_EN	(1 << 18)
+#define CORE_HC_SELECT_IN_HS400	(6 << 19)
+#define CORE_HC_SELECT_IN_MASK	(7 << 19)
 
 #define CORE_VENDOR_SPEC_CAPABILITIES0	0x11c
 
 #define TCXO_FREQ		19200000
 #define SDHCI_MSM_MIN_CLOCK	400000
+#define CORE_FREQ_100MHZ	(100 * 1000 * 1000)
 
 #define CDR_SELEXT_SHIFT	20
 #define CDR_SELEXT_MASK		(0xf << CDR_SELEXT_SHIFT)

@@ -87,6 +95,8 @@ struct sdhci_msm_host {
 	u32 clk_rate;
 	struct mmc_host *mmc;
 	bool use_14lpp_dll_reset;
+	bool tuning_done;
+	bool calibration_done;
 };
 
 /* Platform specific tuning */

@@ -175,8 +185,8 @@ out:
  * Find out the greatest range of consecuitive selected
  * DLL clock output phases that can be used as sampling
  * setting for SD3.0 UHS-I card read operation (in SDR104
- * timing mode) or for eMMC4.5 card read operation (in HS200
- * timing mode).
+ * timing mode) or for eMMC4.5 card read operation (in
+ * HS400/HS200 timing mode).
  * Select the 3/4 of the range and configure the DLL with the
  * selected DLL clock output phase.
  */

drivers/mmc/host/sdhci-msm.c +14 -5

 		return 0;
 
 retry:

@@ -488,7 +499,10 @@ static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host,
 					unsigned int uhs)
 {
 	struct mmc_host *mmc = host->mmc;
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 	u16 ctrl_2;
+	u32 config;
 
 	ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 	/* Select Bus Speed Mode for host */

@@ -503,6 +517,7 @@ static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host,
 	case MMC_TIMING_UHS_SDR50:
 		ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
 		break;
+	case MMC_TIMING_MMC_HS400:
 	case MMC_TIMING_MMC_HS200:
 	case MMC_TIMING_UHS_SDR104:
 		ctrl_2 |= SDHCI_CTRL_UHS_SDR104;

@@ -519,11 +534,33 @@ static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host,
 	 * provide feedback clock, the mode selection can be any value less
 	 * than 3'b011 in bits [2:0] of HOST CONTROL2 register.
 	 */
-	if (host->clock <= 100000000 &&
-	    (uhs == MMC_TIMING_MMC_HS400 ||
-	     uhs == MMC_TIMING_MMC_HS200 ||
-	     uhs == MMC_TIMING_UHS_SDR104))
-		ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
+	if (host->clock <= CORE_FREQ_100MHZ) {
+		if ((uhs == MMC_TIMING_MMC_HS400) ||
+			(uhs == MMC_TIMING_MMC_HS200) ||
+			(uhs == MMC_TIMING_UHS_SDR104))
+			ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
+		/*
+		 * Make sure DLL is disabled when not required
+		 *
+		 * Write 1 to DLL_RST bit of DLL_CONFIG register
+		 */

drivers/mmc/host/sdhci-msm.c +27 -1

+
+		/*
+		 * The DLL needs to be restored and CDCLP533 recalibrated
+		 * when the clock frequency is set back to 400MHz.
+		 */
+		msm_host->calibration_done = false;
+	}
 
 	dev_dbg(mmc_dev(mmc), "%s: clock=%u uhs=%u ctrl_2=0x%x\n",
 		mmc_hostname(host->mmc), host->clock, uhs, ctrl_2);

@@ -670,7 +707,7 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 	struct mmc_ios curr_ios = host->mmc->ios;
-	u32 msm_clock;
+	u32 msm_clock, config;
 	int rc;
 
 	if (!clock)

@@ -691,6 +728,66 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
 	}
 	msm_clock = sdhci_msm_get_msm_clk_rate(host, clock);
 
+	/*
+	 * In general all timing modes are controlled via UHS mode select in
+	 * Host Control2 register. eMMC specific HS200/HS400 doesn't have
+	 * their respective modes defined here, hence we use these values.
+	 *
+	 * HS200 - SDR104 (Since they both are equivalent in functionality)
+	 * HS400 - This involves multiple configurations
+	 *		Initially SDR104 - when tuning is required as HS200
+	 *		Then when switching to DDR @ 400MHz (HS400) we use
+	 *		the vendor specific HC_SELECT_IN to control the mode.
+	 *
+	 * In addition to controlling the modes we also need to select the
+	 * correct input clock for DLL depending on the mode.
+	 *
+	 * HS400 - divided clock (free running MCLK/2)
+	 * All other modes - default (free running MCLK)
+	 */
+	if (curr_ios.timing == MMC_TIMING_MMC_HS400) {
+		/* Select the divided clock (free running MCLK/2) */

drivers/mmc/host/sdhci-msm.c +20 -0

+			/*
+			 * Write 0x6 to HC_SELECT_IN and 1 to HC_SELECT_IN_EN
+			 * field in VENDOR_SPEC_FUNC
+			 */
+			config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
+			config |= CORE_HC_SELECT_IN_HS400;
+			config |= CORE_HC_SELECT_IN_EN;
+			writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
+		}
+	} else {
+		/* Select the default clock (free running MCLK) */
+		config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
+		config &= ~CORE_HC_MCLK_SEL_MASK;
+		config |= CORE_HC_MCLK_SEL_DFLT;
+		writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
+
+		/*
+		 * Disable HC_SELECT_IN to be able to use the UHS mode select
+		 * configuration from Host Control2 register for all other
+		 * modes.

drivers/mmc/host/sdhci-msm.c +6 -0

+
 	if ((msm_clock != msm_host->clk_rate) && msm_host->clk_table) {
 		rc = clk_set_rate(msm_host->clk, msm_clock);
 		if (rc) {

@@ -876,6 +973,11 @@ static int sdhci_msm_probe(struct platform_device *pdev)
 	/* Set HC_MODE_EN bit in HC_MODE register */
 	writel_relaxed(HC_MODE_EN, (msm_host->core_mem + CORE_HC_MODE));
 
+	/* Set FF_CLK_SW_RST_DIS bit in HC_MODE register */
+	config = readl_relaxed(msm_host->core_mem + CORE_HC_MODE);
+	config |= FF_CLK_SW_RST_DIS;
+	writel_relaxed(config, msm_host->core_mem + CORE_HC_MODE);
+
 	host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION));
 	dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n",
 		host_version, ((host_version & SDHCI_VENDOR_VER_MASK) >>

Quoted 68 lines · Ritesh Harjani

From: Venkat Gopalakrishnan <[email protected]>

The following msm platform specific changes are added to support HS400.
- Allow tuning for HS400 mode.
- Configure HS400 timing mode using the VENDOR_SPECIFIC_FUNC register.

Signed-off-by Venkat Gopalakrishnan <[email protected]>

Signed-off-by Ritesh Harjani <[email protected]>

---
 drivers/mmc/host/sdhci-msm.c | 124 +++++++++++++++++++++++++++++++++++++++----
 1 file changed, 113 insertions(+), 11 deletions(-)

drivers/mmc/host/sdhci-msm.c +12 -3

index eb1a9e3..612fa82 100644
@@ -31,6 +31,7 @@
 #define HC_MODE_EN		0x1
 #define CORE_POWER		0x0
 #define CORE_SW_RST		BIT(7)
+#define FF_CLK_SW_RST_DIS	BIT(13)
 
 #define CORE_PWRCTL_STATUS	0xdc
 #define CORE_PWRCTL_MASK	0xe0

@@ -64,11 +65,18 @@
 
 #define CORE_VENDOR_SPEC	0x10c
 #define CORE_CLK_PWRSAVE	BIT(1)
+#define CORE_HC_MCLK_SEL_DFLT	(2 << 8)
+#define CORE_HC_MCLK_SEL_HS400	(3 << 8)
+#define CORE_HC_MCLK_SEL_MASK	(3 << 8)
+#define CORE_HC_SELECT_IN_EN	(1 << 18)
+#define CORE_HC_SELECT_IN_HS400	(6 << 19)
+#define CORE_HC_SELECT_IN_MASK	(7 << 19)
 
 #define CORE_VENDOR_SPEC_CAPABILITIES0	0x11c
 
 #define TCXO_FREQ		19200000
 #define SDHCI_MSM_MIN_CLOCK	400000
+#define CORE_FREQ_100MHZ	(100 * 1000 * 1000)
 
 #define CDR_SELEXT_SHIFT	20
 #define CDR_SELEXT_MASK		(0xf << CDR_SELEXT_SHIFT)

@@ -87,6 +95,8 @@ struct sdhci_msm_host {
 	u32 clk_rate;
 	struct mmc_host *mmc;
 	bool use_14lpp_dll_reset;
+	bool tuning_done;
+	bool calibration_done;
 };
 
 /* Platform specific tuning */

@@ -175,8 +185,8 @@ out:
  * Find out the greatest range of consecuitive selected
  * DLL clock output phases that can be used as sampling
  * setting for SD3.0 UHS-I card read operation (in SDR104
- * timing mode) or for eMMC4.5 card read operation (in HS200
- * timing mode).
+ * timing mode) or for eMMC4.5 card read operation (in
+ * HS400/HS200 timing mode).
  * Select the 3/4 of the range and configure the DLL with the
  * selected DLL clock output phase.
  */

@@ -428,9 +438,10 @@ static int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode)
 	 * Tuning is required for SDR104, HS200 and HS400 cards and
 	 * if clock frequency is greater than 100MHz in these modes.
 	 */
-	if (host->clock <= 100 * 1000 * 1000 ||

drivers/mmc/host/sdhci-msm.c static int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode) · line 444

Quoted 6 lines

drivers/mmc/host/sdhci-msm.c +4 -2

-	    !((ios.timing == MMC_TIMING_MMC_HS200) ||
-	      (ios.timing == MMC_TIMING_UHS_SDR104)))
+	if (host->clock <= CORE_FREQ_100MHZ ||
+		!((ios.timing == MMC_TIMING_MMC_HS400) ||
+		(ios.timing == MMC_TIMING_MMC_HS200) ||
+		(ios.timing == MMC_TIMING_UHS_SDR104)))

Don't need () around ios.timing == MMC_TIMING_MMC_HS400 etc

Quoted 46 lines

drivers/mmc/host/sdhci-msm.c +18 -5

 		return 0;
 
 retry:

@@ -488,7 +499,10 @@ static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host,
 					unsigned int uhs)
 {
 	struct mmc_host *mmc = host->mmc;
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 	u16 ctrl_2;
+	u32 config;
 
 	ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 	/* Select Bus Speed Mode for host */

@@ -503,6 +517,7 @@ static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host,
 	case MMC_TIMING_UHS_SDR50:
 		ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
 		break;
+	case MMC_TIMING_MMC_HS400:
 	case MMC_TIMING_MMC_HS200:
 	case MMC_TIMING_UHS_SDR104:
 		ctrl_2 |= SDHCI_CTRL_UHS_SDR104;

@@ -519,11 +534,33 @@ static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host,
 	 * provide feedback clock, the mode selection can be any value less
 	 * than 3'b011 in bits [2:0] of HOST CONTROL2 register.
 	 */
-	if (host->clock <= 100000000 &&
-	    (uhs == MMC_TIMING_MMC_HS400 ||
-	     uhs == MMC_TIMING_MMC_HS200 ||
-	     uhs == MMC_TIMING_UHS_SDR104))
-		ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
+	if (host->clock <= CORE_FREQ_100MHZ) {
+		if ((uhs == MMC_TIMING_MMC_HS400) ||
+			(uhs == MMC_TIMING_MMC_HS200) ||
+			(uhs == MMC_TIMING_UHS_SDR104))
+			ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
+		/*
+		 * Make sure DLL is disabled when not required
+		 *
+		 * Write 1 to DLL_RST bit of DLL_CONFIG register
+		 */
+		config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
+		config |= CORE_DLL_RST;
+		writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
+

drivers/mmc/host/sdhci-msm.c static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host, · line 556

Quoted 6 lines

drivers/mmc/host/sdhci-msm.c +6 -0

+		/* Write 1 to DLL_PDN bit of DLL_CONFIG register */
+		config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
+		config |= CORE_DLL_PDN;
+		writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
+
+		wmb(); /* drain writebuffer */

Memory barrier could use more explanation.

Quoted 49 lines

drivers/mmc/host/sdhci-msm.c +33 -1

+
+		/*
+		 * The DLL needs to be restored and CDCLP533 recalibrated
+		 * when the clock frequency is set back to 400MHz.
+		 */
+		msm_host->calibration_done = false;
+	}
 
 	dev_dbg(mmc_dev(mmc), "%s: clock=%u uhs=%u ctrl_2=0x%x\n",
 		mmc_hostname(host->mmc), host->clock, uhs, ctrl_2);

@@ -670,7 +707,7 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 	struct mmc_ios curr_ios = host->mmc->ios;
-	u32 msm_clock;
+	u32 msm_clock, config;
 	int rc;
 
 	if (!clock)

@@ -691,6 +728,66 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
 	}
 	msm_clock = sdhci_msm_get_msm_clk_rate(host, clock);
 
+	/*
+	 * In general all timing modes are controlled via UHS mode select in
+	 * Host Control2 register. eMMC specific HS200/HS400 doesn't have
+	 * their respective modes defined here, hence we use these values.
+	 *
+	 * HS200 - SDR104 (Since they both are equivalent in functionality)
+	 * HS400 - This involves multiple configurations
+	 *		Initially SDR104 - when tuning is required as HS200
+	 *		Then when switching to DDR @ 400MHz (HS400) we use
+	 *		the vendor specific HC_SELECT_IN to control the mode.
+	 *
+	 * In addition to controlling the modes we also need to select the
+	 * correct input clock for DLL depending on the mode.
+	 *
+	 * HS400 - divided clock (free running MCLK/2)
+	 * All other modes - default (free running MCLK)
+	 */
+	if (curr_ios.timing == MMC_TIMING_MMC_HS400) {
+		/* Select the divided clock (free running MCLK/2) */
+		config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
+		config &= ~CORE_HC_MCLK_SEL_MASK;
+		config |= CORE_HC_MCLK_SEL_HS400;
+
+		writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
+		/*

drivers/mmc/host/sdhci-msm.c static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock) · line 759

Quoted 4 lines

drivers/mmc/host/sdhci-msm.c +4 -0

+		 * Select HS400 mode using the HC_SELECT_IN from VENDOR SPEC
+		 * register
+		 */
+		if (msm_host->tuning_done && !msm_host->calibration_done) {

In this patch, tuning_done and calibration_done are never true. Is that intended?

Quoted 26 lines

drivers/mmc/host/sdhci-msm.c +24 -0

+			/*
+			 * Write 0x6 to HC_SELECT_IN and 1 to HC_SELECT_IN_EN
+			 * field in VENDOR_SPEC_FUNC
+			 */
+			config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
+			config |= CORE_HC_SELECT_IN_HS400;
+			config |= CORE_HC_SELECT_IN_EN;
+			writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
+		}
+	} else {
+		/* Select the default clock (free running MCLK) */
+		config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
+		config &= ~CORE_HC_MCLK_SEL_MASK;
+		config |= CORE_HC_MCLK_SEL_DFLT;
+		writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
+
+		/*
+		 * Disable HC_SELECT_IN to be able to use the UHS mode select
+		 * configuration from Host Control2 register for all other
+		 * modes.
+		 *
+		 * Write 0 to HC_SELECT_IN and HC_SELECT_IN_EN field
+		 * in VENDOR_SPEC_FUNC
+		 */

drivers/mmc/host/sdhci-msm.c static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock) · line 789

Quoted 6 lines

drivers/mmc/host/sdhci-msm.c +6 -0

+		config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
+		config &= ~CORE_HC_SELECT_IN_EN;
+		config &= ~CORE_HC_SELECT_IN_MASK;
+		writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
+	}
+	wmb(); /* drain writebuffer */

Memory barrier could use more explanation.

Quoted 18 lines

drivers/mmc/host/sdhci-msm.c +6 -0

+
 	if ((msm_clock != msm_host->clk_rate) && msm_host->clk_table) {
 		rc = clk_set_rate(msm_host->clk, msm_clock);
 		if (rc) {

@@ -876,6 +973,11 @@ static int sdhci_msm_probe(struct platform_device *pdev)
 	/* Set HC_MODE_EN bit in HC_MODE register */
 	writel_relaxed(HC_MODE_EN, (msm_host->core_mem + CORE_HC_MODE));
 
+	/* Set FF_CLK_SW_RST_DIS bit in HC_MODE register */
+	config = readl_relaxed(msm_host->core_mem + CORE_HC_MODE);
+	config |= FF_CLK_SW_RST_DIS;
+	writel_relaxed(config, msm_host->core_mem + CORE_HC_MODE);
+
 	host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION));
 	dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n",
 		host_version, ((host_version & SDHCI_VENDOR_VER_MASK) >>

From: Venkat Gopalakrishnan <[email protected]>

In HS400 mode a new RCLK is introduced on the interface for read data transfers. The eMMC5.0 device transmits the read data to the host with respect to rising and falling edges of RCLK. In order to ensure correct operation of read data transfers in HS400 mode, the incoming RX data needs to be sampled by delayed version of RCLK.

The CDCLP533 delay circuit shifts the RCLK by T/4. It needs to be initialized, configured and enabled once during HS400 mode switch and when operational voltage/clock is changed.

Signed-off-by Venkat Gopalakrishnan <[email protected]>

Signed-off-by Ritesh Harjani <[email protected]>

---
 drivers/mmc/host/sdhci-msm.c | 178 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 178 insertions(+)

drivers/mmc/host/sdhci-msm.c +176 -0

index 612fa82..dbf80a9c 100644
@@ -57,6 +57,7 @@
 #define CORE_DLL_PDN		BIT(29)
 #define CORE_DLL_RST		BIT(30)
 #define CORE_DLL_CONFIG		0x100
+#define CORE_CMD_DAT_TRACK_SEL	BIT(0)
 #define CORE_DLL_STATUS		0x108
 
 #define CORE_DLL_CONFIG_2	0x1b4

@@ -72,8 +73,36 @@
 #define CORE_HC_SELECT_IN_HS400	(6 << 19)
 #define CORE_HC_SELECT_IN_MASK	(7 << 19)
 
+#define CORE_CSR_CDC_CTLR_CFG0		0x130
+#define CORE_SW_TRIG_FULL_CALIB		BIT(16)
+#define CORE_HW_AUTOCAL_ENA		BIT(17)
+
+#define CORE_CSR_CDC_CTLR_CFG1		0x134
+#define CORE_CSR_CDC_CAL_TIMER_CFG0	0x138
+#define CORE_TIMER_ENA			BIT(16)
+
+#define CORE_CSR_CDC_CAL_TIMER_CFG1	0x13C
+#define CORE_CSR_CDC_REFCOUNT_CFG	0x140
+#define CORE_CSR_CDC_COARSE_CAL_CFG	0x144
+#define CORE_CDC_OFFSET_CFG		0x14C
+#define CORE_CSR_CDC_DELAY_CFG		0x150
+#define CORE_CDC_SLAVE_DDA_CFG		0x160
+#define CORE_CSR_CDC_STATUS0		0x164
+#define CORE_CALIBRATION_DONE		BIT(0)
+
+#define CORE_CDC_ERROR_CODE_MASK	0x7000000
+
+#define CORE_CSR_CDC_GEN_CFG		0x178
+#define CORE_CDC_SWITCH_BYPASS_OFF	BIT(0)
+#define CORE_CDC_SWITCH_RC_EN		BIT(1)
+
+#define CORE_DDR_200_CFG		0x184
+#define CORE_CDC_T4_DLY_SEL		BIT(0)
+#define CORE_START_CDC_TRAFFIC		BIT(6)
+
 #define CORE_VENDOR_SPEC_CAPABILITIES0	0x11c
 
+#define INVALID_TUNING_PHASE	-1
 #define TCXO_FREQ		19200000
 #define SDHCI_MSM_MIN_CLOCK	400000
 #define CORE_FREQ_100MHZ	(100 * 1000 * 1000)

@@ -97,6 +126,7 @@ struct sdhci_msm_host {
 	bool use_14lpp_dll_reset;
 	bool tuning_done;
 	bool calibration_done;
+	u8 saved_tuning_phase;
 };
 
 /* Platform specific tuning */

@@ -426,6 +456,136 @@ static int msm_init_cm_dll(struct sdhci_host *host)
 	return 0;
 }
 
+static int sdhci_msm_cdclp533_calibration(struct sdhci_host *host)
+{
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
+	u32 wait_cnt, config;
+	int ret;
+
+	pr_debug("%s: Enter %s\n", mmc_hostname(host->mmc), __func__);
+
+	/*
+	 * Retuning in HS400 (DDR mode) will fail, just reset the
+	 * tuning block and restore the saved tuning phase.
+	 */
+	ret = msm_init_cm_dll(host);
+	if (ret)
+		goto out;
+
+	/* Set the selected phase in delay line hw block */
+	ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase);
+	if (ret)
+		goto out;
+
+	/* Write 1 to CMD_DAT_TRACK_SEL field in DLL_CONFIG */
+	config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
+	config |= CORE_CMD_DAT_TRACK_SEL;
+	writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
+
+	/* Write 0 to CDC_T4_DLY_SEL field in VENDOR_SPEC_DDR200_CFG */
+	config = readl_relaxed(host->ioaddr + CORE_DDR_200_CFG);
+	config &= ~CORE_CDC_T4_DLY_SEL;
+	writel_relaxed(config, host->ioaddr + CORE_DDR_200_CFG);
+
+	/* Write 0 to CDC_SWITCH_BYPASS_OFF field in CORE_CSR_CDC_GEN_CFG */
+	config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
+	config &= ~CORE_CDC_SWITCH_BYPASS_OFF;
+	writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
+
+	/* Write 1 to CDC_SWITCH_RC_EN field in CORE_CSR_CDC_GEN_CFG */
+	config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
+	config |= CORE_CDC_SWITCH_RC_EN;
+	writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
+
+	/* Write 0 to START_CDC_TRAFFIC field in CORE_DDR200_CFG */
+	config = readl_relaxed(host->ioaddr + CORE_DDR_200_CFG);
+	config &= ~CORE_START_CDC_TRAFFIC;
+	writel_relaxed(config, host->ioaddr + CORE_DDR_200_CFG);
+
+	/*
+	 * Perform CDC Register Initialization Sequence
+	 *
+	 * CORE_CSR_CDC_CTLR_CFG0	0x11800EC
+	 * CORE_CSR_CDC_CTLR_CFG1	0x3011111
+	 * CORE_CSR_CDC_CAL_TIMER_CFG0	0x1201000
+	 * CORE_CSR_CDC_CAL_TIMER_CFG1	0x4
+	 * CORE_CSR_CDC_REFCOUNT_CFG	0xCB732020
+	 * CORE_CSR_CDC_COARSE_CAL_CFG	0xB19
+	 * CORE_CSR_CDC_DELAY_CFG	0x3AC
+	 * CORE_CDC_OFFSET_CFG		0x0
+	 * CORE_CDC_SLAVE_DDA_CFG	0x16334
+	 */
+
+	writel_relaxed(0x11800EC, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
+	writel_relaxed(0x3011111, host->ioaddr + CORE_CSR_CDC_CTLR_CFG1);
+	writel_relaxed(0x1201000, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
+	writel_relaxed(0x4, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG1);
+	writel_relaxed(0xCB732020, host->ioaddr + CORE_CSR_CDC_REFCOUNT_CFG);
+	writel_relaxed(0xB19, host->ioaddr + CORE_CSR_CDC_COARSE_CAL_CFG);
+	writel_relaxed(0x3AC, host->ioaddr + CORE_CSR_CDC_DELAY_CFG);
+	writel_relaxed(0x0, host->ioaddr + CORE_CDC_OFFSET_CFG);
+	writel_relaxed(0x16334, host->ioaddr + CORE_CDC_SLAVE_DDA_CFG);
+
+	/* CDC HW Calibration */
+
+	/* Write 1 to SW_TRIG_FULL_CALIB field in CORE_CSR_CDC_CTLR_CFG0 */
+	config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
+	config |= CORE_SW_TRIG_FULL_CALIB;
+	writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
+
+	/* Write 0 to SW_TRIG_FULL_CALIB field in CORE_CSR_CDC_CTLR_CFG0 */
+	config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
+	config &= ~CORE_SW_TRIG_FULL_CALIB;
+	writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
+
+	/* Write 1 to HW_AUTOCAL_ENA field in CORE_CSR_CDC_CTLR_CFG0 */
+	config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
+	config |= CORE_HW_AUTOCAL_ENA;
+	writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
+
+	/* Write 1 to TIMER_ENA field in CORE_CSR_CDC_CAL_TIMER_CFG0 */
+	config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
+	config |= CORE_TIMER_ENA;
+	writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
+
+	wmb(); /* drain writebuffer */
+
+	/* Poll on CALIBRATION_DONE field in CORE_CSR_CDC_STATUS0 to be 1 */
+	wait_cnt = 50;
+	while (!(readl_relaxed(host->ioaddr + CORE_CSR_CDC_STATUS0)
+			& CORE_CALIBRATION_DONE)) {
+		/* max. wait for 50us sec for CALIBRATION_DONE bit to be set */
+		if (--wait_cnt == 0) {
+			pr_err("%s: %s: CDC Calibration was not completed\n",
+				mmc_hostname(host->mmc), __func__);
+			ret = -ETIMEDOUT;
+			goto out;
+		}
+		/* wait for 1us before polling again */
+		udelay(1);
+	}
+
+	/* Verify CDC_ERROR_CODE field in CORE_CSR_CDC_STATUS0 is 0 */
+	ret = readl_relaxed(host->ioaddr + CORE_CSR_CDC_STATUS0)
+			& CORE_CDC_ERROR_CODE_MASK;
+	if (ret) {
+		pr_err("%s: %s: CDC Error Code %d\n",
+			mmc_hostname(host->mmc), __func__, ret);
+		ret = -EINVAL;
+		goto out;
+	}
+
+	/* Write 1 to START_CDC_TRAFFIC field in CORE_DDR200_CFG */
+	config = readl_relaxed(host->ioaddr + CORE_DDR_200_CFG);
+	config |= CORE_START_CDC_TRAFFIC;
+	writel_relaxed(config, host->ioaddr + CORE_DDR_200_CFG);
+out:
+	pr_debug("%s: Exit %s, ret:%d\n", mmc_hostname(host->mmc),
+			__func__, ret);
+	return ret;
+}
+
 static int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode)
 {
 	int tuning_seq_cnt = 3;

@@ -433,6 +593,8 @@ static int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode)
 	int rc;
 	struct mmc_host *mmc = host->mmc;
 	struct mmc_ios ios = host->mmc->ios;
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 
 	/*
 	 * Tuning is required for SDR104, HS200 and HS400 cards and

@@ -457,6 +619,7 @@ retry:
 		if (rc)
 			return rc;
 
+		msm_host->saved_tuning_phase = phase;
 		rc = mmc_send_tuning(mmc, opcode, NULL);
 		if (!rc) {
 			/* Tuning is successful at this tuning point */

@@ -492,6 +655,8 @@ retry:
 		rc = -EIO;
 	}
 
+	if (!rc)
+		msm_host->tuning_done = true;
 	return rc;
 }
 

@@ -565,6 +730,17 @@ static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host,
 	dev_dbg(mmc_dev(mmc), "%s: clock=%u uhs=%u ctrl_2=0x%x\n",
 		mmc_hostname(host->mmc), host->clock, uhs, ctrl_2);
 	sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
+
+	spin_unlock_irq(&host->lock);
+
+	/* CDCLP533 HW calibration is only required for HS400 mode*/
+	if (host->clock > CORE_FREQ_100MHZ &&
+	   msm_host->tuning_done && !msm_host->calibration_done &&
+	   (mmc->ios.timing == MMC_TIMING_MMC_HS400))
+		if (!sdhci_msm_cdclp533_calibration(host))
+			msm_host->calibration_done = true;
+
+	spin_lock_irq(&host->lock);
 }
 
 static void sdhci_msm_voltage_switch(struct sdhci_host *host)

drivers/mmc/host/sdhci-msm.c +1 -0

+
 	/* Setup SDCC bus voter clock. */
 	msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus");
 	if (!IS_ERR(msm_host->bus_clk)) {

Quoted 258 lines · Ritesh Harjani

From: Venkat Gopalakrishnan <[email protected]>

In HS400 mode a new RCLK is introduced on the interface for read data transfers. The eMMC5.0 device transmits the read data to the host with respect to rising and falling edges of RCLK. In order to ensure correct operation of read data transfers in HS400 mode, the incoming RX data needs to be sampled by delayed version of RCLK.

The CDCLP533 delay circuit shifts the RCLK by T/4. It needs to be initialized, configured and enabled once during HS400 mode switch and when operational voltage/clock is changed.

Signed-off-by Venkat Gopalakrishnan <[email protected]>

Signed-off-by Ritesh Harjani <[email protected]>

---
 drivers/mmc/host/sdhci-msm.c | 178 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 178 insertions(+)

drivers/mmc/host/sdhci-msm.c +176 -0

index 612fa82..dbf80a9c 100644
@@ -57,6 +57,7 @@
 #define CORE_DLL_PDN		BIT(29)
 #define CORE_DLL_RST		BIT(30)
 #define CORE_DLL_CONFIG		0x100
+#define CORE_CMD_DAT_TRACK_SEL	BIT(0)
 #define CORE_DLL_STATUS		0x108
 
 #define CORE_DLL_CONFIG_2	0x1b4

@@ -72,8 +73,36 @@
 #define CORE_HC_SELECT_IN_HS400	(6 << 19)
 #define CORE_HC_SELECT_IN_MASK	(7 << 19)
 
+#define CORE_CSR_CDC_CTLR_CFG0		0x130
+#define CORE_SW_TRIG_FULL_CALIB		BIT(16)
+#define CORE_HW_AUTOCAL_ENA		BIT(17)
+
+#define CORE_CSR_CDC_CTLR_CFG1		0x134
+#define CORE_CSR_CDC_CAL_TIMER_CFG0	0x138
+#define CORE_TIMER_ENA			BIT(16)
+
+#define CORE_CSR_CDC_CAL_TIMER_CFG1	0x13C
+#define CORE_CSR_CDC_REFCOUNT_CFG	0x140
+#define CORE_CSR_CDC_COARSE_CAL_CFG	0x144
+#define CORE_CDC_OFFSET_CFG		0x14C
+#define CORE_CSR_CDC_DELAY_CFG		0x150
+#define CORE_CDC_SLAVE_DDA_CFG		0x160
+#define CORE_CSR_CDC_STATUS0		0x164
+#define CORE_CALIBRATION_DONE		BIT(0)
+
+#define CORE_CDC_ERROR_CODE_MASK	0x7000000
+
+#define CORE_CSR_CDC_GEN_CFG		0x178
+#define CORE_CDC_SWITCH_BYPASS_OFF	BIT(0)
+#define CORE_CDC_SWITCH_RC_EN		BIT(1)
+
+#define CORE_DDR_200_CFG		0x184
+#define CORE_CDC_T4_DLY_SEL		BIT(0)
+#define CORE_START_CDC_TRAFFIC		BIT(6)
+
 #define CORE_VENDOR_SPEC_CAPABILITIES0	0x11c
 
+#define INVALID_TUNING_PHASE	-1
 #define TCXO_FREQ		19200000
 #define SDHCI_MSM_MIN_CLOCK	400000
 #define CORE_FREQ_100MHZ	(100 * 1000 * 1000)

@@ -97,6 +126,7 @@ struct sdhci_msm_host {
 	bool use_14lpp_dll_reset;
 	bool tuning_done;
 	bool calibration_done;
+	u8 saved_tuning_phase;
 };
 
 /* Platform specific tuning */

@@ -426,6 +456,136 @@ static int msm_init_cm_dll(struct sdhci_host *host)
 	return 0;
 }
 
+static int sdhci_msm_cdclp533_calibration(struct sdhci_host *host)
+{
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
+	u32 wait_cnt, config;
+	int ret;
+
+	pr_debug("%s: Enter %s\n", mmc_hostname(host->mmc), __func__);
+
+	/*
+	 * Retuning in HS400 (DDR mode) will fail, just reset the
+	 * tuning block and restore the saved tuning phase.
+	 */
+	ret = msm_init_cm_dll(host);
+	if (ret)
+		goto out;
+
+	/* Set the selected phase in delay line hw block */
+	ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase);
+	if (ret)
+		goto out;
+
+	/* Write 1 to CMD_DAT_TRACK_SEL field in DLL_CONFIG */
+	config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
+	config |= CORE_CMD_DAT_TRACK_SEL;
+	writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
+
+	/* Write 0 to CDC_T4_DLY_SEL field in VENDOR_SPEC_DDR200_CFG */
+	config = readl_relaxed(host->ioaddr + CORE_DDR_200_CFG);
+	config &= ~CORE_CDC_T4_DLY_SEL;
+	writel_relaxed(config, host->ioaddr + CORE_DDR_200_CFG);
+
+	/* Write 0 to CDC_SWITCH_BYPASS_OFF field in CORE_CSR_CDC_GEN_CFG */
+	config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
+	config &= ~CORE_CDC_SWITCH_BYPASS_OFF;
+	writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
+
+	/* Write 1 to CDC_SWITCH_RC_EN field in CORE_CSR_CDC_GEN_CFG */
+	config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
+	config |= CORE_CDC_SWITCH_RC_EN;
+	writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
+
+	/* Write 0 to START_CDC_TRAFFIC field in CORE_DDR200_CFG */
+	config = readl_relaxed(host->ioaddr + CORE_DDR_200_CFG);
+	config &= ~CORE_START_CDC_TRAFFIC;
+	writel_relaxed(config, host->ioaddr + CORE_DDR_200_CFG);
+
+	/*
+	 * Perform CDC Register Initialization Sequence
+	 *
+	 * CORE_CSR_CDC_CTLR_CFG0	0x11800EC
+	 * CORE_CSR_CDC_CTLR_CFG1	0x3011111
+	 * CORE_CSR_CDC_CAL_TIMER_CFG0	0x1201000
+	 * CORE_CSR_CDC_CAL_TIMER_CFG1	0x4
+	 * CORE_CSR_CDC_REFCOUNT_CFG	0xCB732020
+	 * CORE_CSR_CDC_COARSE_CAL_CFG	0xB19
+	 * CORE_CSR_CDC_DELAY_CFG	0x3AC
+	 * CORE_CDC_OFFSET_CFG		0x0
+	 * CORE_CDC_SLAVE_DDA_CFG	0x16334
+	 */
+
+	writel_relaxed(0x11800EC, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
+	writel_relaxed(0x3011111, host->ioaddr + CORE_CSR_CDC_CTLR_CFG1);
+	writel_relaxed(0x1201000, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
+	writel_relaxed(0x4, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG1);
+	writel_relaxed(0xCB732020, host->ioaddr + CORE_CSR_CDC_REFCOUNT_CFG);
+	writel_relaxed(0xB19, host->ioaddr + CORE_CSR_CDC_COARSE_CAL_CFG);
+	writel_relaxed(0x3AC, host->ioaddr + CORE_CSR_CDC_DELAY_CFG);
+	writel_relaxed(0x0, host->ioaddr + CORE_CDC_OFFSET_CFG);
+	writel_relaxed(0x16334, host->ioaddr + CORE_CDC_SLAVE_DDA_CFG);
+
+	/* CDC HW Calibration */
+
+	/* Write 1 to SW_TRIG_FULL_CALIB field in CORE_CSR_CDC_CTLR_CFG0 */
+	config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
+	config |= CORE_SW_TRIG_FULL_CALIB;
+	writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
+
+	/* Write 0 to SW_TRIG_FULL_CALIB field in CORE_CSR_CDC_CTLR_CFG0 */
+	config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
+	config &= ~CORE_SW_TRIG_FULL_CALIB;
+	writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
+
+	/* Write 1 to HW_AUTOCAL_ENA field in CORE_CSR_CDC_CTLR_CFG0 */
+	config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
+	config |= CORE_HW_AUTOCAL_ENA;
+	writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
+
+	/* Write 1 to TIMER_ENA field in CORE_CSR_CDC_CAL_TIMER_CFG0 */
+	config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
+	config |= CORE_TIMER_ENA;
+	writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
+
+	wmb(); /* drain writebuffer */
+
+	/* Poll on CALIBRATION_DONE field in CORE_CSR_CDC_STATUS0 to be 1 */
+	wait_cnt = 50;
+	while (!(readl_relaxed(host->ioaddr + CORE_CSR_CDC_STATUS0)
+			& CORE_CALIBRATION_DONE)) {
+		/* max. wait for 50us sec for CALIBRATION_DONE bit to be set */
+		if (--wait_cnt == 0) {
+			pr_err("%s: %s: CDC Calibration was not completed\n",
+				mmc_hostname(host->mmc), __func__);
+			ret = -ETIMEDOUT;
+			goto out;
+		}
+		/* wait for 1us before polling again */
+		udelay(1);
+	}
+
+	/* Verify CDC_ERROR_CODE field in CORE_CSR_CDC_STATUS0 is 0 */
+	ret = readl_relaxed(host->ioaddr + CORE_CSR_CDC_STATUS0)
+			& CORE_CDC_ERROR_CODE_MASK;
+	if (ret) {
+		pr_err("%s: %s: CDC Error Code %d\n",
+			mmc_hostname(host->mmc), __func__, ret);
+		ret = -EINVAL;
+		goto out;
+	}
+
+	/* Write 1 to START_CDC_TRAFFIC field in CORE_DDR200_CFG */
+	config = readl_relaxed(host->ioaddr + CORE_DDR_200_CFG);
+	config |= CORE_START_CDC_TRAFFIC;
+	writel_relaxed(config, host->ioaddr + CORE_DDR_200_CFG);
+out:
+	pr_debug("%s: Exit %s, ret:%d\n", mmc_hostname(host->mmc),
+			__func__, ret);
+	return ret;
+}
+
 static int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode)
 {
 	int tuning_seq_cnt = 3;

@@ -433,6 +593,8 @@ static int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode)
 	int rc;
 	struct mmc_host *mmc = host->mmc;
 	struct mmc_ios ios = host->mmc->ios;
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 
 	/*
 	 * Tuning is required for SDR104, HS200 and HS400 cards and

@@ -457,6 +619,7 @@ retry:
 		if (rc)
 			return rc;
 
+		msm_host->saved_tuning_phase = phase;
 		rc = mmc_send_tuning(mmc, opcode, NULL);
 		if (!rc) {
 			/* Tuning is successful at this tuning point */

@@ -492,6 +655,8 @@ retry:
 		rc = -EIO;
 	}
 
+	if (!rc)
+		msm_host->tuning_done = true;
 	return rc;
 }
 

@@ -565,6 +730,17 @@ static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host,
 	dev_dbg(mmc_dev(mmc), "%s: clock=%u uhs=%u ctrl_2=0x%x\n",
 		mmc_hostname(host->mmc), host->clock, uhs, ctrl_2);
 	sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
+
+	spin_unlock_irq(&host->lock);
+
+	/* CDCLP533 HW calibration is only required for HS400 mode*/
+	if (host->clock > CORE_FREQ_100MHZ &&
+	   msm_host->tuning_done && !msm_host->calibration_done &&
+	   (mmc->ios.timing == MMC_TIMING_MMC_HS400))
+		if (!sdhci_msm_cdclp533_calibration(host))
+			msm_host->calibration_done = true;
+
+	spin_lock_irq(&host->lock);
 }
 
 static void sdhci_msm_voltage_switch(struct sdhci_host *host)

@@ -907,6 +1083,8 @@ static int sdhci_msm_probe(struct platform_device *pdev)
 

drivers/mmc/host/sdhci-msm.c static int sdhci_msm_probe(struct platform_device *pdev) · line 1086

Quoted 3 lines

drivers/mmc/host/sdhci-msm.c +1 -0

 	sdhci_msm_populate_dt(&pdev->dev, msm_host);
 
+	msm_host->saved_tuning_phase = INVALID_TUNING_PHASE;

There is never a check for INVALID_TUNING_PHASE which begs the question: why have it?

drivers/mmc/host/sdhci-msm.c static int sdhci_msm_probe(struct platform_device *pdev) · line 1090

Quoted 6 lines

drivers/mmc/host/sdhci-msm.c +1 -0

+
 	/* Setup SDCC bus voter clock. */
 	msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus");
 	if (!IS_ERR(msm_host->bus_clk)) {

Hi Adrian,

Quoted 263 lines · Adrian Hunter

Quoted 262 lines · Ritesh Harjani

From: Venkat Gopalakrishnan <[email protected]>

In HS400 mode a new RCLK is introduced on the interface for read data transfers. The eMMC5.0 device transmits the read data to the host with respect to rising and falling edges of RCLK. In order to ensure correct operation of read data transfers in HS400 mode, the incoming RX data needs to be sampled by delayed version of RCLK.

The CDCLP533 delay circuit shifts the RCLK by T/4. It needs to be initialized, configured and enabled once during HS400 mode switch and when operational voltage/clock is changed.

Signed-off-by Venkat Gopalakrishnan <[email protected]>

Signed-off-by Ritesh Harjani <[email protected]>

---
 drivers/mmc/host/sdhci-msm.c | 178
+++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 178 insertions(+)

drivers/mmc/host/sdhci-msm.c +162 -0

index 612fa82..dbf80a9c 100644
@@ -57,6 +57,7 @@
 #define CORE_DLL_PDN        BIT(29)
 #define CORE_DLL_RST        BIT(30)
 #define CORE_DLL_CONFIG        0x100
+#define CORE_CMD_DAT_TRACK_SEL    BIT(0)
 #define CORE_DLL_STATUS        0x108
 
 #define CORE_DLL_CONFIG_2    0x1b4

@@ -72,8 +73,36 @@
 #define CORE_HC_SELECT_IN_HS400    (6 << 19)
 #define CORE_HC_SELECT_IN_MASK    (7 << 19)
 
+#define CORE_CSR_CDC_CTLR_CFG0        0x130
+#define CORE_SW_TRIG_FULL_CALIB        BIT(16)
+#define CORE_HW_AUTOCAL_ENA        BIT(17)
+
+#define CORE_CSR_CDC_CTLR_CFG1        0x134
+#define CORE_CSR_CDC_CAL_TIMER_CFG0    0x138
+#define CORE_TIMER_ENA            BIT(16)
+
+#define CORE_CSR_CDC_CAL_TIMER_CFG1    0x13C
+#define CORE_CSR_CDC_REFCOUNT_CFG    0x140
+#define CORE_CSR_CDC_COARSE_CAL_CFG    0x144
+#define CORE_CDC_OFFSET_CFG        0x14C
+#define CORE_CSR_CDC_DELAY_CFG        0x150
+#define CORE_CDC_SLAVE_DDA_CFG        0x160
+#define CORE_CSR_CDC_STATUS0        0x164
+#define CORE_CALIBRATION_DONE        BIT(0)
+
+#define CORE_CDC_ERROR_CODE_MASK    0x7000000
+
+#define CORE_CSR_CDC_GEN_CFG        0x178
+#define CORE_CDC_SWITCH_BYPASS_OFF    BIT(0)
+#define CORE_CDC_SWITCH_RC_EN        BIT(1)
+
+#define CORE_DDR_200_CFG        0x184
+#define CORE_CDC_T4_DLY_SEL        BIT(0)
+#define CORE_START_CDC_TRAFFIC        BIT(6)
+
 #define CORE_VENDOR_SPEC_CAPABILITIES0    0x11c
 
+#define INVALID_TUNING_PHASE    -1
 #define TCXO_FREQ        19200000
 #define SDHCI_MSM_MIN_CLOCK    400000
 #define CORE_FREQ_100MHZ    (100 * 1000 * 1000)

@@ -97,6 +126,7 @@ struct sdhci_msm_host {
     bool use_14lpp_dll_reset;
     bool tuning_done;
     bool calibration_done;
+    u8 saved_tuning_phase;
 };
 
 /* Platform specific tuning */

@@ -426,6 +456,136 @@ static int msm_init_cm_dll(struct sdhci_host *host)
     return 0;
 }
 
+static int sdhci_msm_cdclp533_calibration(struct sdhci_host *host)
+{
+    struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+    struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
+    u32 wait_cnt, config;
+    int ret;
+
+    pr_debug("%s: Enter %s\n", mmc_hostname(host->mmc), __func__);
+
+    /*
+     * Retuning in HS400 (DDR mode) will fail, just reset the
+     * tuning block and restore the saved tuning phase.
+     */
+    ret = msm_init_cm_dll(host);
+    if (ret)
+        goto out;
+
+    /* Set the selected phase in delay line hw block */
+    ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase);
+    if (ret)
+        goto out;
+
+    /* Write 1 to CMD_DAT_TRACK_SEL field in DLL_CONFIG */
+    config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
+    config |= CORE_CMD_DAT_TRACK_SEL;
+    writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
+
+    /* Write 0 to CDC_T4_DLY_SEL field in VENDOR_SPEC_DDR200_CFG */
+    config = readl_relaxed(host->ioaddr + CORE_DDR_200_CFG);
+    config &= ~CORE_CDC_T4_DLY_SEL;
+    writel_relaxed(config, host->ioaddr + CORE_DDR_200_CFG);
+
+    /* Write 0 to CDC_SWITCH_BYPASS_OFF field in CORE_CSR_CDC_GEN_CFG */
+    config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
+    config &= ~CORE_CDC_SWITCH_BYPASS_OFF;
+    writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
+
+    /* Write 1 to CDC_SWITCH_RC_EN field in CORE_CSR_CDC_GEN_CFG */
+    config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
+    config |= CORE_CDC_SWITCH_RC_EN;
+    writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
+
+    /* Write 0 to START_CDC_TRAFFIC field in CORE_DDR200_CFG */
+    config = readl_relaxed(host->ioaddr + CORE_DDR_200_CFG);
+    config &= ~CORE_START_CDC_TRAFFIC;
+    writel_relaxed(config, host->ioaddr + CORE_DDR_200_CFG);
+
+    /*
+     * Perform CDC Register Initialization Sequence
+     *
+     * CORE_CSR_CDC_CTLR_CFG0    0x11800EC
+     * CORE_CSR_CDC_CTLR_CFG1    0x3011111
+     * CORE_CSR_CDC_CAL_TIMER_CFG0    0x1201000
+     * CORE_CSR_CDC_CAL_TIMER_CFG1    0x4
+     * CORE_CSR_CDC_REFCOUNT_CFG    0xCB732020
+     * CORE_CSR_CDC_COARSE_CAL_CFG    0xB19
+     * CORE_CSR_CDC_DELAY_CFG    0x3AC
+     * CORE_CDC_OFFSET_CFG        0x0
+     * CORE_CDC_SLAVE_DDA_CFG    0x16334
+     */
+
+    writel_relaxed(0x11800EC, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
+    writel_relaxed(0x3011111, host->ioaddr + CORE_CSR_CDC_CTLR_CFG1);
+    writel_relaxed(0x1201000, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
+    writel_relaxed(0x4, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG1);
+    writel_relaxed(0xCB732020, host->ioaddr + CORE_CSR_CDC_REFCOUNT_CFG);
+    writel_relaxed(0xB19, host->ioaddr + CORE_CSR_CDC_COARSE_CAL_CFG);
+    writel_relaxed(0x3AC, host->ioaddr + CORE_CSR_CDC_DELAY_CFG);
+    writel_relaxed(0x0, host->ioaddr + CORE_CDC_OFFSET_CFG);
+    writel_relaxed(0x16334, host->ioaddr + CORE_CDC_SLAVE_DDA_CFG);
+
+    /* CDC HW Calibration */
+
+    /* Write 1 to SW_TRIG_FULL_CALIB field in CORE_CSR_CDC_CTLR_CFG0 */
+    config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
+    config |= CORE_SW_TRIG_FULL_CALIB;
+    writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
+
+    /* Write 0 to SW_TRIG_FULL_CALIB field in CORE_CSR_CDC_CTLR_CFG0 */
+    config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
+    config &= ~CORE_SW_TRIG_FULL_CALIB;
+    writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
+
+    /* Write 1 to HW_AUTOCAL_ENA field in CORE_CSR_CDC_CTLR_CFG0 */
+    config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
+    config |= CORE_HW_AUTOCAL_ENA;
+    writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
+
+    /* Write 1 to TIMER_ENA field in CORE_CSR_CDC_CAL_TIMER_CFG0 */
+    config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
+    config |= CORE_TIMER_ENA;
+    writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
+
+    wmb(); /* drain writebuffer */
+
+    /* Poll on CALIBRATION_DONE field in CORE_CSR_CDC_STATUS0 to be 1 */
+    wait_cnt = 50;
+    while (!(readl_relaxed(host->ioaddr + CORE_CSR_CDC_STATUS0)
+            & CORE_CALIBRATION_DONE)) {
+        /* max. wait for 50us sec for CALIBRATION_DONE bit to be set */
+        if (--wait_cnt == 0) {
+            pr_err("%s: %s: CDC Calibration was not completed\n",
+                mmc_hostname(host->mmc), __func__);
+            ret = -ETIMEDOUT;
+            goto out;
+        }
+        /* wait for 1us before polling again */
+        udelay(1);
+    }
+
+    /* Verify CDC_ERROR_CODE field in CORE_CSR_CDC_STATUS0 is 0 */
+    ret = readl_relaxed(host->ioaddr + CORE_CSR_CDC_STATUS0)
+            & CORE_CDC_ERROR_CODE_MASK;
+    if (ret) {
+        pr_err("%s: %s: CDC Error Code %d\n",
+            mmc_hostname(host->mmc), __func__, ret);
+        ret = -EINVAL;
+        goto out;
+    }
+
+    /* Write 1 to START_CDC_TRAFFIC field in CORE_DDR200_CFG */
+    config = readl_relaxed(host->ioaddr + CORE_DDR_200_CFG);
+    config |= CORE_START_CDC_TRAFFIC;
+    writel_relaxed(config, host->ioaddr + CORE_DDR_200_CFG);
+out:
+    pr_debug("%s: Exit %s, ret:%d\n", mmc_hostname(host->mmc),
+            __func__, ret);
+    return ret;
+}
+
 static int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode)
 {
     int tuning_seq_cnt = 3;

@@ -433,6 +593,8 @@ static int sdhci_msm_execute_tuning(struct sdhci_host
 *host, u32 opcode)
     int rc;
     struct mmc_host *mmc = host->mmc;
     struct mmc_ios ios = host->mmc->ios;
+    struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+    struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 
     /*

* Tuning is required for SDR104, HS200 and HS400 cards and

drivers/mmc/host/sdhci-msm.c +14 -0

@@ -457,6 +619,7 @@ retry:
         if (rc)
             return rc;
 
+        msm_host->saved_tuning_phase = phase;
         rc = mmc_send_tuning(mmc, opcode, NULL);
         if (!rc) {
             /* Tuning is successful at this tuning point */

@@ -492,6 +655,8 @@ retry:
         rc = -EIO;
     }
 
+    if (!rc)
+        msm_host->tuning_done = true;
     return rc;
 }
 

@@ -565,6 +730,17 @@ static void sdhci_msm_set_uhs_signaling(struct
 sdhci_host *host,
     dev_dbg(mmc_dev(mmc), "%s: clock=%u uhs=%u ctrl_2=0x%x\n",
         mmc_hostname(host->mmc), host->clock, uhs, ctrl_2);
     sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
+
+    spin_unlock_irq(&host->lock);
+
+    /* CDCLP533 HW calibration is only required for HS400 mode*/
+    if (host->clock > CORE_FREQ_100MHZ &&
+       msm_host->tuning_done && !msm_host->calibration_done &&
+       (mmc->ios.timing == MMC_TIMING_MMC_HS400))
+        if (!sdhci_msm_cdclp533_calibration(host))
+            msm_host->calibration_done = true;
+
+    spin_lock_irq(&host->lock);
 }
 

static void sdhci_msm_voltage_switch(struct sdhci_host *host)

drivers/mmc/host/sdhci-msm.c +0 -0

@@ -907,6 +1083,8 @@ static int sdhci_msm_probe(struct platform_device
 *pdev)
 

Quoted 6 lines

drivers/mmc/host/sdhci-msm.c static int sdhci_msm_probe(struct platform_device *pdev) · line 1086

Quoted 3 lines

drivers/mmc/host/sdhci-msm.c +1 -0

     sdhci_msm_populate_dt(&pdev->dev, msm_host);
 
+    msm_host->saved_tuning_phase = INVALID_TUNING_PHASE;

There is never a check for INVALID_TUNING_PHASE which begs the question: why have it?

phase value can be between 0x0 to 0xf. So during probe saved_tuning_phase is getting initialized with -1 value.

Let me know if any concern, we can remove it as well.
But wont it look incorrect if we initialize it with some valid phase value before even tuning is completed?

Quoted 8 lines

Quoted 7 lines

drivers/mmc/host/sdhci-msm.c +1 -0

+
     /* Setup SDCC bus voter clock. */
     msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus");

     if (!IS_ERR(msm_host->bus_clk)) {

Quoted 272 lines · Ritesh Harjani

Hi Adrian,

Quoted 263 lines · Adrian Hunter

Quoted 262 lines · Ritesh Harjani

From: Venkat Gopalakrishnan <[email protected]>

In HS400 mode a new RCLK is introduced on the interface for read data transfers. The eMMC5.0 device transmits the read data to the host with respect to rising and falling edges of RCLK. In order to ensure correct operation of read data transfers in HS400 mode, the incoming RX data needs to be sampled by delayed version of RCLK.

The CDCLP533 delay circuit shifts the RCLK by T/4. It needs to be initialized, configured and enabled once during HS400 mode switch and when operational voltage/clock is changed.

Signed-off-by Venkat Gopalakrishnan <[email protected]>

Signed-off-by Ritesh Harjani <[email protected]>

---
 drivers/mmc/host/sdhci-msm.c | 178
+++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 178 insertions(+)

drivers/mmc/host/sdhci-msm.c +162 -0

index 612fa82..dbf80a9c 100644
@@ -57,6 +57,7 @@
 #define CORE_DLL_PDN        BIT(29)
 #define CORE_DLL_RST        BIT(30)
 #define CORE_DLL_CONFIG        0x100
+#define CORE_CMD_DAT_TRACK_SEL    BIT(0)
 #define CORE_DLL_STATUS        0x108
 
 #define CORE_DLL_CONFIG_2    0x1b4

@@ -72,8 +73,36 @@
 #define CORE_HC_SELECT_IN_HS400    (6 << 19)
 #define CORE_HC_SELECT_IN_MASK    (7 << 19)
 
+#define CORE_CSR_CDC_CTLR_CFG0        0x130
+#define CORE_SW_TRIG_FULL_CALIB        BIT(16)
+#define CORE_HW_AUTOCAL_ENA        BIT(17)
+
+#define CORE_CSR_CDC_CTLR_CFG1        0x134
+#define CORE_CSR_CDC_CAL_TIMER_CFG0    0x138
+#define CORE_TIMER_ENA            BIT(16)
+
+#define CORE_CSR_CDC_CAL_TIMER_CFG1    0x13C
+#define CORE_CSR_CDC_REFCOUNT_CFG    0x140
+#define CORE_CSR_CDC_COARSE_CAL_CFG    0x144
+#define CORE_CDC_OFFSET_CFG        0x14C
+#define CORE_CSR_CDC_DELAY_CFG        0x150
+#define CORE_CDC_SLAVE_DDA_CFG        0x160
+#define CORE_CSR_CDC_STATUS0        0x164
+#define CORE_CALIBRATION_DONE        BIT(0)
+
+#define CORE_CDC_ERROR_CODE_MASK    0x7000000
+
+#define CORE_CSR_CDC_GEN_CFG        0x178
+#define CORE_CDC_SWITCH_BYPASS_OFF    BIT(0)
+#define CORE_CDC_SWITCH_RC_EN        BIT(1)
+
+#define CORE_DDR_200_CFG        0x184
+#define CORE_CDC_T4_DLY_SEL        BIT(0)
+#define CORE_START_CDC_TRAFFIC        BIT(6)
+
 #define CORE_VENDOR_SPEC_CAPABILITIES0    0x11c
 
+#define INVALID_TUNING_PHASE    -1
 #define TCXO_FREQ        19200000
 #define SDHCI_MSM_MIN_CLOCK    400000
 #define CORE_FREQ_100MHZ    (100 * 1000 * 1000)

@@ -97,6 +126,7 @@ struct sdhci_msm_host {
     bool use_14lpp_dll_reset;
     bool tuning_done;
     bool calibration_done;
+    u8 saved_tuning_phase;
 };
 
 /* Platform specific tuning */

@@ -426,6 +456,136 @@ static int msm_init_cm_dll(struct sdhci_host *host)
     return 0;
 }
 
+static int sdhci_msm_cdclp533_calibration(struct sdhci_host *host)
+{
+    struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+    struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
+    u32 wait_cnt, config;
+    int ret;
+
+    pr_debug("%s: Enter %s\n", mmc_hostname(host->mmc), __func__);
+
+    /*
+     * Retuning in HS400 (DDR mode) will fail, just reset the
+     * tuning block and restore the saved tuning phase.
+     */
+    ret = msm_init_cm_dll(host);
+    if (ret)
+        goto out;
+
+    /* Set the selected phase in delay line hw block */
+    ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase);
+    if (ret)
+        goto out;
+
+    /* Write 1 to CMD_DAT_TRACK_SEL field in DLL_CONFIG */
+    config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
+    config |= CORE_CMD_DAT_TRACK_SEL;
+    writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
+
+    /* Write 0 to CDC_T4_DLY_SEL field in VENDOR_SPEC_DDR200_CFG */
+    config = readl_relaxed(host->ioaddr + CORE_DDR_200_CFG);
+    config &= ~CORE_CDC_T4_DLY_SEL;
+    writel_relaxed(config, host->ioaddr + CORE_DDR_200_CFG);
+
+    /* Write 0 to CDC_SWITCH_BYPASS_OFF field in CORE_CSR_CDC_GEN_CFG */
+    config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
+    config &= ~CORE_CDC_SWITCH_BYPASS_OFF;
+    writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
+
+    /* Write 1 to CDC_SWITCH_RC_EN field in CORE_CSR_CDC_GEN_CFG */
+    config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
+    config |= CORE_CDC_SWITCH_RC_EN;
+    writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
+
+    /* Write 0 to START_CDC_TRAFFIC field in CORE_DDR200_CFG */
+    config = readl_relaxed(host->ioaddr + CORE_DDR_200_CFG);
+    config &= ~CORE_START_CDC_TRAFFIC;
+    writel_relaxed(config, host->ioaddr + CORE_DDR_200_CFG);
+
+    /*
+     * Perform CDC Register Initialization Sequence
+     *
+     * CORE_CSR_CDC_CTLR_CFG0    0x11800EC
+     * CORE_CSR_CDC_CTLR_CFG1    0x3011111
+     * CORE_CSR_CDC_CAL_TIMER_CFG0    0x1201000
+     * CORE_CSR_CDC_CAL_TIMER_CFG1    0x4
+     * CORE_CSR_CDC_REFCOUNT_CFG    0xCB732020
+     * CORE_CSR_CDC_COARSE_CAL_CFG    0xB19
+     * CORE_CSR_CDC_DELAY_CFG    0x3AC
+     * CORE_CDC_OFFSET_CFG        0x0
+     * CORE_CDC_SLAVE_DDA_CFG    0x16334
+     */
+
+    writel_relaxed(0x11800EC, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
+    writel_relaxed(0x3011111, host->ioaddr + CORE_CSR_CDC_CTLR_CFG1);
+    writel_relaxed(0x1201000, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
+    writel_relaxed(0x4, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG1);
+    writel_relaxed(0xCB732020, host->ioaddr + CORE_CSR_CDC_REFCOUNT_CFG);
+    writel_relaxed(0xB19, host->ioaddr + CORE_CSR_CDC_COARSE_CAL_CFG);
+    writel_relaxed(0x3AC, host->ioaddr + CORE_CSR_CDC_DELAY_CFG);
+    writel_relaxed(0x0, host->ioaddr + CORE_CDC_OFFSET_CFG);
+    writel_relaxed(0x16334, host->ioaddr + CORE_CDC_SLAVE_DDA_CFG);
+
+    /* CDC HW Calibration */
+
+    /* Write 1 to SW_TRIG_FULL_CALIB field in CORE_CSR_CDC_CTLR_CFG0 */
+    config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
+    config |= CORE_SW_TRIG_FULL_CALIB;
+    writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
+
+    /* Write 0 to SW_TRIG_FULL_CALIB field in CORE_CSR_CDC_CTLR_CFG0 */
+    config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
+    config &= ~CORE_SW_TRIG_FULL_CALIB;
+    writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
+
+    /* Write 1 to HW_AUTOCAL_ENA field in CORE_CSR_CDC_CTLR_CFG0 */
+    config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
+    config |= CORE_HW_AUTOCAL_ENA;
+    writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
+
+    /* Write 1 to TIMER_ENA field in CORE_CSR_CDC_CAL_TIMER_CFG0 */
+    config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
+    config |= CORE_TIMER_ENA;
+    writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
+
+    wmb(); /* drain writebuffer */
+
+    /* Poll on CALIBRATION_DONE field in CORE_CSR_CDC_STATUS0 to be 1 */
+    wait_cnt = 50;
+    while (!(readl_relaxed(host->ioaddr + CORE_CSR_CDC_STATUS0)
+            & CORE_CALIBRATION_DONE)) {
+        /* max. wait for 50us sec for CALIBRATION_DONE bit to be set */
+        if (--wait_cnt == 0) {
+            pr_err("%s: %s: CDC Calibration was not completed\n",
+                mmc_hostname(host->mmc), __func__);
+            ret = -ETIMEDOUT;
+            goto out;
+        }
+        /* wait for 1us before polling again */
+        udelay(1);
+    }
+
+    /* Verify CDC_ERROR_CODE field in CORE_CSR_CDC_STATUS0 is 0 */
+    ret = readl_relaxed(host->ioaddr + CORE_CSR_CDC_STATUS0)
+            & CORE_CDC_ERROR_CODE_MASK;
+    if (ret) {
+        pr_err("%s: %s: CDC Error Code %d\n",
+            mmc_hostname(host->mmc), __func__, ret);
+        ret = -EINVAL;
+        goto out;
+    }
+
+    /* Write 1 to START_CDC_TRAFFIC field in CORE_DDR200_CFG */
+    config = readl_relaxed(host->ioaddr + CORE_DDR_200_CFG);
+    config |= CORE_START_CDC_TRAFFIC;
+    writel_relaxed(config, host->ioaddr + CORE_DDR_200_CFG);
+out:
+    pr_debug("%s: Exit %s, ret:%d\n", mmc_hostname(host->mmc),
+            __func__, ret);
+    return ret;
+}
+
 static int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode)
 {
     int tuning_seq_cnt = 3;

@@ -433,6 +593,8 @@ static int sdhci_msm_execute_tuning(struct sdhci_host
 *host, u32 opcode)
     int rc;
     struct mmc_host *mmc = host->mmc;
     struct mmc_ios ios = host->mmc->ios;
+    struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+    struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 
     /*

* Tuning is required for SDR104, HS200 and HS400 cards and

drivers/mmc/host/sdhci-msm.c +14 -0

@@ -457,6 +619,7 @@ retry:
         if (rc)
             return rc;
 
+        msm_host->saved_tuning_phase = phase;
         rc = mmc_send_tuning(mmc, opcode, NULL);
         if (!rc) {
             /* Tuning is successful at this tuning point */

@@ -492,6 +655,8 @@ retry:
         rc = -EIO;
     }
 
+    if (!rc)
+        msm_host->tuning_done = true;
     return rc;
 }
 

@@ -565,6 +730,17 @@ static void sdhci_msm_set_uhs_signaling(struct
 sdhci_host *host,
     dev_dbg(mmc_dev(mmc), "%s: clock=%u uhs=%u ctrl_2=0x%x\n",
         mmc_hostname(host->mmc), host->clock, uhs, ctrl_2);
     sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
+
+    spin_unlock_irq(&host->lock);
+
+    /* CDCLP533 HW calibration is only required for HS400 mode*/
+    if (host->clock > CORE_FREQ_100MHZ &&
+       msm_host->tuning_done && !msm_host->calibration_done &&
+       (mmc->ios.timing == MMC_TIMING_MMC_HS400))
+        if (!sdhci_msm_cdclp533_calibration(host))
+            msm_host->calibration_done = true;
+
+    spin_lock_irq(&host->lock);
 }
 

static void sdhci_msm_voltage_switch(struct sdhci_host *host)

drivers/mmc/host/sdhci-msm.c +0 -0

@@ -907,6 +1083,8 @@ static int sdhci_msm_probe(struct platform_device
 *pdev)
 

Quoted 6 lines

drivers/mmc/host/sdhci-msm.c static int sdhci_msm_probe(struct platform_device *pdev) · line 1086

Quoted 3 lines

drivers/mmc/host/sdhci-msm.c +1 -0

     sdhci_msm_populate_dt(&pdev->dev, msm_host);
 
+    msm_host->saved_tuning_phase = INVALID_TUNING_PHASE;

There is never a check for INVALID_TUNING_PHASE which begs the question: why have it?

Quoted 6 lines

phase value can be between 0x0 to 0xf. So during probe saved_tuning_phase is getting initialized with -1 value.

Let me know if any concern, we can remove it as well.
But wont it look incorrect if we initialize it with some valid phase value before even tuning is completed?

INVALID_TUNING_PHASE is fine, I would just expect it be checked e.g. in msm_config_cm_dll_phase

	if (phase > 0xf)
		return -EINVAL;

Quoted 10 lines

Quoted 9 lines

Quoted 8 lines

drivers/mmc/host/sdhci-msm.c +1 -0

+
     /* Setup SDCC bus voter clock. */
     msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus");

     if (!IS_ERR(msm_host->bus_clk)) {

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This adds support for sdhc-msm controllers to get supported clk-rates from DT. sdhci-msm would need it's own set_clock ops to be implemented. For this, supported clk-rates needs to be populated in sdhci_msm_pltfm_data.

Signed-off-by Ritesh Harjani <[email protected]>

---
 .../devicetree/bindings/mmc/sdhci-msm.txt          |  1 +
 drivers/mmc/host/sdhci-msm.c                       | 48 ++++++++++++++++++++++
 2 files changed, 49 insertions(+)

Documentation/devicetree/bindings/mmc/sdhci-msm.txt +1 -0

index 485483a..6a83b38 100644
@@ -17,6 +17,7 @@ Required properties:
 	"iface" - Main peripheral bus clock (PCLK/HCLK - AHB Bus clock) (required)
 	"core"	- SDC MMC clock (MCLK) (required)
 	"bus"	- SDCC bus voter clock (optional)
+- clk-rates: Array of supported GCC clock frequencies for sdhc, Units - Hz.
 
 Example:
 

drivers/mmc/host/sdhci-msm.c +2 -0

index 85ddaae..042ecb2 100644
@@ -81,6 +81,8 @@ struct sdhci_msm_host {
 	struct clk *clk;	/* main SD/MMC bus clock */
 	struct clk *pclk;	/* SDHC peripheral bus clock */
 	struct clk *bus_clk;	/* SDHC bus voter clock */
+	u32 *clk_table;
+	int clk_table_sz;
 	struct mmc_host *mmc;
 	bool use_14lpp_dll_reset;
 };

drivers/mmc/host/sdhci-msm.c +4 -0

+	if (count < 0) {
+		dev_warn(dev, "%s: Invalid dt property, err(%d)\n",
+				prop_name, count);
+		return count;

drivers/mmc/host/sdhci-msm.c +14 -0

+{
+	int table_sz = 0;
+	u32 *table = NULL;
+
+	if (sdhci_msm_dt_get_array(dev, "clk-rates", &table, &table_sz)) {
+		dev_warn(dev, "failed in DT parsing for supported clk-rates\n");
+		return;
+	}
+	msm_host->clk_table = table;
+	msm_host->clk_table_sz = table_sz;
+}
+
 static int sdhci_msm_probe(struct platform_device *pdev)
 {
 	struct sdhci_host *host;

@@ -608,6 +654,8 @@ static int sdhci_msm_probe(struct platform_device *pdev)
 
 	sdhci_get_of_property(pdev);
 
+	sdhci_msm_populate_dt(&pdev->dev, msm_host);
+
 	/* Setup SDCC bus voter clock. */
 	msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus");
 	if (!IS_ERR(msm_host->bus_clk)) {

Quoted 40 lines · Ritesh Harjani

This adds support for sdhc-msm controllers to get supported clk-rates from DT. sdhci-msm would need it's own set_clock ops to be implemented. For this, supported clk-rates needs to be populated in sdhci_msm_pltfm_data.

Signed-off-by Ritesh Harjani <[email protected]>

---
 .../devicetree/bindings/mmc/sdhci-msm.txt          |  1 +
 drivers/mmc/host/sdhci-msm.c                       | 48 ++++++++++++++++++++++
 2 files changed, 49 insertions(+)

Documentation/devicetree/bindings/mmc/sdhci-msm.txt +1 -0

index 485483a..6a83b38 100644
@@ -17,6 +17,7 @@ Required properties:
 	"iface" - Main peripheral bus clock (PCLK/HCLK - AHB Bus clock) (required)
 	"core"	- SDC MMC clock (MCLK) (required)
 	"bus"	- SDCC bus voter clock (optional)
+- clk-rates: Array of supported GCC clock frequencies for sdhc, Units - Hz.
 
 Example:
 

drivers/mmc/host/sdhci-msm.c +2 -0

index 85ddaae..042ecb2 100644
@@ -81,6 +81,8 @@ struct sdhci_msm_host {
 	struct clk *clk;	/* main SD/MMC bus clock */
 	struct clk *pclk;	/* SDHC peripheral bus clock */
 	struct clk *bus_clk;	/* SDHC bus voter clock */
+	u32 *clk_table;
+	int clk_table_sz;
 	struct mmc_host *mmc;
 	bool use_14lpp_dll_reset;
 };

@@ -582,6 +584,50 @@ static const struct sdhci_pltfm_data sdhci_msm_pdata = {
 	.ops = &sdhci_msm_ops,
 };
 

drivers/mmc/host/sdhci-msm.c static const struct sdhci_pltfm_data sdhci_msm_pdata = { · line 588

Quoted 2 lines

drivers/mmc/host/sdhci-msm.c +2 -0

+static int sdhci_msm_dt_get_array(struct device *dev, const char *prop_name,
+				u32 **table, int *size)

It is nice to align to the open parenthesis. Have a look at the checks from checkpatch --strict

drivers/mmc/host/sdhci-msm.c static const struct sdhci_pltfm_data sdhci_msm_pdata = { · line 594

Quoted 7 lines

drivers/mmc/host/sdhci-msm.c +6 -0

+{
+	struct device_node *np = dev->of_node;
+	int count, ret;
+	u32 *arr;
+
+	count = of_property_count_elems_of_size(np, prop_name, sizeof(u32));

Shouldn't this be of_property_count_u32_elems()

drivers/mmc/host/sdhci-msm.c static const struct sdhci_pltfm_data sdhci_msm_pdata = { · line 595

Quoted 2 lines

drivers/mmc/host/sdhci-msm.c +1 -0

+	if (count < 0) {

Quoted 8 lines

drivers/mmc/host/sdhci-msm.c +8 -0

+		dev_warn(dev, "%s: Invalid dt property, err(%d)\n",
+				prop_name, count);
+		return count;
+	}
+
+	arr = kcalloc(count, sizeof(*arr), GFP_KERNEL);
+	if (!arr)
+		return -ENOMEM;

drivers/mmc/host/sdhci-msm.c static const struct sdhci_pltfm_data sdhci_msm_pdata = { · line 608

Quoted 5 lines

drivers/mmc/host/sdhci-msm.c +5 -0

+
+	ret = of_property_read_u32_array(np, prop_name, arr, count);
+	if (ret) {
+		kfree(arr);
+		dev_warn(dev, "%s Invalid dt array property, err(%d)\n",

'err(%d)' is an unusual style for printing error numbers. 'error %d' looks better.

Also in some messages you have 'DT' and others 'dt'. Also here it is '%s' but above '%s:', and some messages start with a lower case letter and some upper case. Please try to make everything consistent.

Quoted 4 lines

drivers/mmc/host/sdhci-msm.c +4 -0

+				prop_name, ret);
+		return ret;
+	}
+	*table = arr;

drivers/mmc/host/sdhci-msm.c static const struct sdhci_pltfm_data sdhci_msm_pdata = { · line 618

Quoted 6 lines

drivers/mmc/host/sdhci-msm.c +6 -0

+	*size = count;
+	return 0;
+}
+
+void sdhci_msm_populate_dt(struct device *dev,
+						struct sdhci_msm_host *msm_host)

Align to open parenthesis

Quoted 20 lines

drivers/mmc/host/sdhci-msm.c +12 -0

+{
+	int table_sz = 0;
+	u32 *table = NULL;
+
+	if (sdhci_msm_dt_get_array(dev, "clk-rates", &table, &table_sz)) {
+		dev_warn(dev, "failed in DT parsing for supported clk-rates\n");
+		return;
+	}
+	msm_host->clk_table = table;
+	msm_host->clk_table_sz = table_sz;
+}
+
 static int sdhci_msm_probe(struct platform_device *pdev)
 {
 	struct sdhci_host *host;

@@ -608,6 +654,8 @@ static int sdhci_msm_probe(struct platform_device *pdev)
 
 	sdhci_get_of_property(pdev);
 

drivers/mmc/host/sdhci-msm.c static int sdhci_msm_probe(struct platform_device *pdev) · line 661

Quoted 6 lines

drivers/mmc/host/sdhci-msm.c +2 -0

+	sdhci_msm_populate_dt(&pdev->dev, msm_host);
+
 	/* Setup SDCC bus voter clock. */
 	msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus");
 	if (!IS_ERR(msm_host->bus_clk)) {

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This adds support for sdhc-msm controllers to get supported clk-rates from DT. sdhci-msm would need it's own set_clock ops to be implemented. For this, supported clk-rates needs to be populated in sdhci_msm_pltfm_data.

Signed-off-by Ritesh Harjani <[email protected]>

---
 .../devicetree/bindings/mmc/sdhci-msm.txt          |  1 +
 drivers/mmc/host/sdhci-msm.c                       | 48 ++++++++++++++++++++++
 2 files changed, 49 insertions(+)

Documentation/devicetree/bindings/mmc/sdhci-msm.txt +0 -0

index 485483a..6a83b38 100644

Quoted 11 lines · Ritesh Harjani

This adds support for sdhc-msm controllers to get supported clk-rates from DT. sdhci-msm would need it's own set_clock ops to be implemented. For this, supported clk-rates needs to be populated in sdhci_msm_pltfm_data.

Signed-off-by Ritesh Harjani <[email protected]>

---
 .../devicetree/bindings/mmc/sdhci-msm.txt          |  1 +
 drivers/mmc/host/sdhci-msm.c                       | 48 ++++++++++++++++++++++
 2 files changed, 49 insertions(+)

Documentation/devicetree/bindings/mmc/sdhci-msm.txt Required properties: · line 20

Quoted 9 lines

Documentation/devicetree/bindings/mmc/sdhci-msm.txt +1 -0

index 485483a..6a83b38 100644
@@ -17,6 +17,7 @@ Required properties:
 	"iface" - Main peripheral bus clock (PCLK/HCLK - AHB Bus clock) (required)
 	"core"	- SDC MMC clock (MCLK) (required)
 	"bus"	- SDCC bus voter clock (optional)
+- clk-rates: Array of supported GCC clock frequencies for sdhc, Units - Hz.

Why can't some combination of assigned-clock-rates and querying the clock provider for rates be used here?

Minimally this would need unit suffix and either be made common or have a vendor prefix.

Rob
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Hi Rob,

Thanks for review.

Quoted 15 lines · Rob Herring

Quoted 13 lines · Ritesh Harjani

This adds support for sdhc-msm controllers to get supported clk-rates from DT. sdhci-msm would need it's own set_clock ops to be implemented. For this, supported clk-rates needs to be populated in sdhci_msm_pltfm_data.

Signed-off-by Ritesh Harjani <[email protected]>

---
 .../devicetree/bindings/mmc/sdhci-msm.txt          |  1 +
 drivers/mmc/host/sdhci-msm.c                       | 48
++++++++++++++++++++++
 2 files changed, 49 insertions(+)

Quoted 16 lines

Quoted 11 lines

Documentation/devicetree/bindings/mmc/sdhci-msm.txt +1 -0

index 485483a..6a83b38 100644
@@ -17,6 +17,7 @@ Required properties:
        "iface" - Main peripheral bus clock (PCLK/HCLK - AHB Bus clock)
 (required)
        "core"  - SDC MMC clock (MCLK) (required)
        "bus"   - SDCC bus voter clock (optional)
+- clk-rates: Array of supported GCC clock frequencies for sdhc, Units -

Quoted 1 line

Hz.

Why can't some combination of assigned-clock-rates and querying the clock provider for rates be used here?

From what I understood, assigned-clock-rates would only work for setting some default clock rates for certain clocks by calling of_clk_set_defaults.

Whereas the requirement here is -
That since SDHC msm directly controls the clk(core clock) at source, it's sdhci-msm driver needs to know the supported clk-rates by the underlying platform to configure the nearest floor value supported on this platform (when the request arrives from the core layer to switch the clock).

Hence the table of clk-rates is provided for sdhci-msm.

Quoted 3 lines

Minimally this would need unit suffix and either be made common or have a vendor prefix.

Sure will this work in that case - "qcom-clk-rates"

Quoted 41 lines · Ritesh Harjani

Hi Rob,

Thanks for review.

Quoted 15 lines · Rob Herring

Quoted 13 lines · Ritesh Harjani

This adds support for sdhc-msm controllers to get supported clk-rates from DT. sdhci-msm would need it's own set_clock ops to be implemented. For this, supported clk-rates needs to be populated in sdhci_msm_pltfm_data.

Signed-off-by Ritesh Harjani <[email protected]>

---
 .../devicetree/bindings/mmc/sdhci-msm.txt          |  1 +
 drivers/mmc/host/sdhci-msm.c                       | 48
++++++++++++++++++++++
 2 files changed, 49 insertions(+)

Quoted 16 lines

Quoted 11 lines

Documentation/devicetree/bindings/mmc/sdhci-msm.txt +1 -0

index 485483a..6a83b38 100644
@@ -17,6 +17,7 @@ Required properties:
        "iface" - Main peripheral bus clock (PCLK/HCLK - AHB Bus clock)
 (required)
        "core"  - SDC MMC clock (MCLK) (required)
        "bus"   - SDCC bus voter clock (optional)
+- clk-rates: Array of supported GCC clock frequencies for sdhc, Units -

Quoted 1 line

Hz.

Why can't some combination of assigned-clock-rates and querying the clock provider for rates be used here?

From what I understood, assigned-clock-rates would only work for setting some default clock rates for certain clocks by calling of_clk_set_defaults.

Quoted 5 lines

Whereas the requirement here is -
That since SDHC msm directly controls the clk(core clock) at source, it's sdhci-msm driver needs to know the supported clk-rates by the underlying platform to configure the nearest floor value supported on this platform (when the request arrives from the core layer to switch the clock).

Why does clk_round_rate not work for you? That will round down to the nearest frequency supported.

Quoted 8 lines

Hence the table of clk-rates is provided for sdhci-msm.

Quoted 3 lines

Minimally this would need unit suffix and either be made common or have a vendor prefix.

Sure will this work in that case - "qcom-clk-rates"

"qcom,clk-rates", but I'm not yet convinced this is right.

Rob
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Hi Rob

Quoted 57 lines · Rob Herring

Quoted 52 lines · Ritesh Harjani

Hi Rob,

Thanks for review.

Quoted 27 lines · Rob Herring

Quoted 24 lines · Ritesh Harjani

This adds support for sdhc-msm controllers to get supported clk-rates from DT. sdhci-msm would need it's own set_clock ops to be implemented. For this, supported clk-rates needs to be populated in sdhci_msm_pltfm_data.

Signed-off-by Ritesh Harjani <[email protected]>

---
 .../devicetree/bindings/mmc/sdhci-msm.txt          |  1 +
 drivers/mmc/host/sdhci-msm.c                       | 48
++++++++++++++++++++++
 2 files changed, 49 insertions(+)

Documentation/devicetree/bindings/mmc/sdhci-msm.txt +0 -0

index 485483a..6a83b38 100644
@@ -17,6 +17,7 @@ Required properties:
        "iface" - Main peripheral bus clock (PCLK/HCLK - AHB Bus clock)
 (required)
        "core"  - SDC MMC clock (MCLK) (required)
        "bus"   - SDCC bus voter clock (optional)

Quoted 8 lines

Quoted 3 lines

Documentation/devicetree/bindings/mmc/sdhci-msm.txt +1 -1

+- clk-rates: Array of supported GCC clock frequencies for sdhc, Units
-

Hz.

Why can't some combination of assigned-clock-rates and querying the clock provider for rates be used here?

From what I understood, assigned-clock-rates would only work for setting some default clock rates for certain clocks by calling of_clk_set_defaults.

Whereas the requirement here is -
That since SDHC msm directly controls the clk(core clock) at source, it's sdhci-msm driver needs to know the supported clk-rates by the underlying platform to configure the nearest floor value supported on this platform (when the request arrives from the core layer to switch the clock).

Quoted 2 lines

Why does clk_round_rate not work for you? That will round down to the nearest frequency supported.

clk_round_rate will round off to nearest supported "ceil" frequency. But we require nearest rounded off "floor" frequency.

Quoted 61 lines · Ritesh Harjani

Hi Rob

Quoted 57 lines · Rob Herring

Quoted 52 lines · Ritesh Harjani

Hi Rob,

Thanks for review.

Quoted 27 lines · Rob Herring

Quoted 24 lines · Ritesh Harjani

This adds support for sdhc-msm controllers to get supported clk-rates from DT. sdhci-msm would need it's own set_clock ops to be implemented. For this, supported clk-rates needs to be populated in sdhci_msm_pltfm_data.

Signed-off-by Ritesh Harjani <[email protected]>

---
 .../devicetree/bindings/mmc/sdhci-msm.txt          |  1 +
 drivers/mmc/host/sdhci-msm.c                       | 48
++++++++++++++++++++++
 2 files changed, 49 insertions(+)

Documentation/devicetree/bindings/mmc/sdhci-msm.txt +0 -0

index 485483a..6a83b38 100644
@@ -17,6 +17,7 @@ Required properties:
        "iface" - Main peripheral bus clock (PCLK/HCLK - AHB Bus clock)
 (required)
        "core"  - SDC MMC clock (MCLK) (required)
        "bus"   - SDCC bus voter clock (optional)

Quoted 8 lines

Quoted 3 lines

Documentation/devicetree/bindings/mmc/sdhci-msm.txt +1 -1

+- clk-rates: Array of supported GCC clock frequencies for sdhc, Units
-

Hz.

Why can't some combination of assigned-clock-rates and querying the clock provider for rates be used here?

From what I understood, assigned-clock-rates would only work for setting some default clock rates for certain clocks by calling of_clk_set_defaults.

Whereas the requirement here is -
That since SDHC msm directly controls the clk(core clock) at source, it's sdhci-msm driver needs to know the supported clk-rates by the underlying platform to configure the nearest floor value supported on this platform (when the request arrives from the core layer to switch the clock).

Quoted 5 lines

Quoted 2 lines

Why does clk_round_rate not work for you? That will round down to the nearest frequency supported.

clk_round_rate will round off to nearest supported "ceil" frequency. But we require nearest rounded off "floor" frequency.

Then fix the clk framework to do what you want. This doesn't need to be in DT.

Rob
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This add get_min_clock() and get_max_clock() callback for sdhci-msm. sdhci-msm min/max clocks may be different hence implement these callbacks.

Signed-off-by Sahitya Tummala <[email protected]>

Signed-off-by Ritesh Harjani <[email protected]>

---
 drivers/mmc/host/sdhci-msm.c | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

drivers/mmc/host/sdhci-msm.c +1 -0

index 042ecb2..4e17201 100644
@@ -68,6 +68,7 @@
 #define CORE_VENDOR_SPEC_CAPABILITIES0	0x11c
 
 #define TCXO_FREQ		19200000
+#define SDHCI_MSM_MIN_CLOCK	400000
 
 #define CDR_SELEXT_SHIFT	20
 #define CDR_SELEXT_MASK		(0xf << CDR_SELEXT_SHIFT)

drivers/mmc/host/sdhci-msm.c +6 -0

+		return SDHCI_MSM_MIN_CLOCK;
+	}
+}
+
 static const struct of_device_id sdhci_msm_dt_match[] = {
 	{ .compatible = "qcom,sdhci-msm-v4" },
 	{},

@@ -572,6 +599,8 @@ static const struct sdhci_ops sdhci_msm_ops = {
 	.platform_execute_tuning = sdhci_msm_execute_tuning,
 	.reset = sdhci_reset,
 	.set_clock = sdhci_set_clock,
+	.get_min_clock = sdhci_msm_get_min_clock,
+	.get_max_clock = sdhci_msm_get_max_clock,
 	.set_bus_width = sdhci_set_bus_width,
 	.set_uhs_signaling = sdhci_msm_set_uhs_signaling,
 	.voltage_switch = sdhci_msm_voltage_switch,

Quoted 26 lines · Ritesh Harjani

This add get_min_clock() and get_max_clock() callback for sdhci-msm. sdhci-msm min/max clocks may be different hence implement these callbacks.

Signed-off-by Sahitya Tummala <[email protected]>

Signed-off-by Ritesh Harjani <[email protected]>

---
 drivers/mmc/host/sdhci-msm.c | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

drivers/mmc/host/sdhci-msm.c +1 -0

index 042ecb2..4e17201 100644
@@ -68,6 +68,7 @@
 #define CORE_VENDOR_SPEC_CAPABILITIES0	0x11c
 
 #define TCXO_FREQ		19200000
+#define SDHCI_MSM_MIN_CLOCK	400000
 
 #define CDR_SELEXT_SHIFT	20
 #define CDR_SELEXT_MASK		(0xf << CDR_SELEXT_SHIFT)

@@ -561,6 +562,32 @@ static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data)
 	return IRQ_HANDLED;
 }
 

drivers/mmc/host/sdhci-msm.c static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data) · line 571

Quoted 7 lines

drivers/mmc/host/sdhci-msm.c +7 -0

+static unsigned int sdhci_msm_get_max_clock(struct sdhci_host *host)
+{
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
+	int count;
+
+	if (msm_host->clk_table) {

I don't know if DT allows empty arrays, but if it does, might not msm_host->clk_table_sz be zero here.

drivers/mmc/host/sdhci-msm.c static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data) · line 574

Quoted 4 lines

drivers/mmc/host/sdhci-msm.c +3 -0

+		count = msm_host->clk_table_sz;
+		return msm_host->clk_table[count - 1];
+	} else {

'else' is redundant here.

drivers/mmc/host/sdhci-msm.c static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data) · line 584

Quoted 11 lines

drivers/mmc/host/sdhci-msm.c +10 -0

+		return clk_round_rate(msm_host->clk, ULONG_MAX);
+	}
+}
+
+static unsigned int sdhci_msm_get_min_clock(struct sdhci_host *host)
+{
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
+
+	if (msm_host->clk_table) {

Same about possibility of msm_host->clk_table_sz being zero.

drivers/mmc/host/sdhci-msm.c static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data) · line 586

Quoted 3 lines

drivers/mmc/host/sdhci-msm.c +2 -0

+		return msm_host->clk_table[0];
+	} else {

'else' is redundant here.

Quoted 10 lines

drivers/mmc/host/sdhci-msm.c +4 -0

+		return SDHCI_MSM_MIN_CLOCK;
+	}
+}
+
 static const struct of_device_id sdhci_msm_dt_match[] = {
 	{ .compatible = "qcom,sdhci-msm-v4" },
 	{},

drivers/mmc/host/sdhci-msm.c static const struct sdhci_ops sdhci_msm_ops = { · line 606

Quoted 8 lines

drivers/mmc/host/sdhci-msm.c +2 -0

@@ -572,6 +599,8 @@ static const struct sdhci_ops sdhci_msm_ops = {
 	.platform_execute_tuning = sdhci_msm_execute_tuning,
 	.reset = sdhci_reset,
 	.set_clock = sdhci_set_clock,
+	.get_min_clock = sdhci_msm_get_min_clock,
+	.get_max_clock = sdhci_msm_get_max_clock,
 	.set_bus_width = sdhci_set_bus_width,
 	.set_uhs_signaling = sdhci_msm_set_uhs_signaling,
 	.voltage_switch = sdhci_msm_voltage_switch,

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