perf: honouring the cpuid for number of fixed counters in hypervisors
Subsystems (2)
RFC PATCH 1/1 perf: honouring the cpuid for number of fixed counters in hypervisors
From: Imre Palik <[email protected]>
perf doesn't seem to honour the number of fixed counters specified by cpuid leaf 0xa. It always assume that Intel CPUs have at least 3 fixed counters.
So if some of the fixed counters are masked out by the hypervisor, it still tries to check/set them.
This patch makes perf behave nicer when the kernel is running under a hypervisor that doesn't expose all the counters.
This patch contains some ideas from Matt Wilson.
Signed-off-by Imre Palik <[email protected]>
Cc Matt Wilson <[email protected]>
--- arch/x86/events/intel/core.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-)
arch/x86/events/intel/core.c +11 -3
@@ -3607,10 +3607,18 @@ __init int intel_pmu_init(void)/* * Quirk: v2 perfmon does not report fixed-purpose events, so -* assume at least 3 events: +* assume at least 3 events, when not running in a hypervisor: */ -if (version >1 ) - x86_pmu.num_counters_fixed =max ((int )edx.split.num_counters_fixed,3 ); +if (version >1 ) { +unsigned int ecx =cpuid_ecx (1 ); + +if (ecx >>31 ) + x86_pmu.num_counters_fixed = + edx.split.num_counters_fixed; +else + x86_pmu.num_counters_fixed = +max ((int )edx.split.num_counters_fixed,3 ); + }if (boot_cpu_has (X86_FEATURE_PDCM )) {u64 capabilities;
Signature · 1 line
2.10.1
Peter Zijlstra
maintainerarch/x86/events/intel/core.c __init int intel_pmu_init(void) · line 3615
Quoted 4 lines · Imre Palik
arch/x86/events/intel/core.c +4
-0+if (version >1 ) { +unsigned int ecx =cpuid_ecx (1 ); + +if (ecx >>31 )
What is this magic, undocumented gunk doing? Is that supposed to be static_cpu_has(X86_FEATURE_HYPERVISOR) ?