doc: Add bindings document for Xilinx LogiCore PR Decoupler
Subsystems (3)
Moritz Fischer
maintainerPATCH v2 1/2 doc: Add bindings document for Xilinx LogiCore PR Decoupler
This adds the binding documentation for the Xilinx LogiCORE PR Decoupler soft core.
---
Changes from v1:
- Added clock names & clock to example
- Merged some of the description from Michal's version
--- .../bindings/fpga/xilinx-pr-decoupler.txt | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt
Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt new file +32 -0
@@ -0,0 +1,32 @@ +Xilinx LogiCORE Partial Reconfig Decoupler Softcore + +The Xilinx LogiCORE Partial Reconfig Decoupler manages one or more +decouplers / fpga bridges. +The controller can decouple/disable the bridges which prevents signal +changes from passing through the bridge. The controller can also +couple / enable the bridges which allows traffic to pass through the +bridge normally. + +The Driver supports only MMIO handling. A PR region can have multiple +PR Decouples which can bhe handled independently or chaines via decouple/ +decouple_status signals. + +Required properties: +- compatible : Should contain "xlnx,pr-decoupler-1.00" +- regs : base address and size for decoupler module +- clocks : input clock to IP +- clock-names : should contain "aclk" + +Optional properties: +- bridge-enable : 0 if driver should disable bridge at startup + 1 if driver should enable bridge at startup + Default is to leave bridge in current state. + +Example: + fpga-bridge at 100000450 { + compatible = "xlnx,pr-decoupler-1.00"; + regs = <0x1000 0x10>; + clocks = <&clkc 15>; + clock-names = "aclk"; + bridge-enable = <0>; + };
Signature · 1 line
2.7.4
Moritz Fischer
maintainerPATCH v2 2/2 fpga: Add support for Xilinx LogiCORE PR Decoupler
This adds support for the Xilinx LogiCORE PR Decoupler soft-ip that does decoupling of PR regions in the FPGA fabric during partial reconfiguration.
---
Changes from v1:
- Added Michal as Co-Author since I pulled in some of his code
- Reworked clk handling in _remove()
- Pulled in Michal's version of show_enable(), ditched priv->enabled
--- drivers/fpga/Kconfig | 9 +++ drivers/fpga/Makefile | 1 + drivers/fpga/xilinx-pr-decoupler.c | 147 +++++++++++++++++++++++++++++++++++++ 3 files changed, 157 insertions(+) create mode 100644 drivers/fpga/xilinx-pr-decoupler.c
drivers/fpga/Kconfig +9 -0
@@ -69,6 +69,15 @@ config ALTERA_FREEZE_BRIDGE isolate one region of the FPGA from the busses while that region is being reprogrammed. +config XILINX_PR_DECOUPLER + tristate "Xilinx LogiCORE PR Decoupler" + depends on FPGA_BRIDGE + help + Say Y to enable drivers for Xilinx LogiCORE PR Decoupler. + The PR Decoupler exists in the FPGA fabric to isolate one + region of the FPGA from the busses while that region is + being reprogrammed during partial reconfig. + endif # FPGA endmenu
drivers/fpga/Makefile +1 -0
@@ -15,6 +15,7 @@ obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o obj-$(CONFIG_FPGA_BRIDGE) += fpga-bridge.o obj-$(CONFIG_SOCFPGA_FPGA_BRIDGE) += altera-hps2fpga.o altera-fpga2sdram.o obj-$(CONFIG_ALTERA_FREEZE_BRIDGE) += altera-freeze-bridge.o +obj-$(CONFIG_XILINX_PR_DECOUPLER) += xilinx-pr-decoupler.o # High Level Interfaces obj-$(CONFIG_FPGA_REGION) += fpga-region.o
drivers/fpga/xilinx-pr-decoupler.c new file +147 -0
147 lines not on this page · raw message
Signature · 1 line
2.7.4
Re: [PATCH v2 2/2] fpga: Add support for Xilinx LogiCORE PR Decoupler
Quoted 126 lines · Moritz Fischer
This adds support for the Xilinx LogiCORE PR Decoupler soft-ip that does decoupling of PR regions in the FPGA fabric during partial reconfiguration.
Signed-off-by Moritz Fischer <[email protected]>Cc Michal Simek <[email protected]>Cc S?ren Brinkmann <[email protected]>Cc linux-kernel at vger.kernel.orgCc devicetree at vger.kernel.org---
Changes from v1:
- Added Michal as Co-Author since I pulled in some of his code
- Reworked clk handling in_remove()
- Pulled in Michal's version ofshow_enable(), ditchedpriv->enabled--- drivers/fpga/Kconfig | 9 +++ drivers/fpga/Makefile | 1 + drivers/fpga/xilinx-pr-decoupler.c | 147 +++++++++++++++++++++++++++++++++++++ 3 files changed, 157 insertions(+) create mode 100644 drivers/fpga/xilinx-pr-decoupler.cdrivers/fpga/Kconfig +9
-0@@ -69,6 +69,15 @@ config ALTERA_FREEZE_BRIDGE isolate one region of the FPGA from the busses while that region is being reprogrammed. +config XILINX_PR_DECOUPLER + tristate "Xilinx LogiCORE PR Decoupler" + depends on FPGA_BRIDGE + help + Say Y to enable drivers for Xilinx LogiCORE PR Decoupler. + The PR Decoupler exists in the FPGA fabric to isolate one + region of the FPGA from the busses while that region is + being reprogrammed during partial reconfig. + endif # FPGA endmenudrivers/fpga/Makefile +1
-0@@ -15,6 +15,7 @@ obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o obj-$(CONFIG_FPGA_BRIDGE) += fpga-bridge.o obj-$(CONFIG_SOCFPGA_FPGA_BRIDGE) += altera-hps2fpga.o altera-fpga2sdram.o obj-$(CONFIG_ALTERA_FREEZE_BRIDGE) += altera-freeze-bridge.o +obj-$(CONFIG_XILINX_PR_DECOUPLER) += xilinx-pr-decoupler.o # High Level Interfaces obj-$(CONFIG_FPGA_REGION) += fpga-region.odrivers/fpga/xilinx-pr-decoupler.c new file +65
-0@@ -0,0 +1,147 @@ +/* +* Copyright (c) 2017, National Instruments Corp. +* Copyright (c) 2017, Xilix Inc +* +* FPGA Bridge Driver for the Xilinx LogiCORE Partial Reconfiguration +* Decoupler IP Core. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; version 2 of the License. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +#include <linux/clk.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/of_device.h> +#include <linux/module.h> +#include <linux/fpga/fpga-bridge.h> + +#define CTRL_CMD_DECOUPLE BIT(0) +#define CTRL_CMD_COUPLE ~BIT(0) + +struct xlnx_pr_decoupler_data { +void __iomem *io_base; +struct clk *clk; +}; + +static int xlnx_pr_decoupler_enable_set (struct fpga_bridge *bridge,bool enable) +{ +int err; +struct xlnx_pr_decoupler_data *priv = bridge->priv; + + err =clk_enable (priv->clk); +if (err) +return err; + +if (enable) +writel (CTRL_CMD_COUPLE , priv->io_base); +else +writel (CTRL_CMD_DECOUPLE , priv->io_base); + +clk_disable (priv->clk); + +return 0 ; +} + +static int xlnx_pr_decoupler_enable_show (struct fpga_bridge *bridge) +{ +const struct xlnx_pr_decoupler_data *priv = bridge->priv; +u32 status; +int err; + + err =clk_enable (priv->clk); +if (err) +return err; + + status =readl (priv->io_base); + +clk_disable (priv->clk); +
drivers/fpga/xilinx-pr-decoupler.c line 75
Quoted 10 lines
drivers/fpga/xilinx-pr-decoupler.c new file +10
-0+return !status; +} + +static struct fpga_bridge_ops xlnx_pr_decoupler_br_ops = { + .enable_set = xlnx_pr_decoupler_enable_set, + .enable_show = xlnx_pr_decoupler_enable_show, +}; + +static const struct of_device_id xlnx_pr_decoupler_of_match[] = { + { .compatible ="xlnx,pr-decoupler-1.00" , },
I would add here that generic compatible string too.
Thanks,
Michal
kbuild test robot
build botRe: [PATCH v2 2/2] fpga: Add support for Xilinx LogiCORE PR Decoupler
In reply to Moritz Fischerurl: https://github.com/0day-ci/linux/commits/Moritz-Fischer/doc-Add-bindings-document-for-Xilinx-LogiCore-PR-Decoupler/20170320-005406 config: ia64-allmodconfig (attached as .config) compiler…
Hi Moritz,
[auto build test WARNING on linus/master]
[also build test WARNING on v4.11-rc2 next-20170310]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Moritz-Fischer/doc-Add-bindings-document-for-Xilinx-LogiCore-PR-Decoupler/20170320-005406
config: ia64-allmodconfig (attached as .config)
compiler: ia64-linux-gcc (GCC) 6.2.0
reproduce:
wget https://raw.githubusercontent.com/01org/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=ia64
All warnings (new ones prefixed by >>):
In file included from include/linux/io.h:25:0,
from drivers/fpga/xilinx-pr-decoupler.c:19:
drivers/fpga/xilinx-pr-decoupler.c: In function 'xlnx_pr_decoupler_enable_set':
arch/ia64/include/asm/io.h:395:30: warning: large integer implicitly truncated to unsigned type [-Woverflow]
#define writel(v,a) __writel((v), (a))
^
>> drivers/fpga/xilinx-pr-decoupler.c:43:3: note: in expansion of macro 'writel'
writel(CTRL_CMD_COUPLE, priv->io_base);
^~~~~~vim +/writel +43 drivers/fpga/xilinx-pr-decoupler.c
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include <linux/clk.h>
> 19 #include <linux/io.h>
20 #include <linux/kernel.h>
21 #include <linux/of_device.h>
22 #include <linux/module.h>
23 #include <linux/fpga/fpga-bridge.h>
24
25 #define CTRL_CMD_DECOUPLE BIT(0)
26 #define CTRL_CMD_COUPLE ~BIT(0)
27
28 struct xlnx_pr_decoupler_data {
29 void __iomem *io_base;
30 struct clk *clk;
31 };
32
33 static int xlnx_pr_decoupler_enable_set(struct fpga_bridge *bridge, bool enable)
34 {
35 int err;
36 struct xlnx_pr_decoupler_data *priv = bridge->priv;
37
38 err = clk_enable(priv->clk);
39 if (err)
40 return err;
41
42 if (enable)
> 43 writel(CTRL_CMD_COUPLE, priv->io_base);
44 else
45 writel(CTRL_CMD_DECOUPLE, priv->io_base);
46 ---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
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kbuild test robot
build botRe: [PATCH v2 2/2] fpga: Add support for Xilinx LogiCORE PR Decoupler
In reply to Moritz Fischerurl: https://github.com/0day-ci/linux/commits/Moritz-Fischer/doc-Add-bindings-document-for-Xilinx-LogiCore-PR-Decoupler/20170320-005406 config: alpha-allyesconfig (attached as .config) compiler…
Hi Moritz,
[auto build test WARNING on linus/master]
[also build test WARNING on v4.11-rc2 next-20170310]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Moritz-Fischer/doc-Add-bindings-document-for-Xilinx-LogiCore-PR-Decoupler/20170320-005406
config: alpha-allyesconfig (attached as .config)
compiler: alpha-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
wget https://raw.githubusercontent.com/01org/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=alpha
All warnings (new ones prefixed by >>):
drivers/fpga/xilinx-pr-decoupler.c: In function 'xlnx_pr_decoupler_enable_set':
>> drivers/fpga/xilinx-pr-decoupler.c:26:26: warning: large integer implicitly truncated to unsigned type [-Woverflow]
#define CTRL_CMD_COUPLE ~BIT(0)
^
>> drivers/fpga/xilinx-pr-decoupler.c:43:10: note: in expansion of macro 'CTRL_CMD_COUPLE'
writel(CTRL_CMD_COUPLE, priv->io_base);
^~~~~~~~~~~~~~~vim +26 drivers/fpga/xilinx-pr-decoupler.c
20 #include <linux/kernel.h>
21 #include <linux/of_device.h>
22 #include <linux/module.h>
23 #include <linux/fpga/fpga-bridge.h>
24
25 #define CTRL_CMD_DECOUPLE BIT(0)
> 26 #define CTRL_CMD_COUPLE ~BIT(0)
27
28 struct xlnx_pr_decoupler_data {
29 void __iomem *io_base;
30 struct clk *clk;
31 };
32
33 static int xlnx_pr_decoupler_enable_set(struct fpga_bridge *bridge, bool enable)
34 {
35 int err;
36 struct xlnx_pr_decoupler_data *priv = bridge->priv;
37
38 err = clk_enable(priv->clk);
39 if (err)
40 return err;
41
42 if (enable)
> 43 writel(CTRL_CMD_COUPLE, priv->io_base);
44 else
45 writel(CTRL_CMD_DECOUPLE, priv->io_base);
46 ---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
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Quoted 30 lines · Moritz Fischer
This adds the binding documentation for the Xilinx LogiCORE PR Decoupler soft core.
Signed-off-by Moritz Fischer <[email protected]>Cc Michal Simek <[email protected]>Cc S?ren Brinkmann <[email protected]>Cc linux-kernel at vger.kernel.orgCc devicetree at vger.kernel.org---
Changes from v1:
- Added clock names & clock to example
- Merged some of the description from Michal's version--- .../bindings/fpga/xilinx-pr-decoupler.txt | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txtDocumentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt new file +5
-0@@ -0,0 +1,32 @@ +Xilinx LogiCORE Partial Reconfig Decoupler Softcore + +The Xilinx LogiCORE Partial Reconfig Decoupler manages one or more +decouplers / fpga bridges. +The controller can decouple/disable the bridges which prevents signal
Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt line 15
Quoted 10 lines
Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt new file +10
-0+changes from passing through the bridge. The controller can also +couple / enable the bridges which allows traffic to pass through the +bridge normally. + +The Driver supports only MMIO handling. A PR region can have multiple +PR Decouples which can bhe handled independently or chaines via decouple/ +decouple_status signals. + +Required properties: +- compatible : Should contain "xlnx,pr-decoupler-1.00"
should
I would tend to do this as "xlnx,pr-decoupler-1.00" and/or "xlnx,pr_decoupler"
Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt line 23
Quoted 8 lines
Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt new file +8
-0+- regs : base address and size for decoupler module +- clocks : input clock to IP +- clock-names : should contain "aclk" + +Optional properties: +- bridge-enable : 0 if driver should disable bridge at startup + 1 if driver should enable bridge at startup + Default is to leave bridge in current state.
Interesting that this is not a bool.
But anyway this should be link to bridge binding because I expect this is the same for all.
Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt line 27
Quoted 4 lines
Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt new file +4
-0+ +Example: + fpga-bridge at 100000450 { + compatible = "xlnx,pr-decoupler-1.00";
"xlnx,pr-decoupler-1.00", "xlnx,pr_decoupler";
Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt line 32
Quoted 6 lines
Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt new file +5
-0+ regs = <0x1000 0x10>; + clocks = <&clkc 15>; + clock-names = "aclk"; + bridge-enable = <0>; + };
Thanks,
Michal